CN109449141A - 半导体封装 - Google Patents

半导体封装 Download PDF

Info

Publication number
CN109449141A
CN109449141A CN201810499679.1A CN201810499679A CN109449141A CN 109449141 A CN109449141 A CN 109449141A CN 201810499679 A CN201810499679 A CN 201810499679A CN 109449141 A CN109449141 A CN 109449141A
Authority
CN
China
Prior art keywords
encapsulation
chip
semiconductor
substrate
antenna
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
CN201810499679.1A
Other languages
English (en)
Inventor
韩府义
周哲雅
郭哲宏
吴文洲
陈南诚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
MediaTek Inc
Original Assignee
MediaTek Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by MediaTek Inc filed Critical MediaTek Inc
Publication of CN109449141A publication Critical patent/CN109449141A/zh
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q21/00—Antenna arrays or systems
    • H01Q21/06—Arrays of individually energised antenna units similarly polarised and spaced apart
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6616—Vertical connections, e.g. vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16141—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged on opposite sides of a substrate, e.g. mirror arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/142—HF devices
    • H01L2924/1421—RF devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Details Of Aerials (AREA)
  • Variable-Direction Aerials And Aerial Arrays (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

本发明公开一种半导体封装，包括：底部芯片封装，具有第一侧和与所述第一侧相对的第二侧，所述底部芯片封装进一步包括第一半导体芯片；以及第一顶部天线封装，安装在底部芯片封装的第一侧上并且具有第一辐射天线元件。采用这种方式，将底部芯片封装和第一顶部天线封装分离开，就可以对底部芯片封装和第一顶部天线封装进行分别设计，以满足两者之间不同的功能和要求，兼容天线和布线的设计要求；本发明可以在底部芯片封装上进行较密集的布线以实现互连，而第一顶部天线封装上则可以布置的较为均匀，从而实现较低的封装成本，较短的前置时间和较好的设计灵活性。

Description

半导体封装
技术领域
本发明涉及半导体技术领域，尤其涉及一种半导体封装。
背景技术
如本领域所知，芯片和天线之间较短的互连(interconnect)在毫米波(mmW，millimeter-wave)应用中越来越关键。为了实现芯片和天线之间更短的互连以及更小的体积和更高的半导体封装集成度，在半导体芯片封装领域中已经开发出了在封装内包含有集成电路(IC)芯片和天线的天线封装(AiP，Antenna in Package)。
遗憾的是，天线和布线之间对基板层的设计要求是非常不同。典型地，通常需要在基板层中使用薄堆积(build-up)层，以便实现薄通孔和密集互连。然而，这种要求与天线设计的要求相矛盾，天线设计通常需要厚的、几乎均匀分布的基板层。
因此，如何提供一种半导体封装以解决上述矛盾，成为本领域亟需解决的问题。
发明内容
有鉴于此，本发明提供一种半导体封装，以更好的兼容天线和布线的设计要求。
根据本发明的一个方面，公开一种半导体封装，包括：
底部芯片封装，具有第一侧和与所述第一侧相对的第二侧，所述底部芯片封装进一步包括第一半导体芯片；以及
第一顶部天线封装，安装在底部芯片封装的第一侧上并且具有第一辐射天线元件。
本发明提供的半导体封装由于包括底部芯片封装和第一顶部天线封装，采用这种方式，将底部芯片封装和第一顶部天线封装分离开，就可以对底部芯片封装和第一顶部天线封装进行分别设计，以满足两者之间不同的功能和要求，兼容天线和布线的设计要求；本发明可以在底部芯片封装上进行较密集的布线以实现互连，而第一顶部天线封装上则可以布置的较为均匀，从而实现较低的封装成本，较短的前置时间和较好的设计灵活性。
在阅读了随后以不同附图展示的优选实施例的详细说明之后，本发明的这些和其它目标对本领域普通技术人员来说无疑将变得明显。
附图说明
图1是示出根据本发明一个实施例的包括安装在底部芯片封装上的分离天线装置的示例性半导体封装1a的示意性横截面图；
图2-9示出了根据本发明各种实施例的如图1所示的一些示例性半导体封装的变型；
图10-13是示出根据本发明的其他实施例的示例性顶部天线封装的示意性截面图；
图14示出了顶部天线封装的示例性扇出型芯片封装。
具体实施方式
在说明书和随后的权利要求书中始终使用特定术语来指代特定组件。正如本领域技术人员所认识到的，制造商可以用不同的名称指代组件。本文件无意于区分那些名称不同但功能相同的组件。在以下的说明书和权利要求中，术语“包括”和“包括”被用于开放式类型，因此应当被解释为意味着“包括，但不限于...”。此外，术语“耦合”旨在表示间接或直接的电连接。因此，如果一个设备耦合到另一设备，则该连接可以是直接电连接，或者经由其它设备和连接的间接电连接。
以下描述是实施本发明的最佳设想方式。这一描述是为了说明本发明的一般原理而不是用来限制的本发明。本发明的范围通过所附权利要求书来确定。
下面将参考特定实施例并且参考某些附图来描述本发明，但是本发明不限于此，并且仅由权利要求限制。所描述的附图仅是示意性的而并非限制性的。在附图中，为了说明的目的，一些元件的尺寸可能被夸大，而不是按比例绘制。在本发明的实践中，尺寸和相对尺寸不对应于实际尺寸。
术语“晶粒(die)”，“芯片(chip)”，“半导体芯片”和“半导体晶粒”在整个说明书中可互换使用，以表示集成电路芯片或晶粒。本文使用的术语“水平”可以定义为平行于平面或表面(例如基板的表面)的方向，而不管它的朝向如何。如本文所使用的术语“垂直”可以指与刚刚描述的水平方向正交的方向。而例如“在…上”，“在…上方”，“在…下”，“底部”，“顶部”，“侧”(例如“侧壁”)，“较高”，“较低”，“之上”和“之下”，均可以参考水平面。
本发明涉及一种半导体封装，包括安装在底部半导体芯片封装(或底部芯片封装)上的至少一个分离(discrete)天线装置(或顶部天线封装)，由此形成天线叠层封装结构。根据本发明一些实施例，本文中各种实施例中公开的示例性半导体封装提供了包括但不限于：与常规的在封装中的天线相比，具有更低的封装成本，更短的前置时间(lead-time)和/或更好的设计灵活性的优点。
具体来说，现有技术中，包含有集成电路芯片和天线的封装体为了兼容这两种结构，封装体中会留出更多个较薄的薄基板层，为集成电路芯片设置更多的布线；同时封装体较厚也可以为天线留出较厚的厚基板层，以承载天线的设计。因此现有技术中的封装体会制造的较厚、体积较大，从而容纳数量较多的薄基板层以及较厚的厚基板层，例如封装体可能需要12层基板层，以满足包括集成电路芯片和天线的封装体的需求。
而本发明中将顶部天线封装与底部芯片封装分离开，就可以将这两个结构分开制造成型后再组装在一起。这样可以根据顶部天线封装与底部芯片封装各自不同的功能和要求进行设计和制造，而无需将封装体做的较厚去兼容其他的结构，所以顶部天线封装与底部芯片封装中每一个都可以做的较薄，例如现有的封装体需要12层基板层，而本发明中封装相同的芯片和天线只需要6层基板层(底部芯片封装)和2层基板层(顶部天线封装)即可，因此本发明中需要的材料相比现有技术更少，需要的制程也更少，从而大大降低了生产、封装成本。此外，顶部天线封装与底部芯片封装可分开制造成型，这样就可以同时生产顶部天线封装与底部芯片封装之后，再组装得到半导体封装，而现有技术中一整个封装体仅能按照流程在一条流水线生产，因此本发明中顶部天线封装与底部芯片封装分离可以加快生产效率，具有更短的前置时间。并且本发明中顶部天线封装与底部芯片封装分离，用户或设计人员可根据需要对封装进行组合，以满足不同的需求。例如可以将多个底部芯片封装连接在一起使用，或根据需求选择多个底部芯片封装和顶部天线封装组合在一起使用，适应不同的应用场景和用户需求，因此本发明的方案增加了设计弹性，具有更好的设计灵活性，可以满足更广泛的使用需求。
图1是示出根据本发明一个实施例的包括安装在底部芯片封装上的分离天线装置的示例性半导体封装1a的示意性横截面图。根据一个实施例，半导体封装可以是无线模块，并且分离天线装置可以是天线封装。如图1所示，半导体封装1a包括底部芯片封装10和安装在底部芯片封装10上的顶部天线封装20。底部芯片封装10具有第一侧10a和与第一侧10a相对的第二侧10b。顶部天线封装20可以安装在第一侧10a上。底部芯片封装10可以包括安装在第二侧10b上的半导体芯片(或半导体晶粒)30。例如，半导体芯片30可以是RFIC(RadioFrequency Integrated Circuit，射频集成电路)芯片，基带(base-band)集成电路芯片和/或系统单芯片(SOC，System-in-Chip)晶粒，但不限于此。此外半导体芯片30的数量不限于一个，也可以是两个或更多个，本实施例中其余的实施方式中半导体芯片的数量也不限于一个，可以是两个或更多个。另外，还可以设置模塑料覆盖半导体芯片30，以保护半导体芯片；模塑料还可以设置在顶部天线封装20与底部芯片封装10之间，以提高半导体封装的机械强度。
根据一个实施例，底部芯片封装10可以包括封装基板100，封装基板100具有带有一个或多个导电通孔112的芯部110，以及一个或多个堆积(build-up)层120。导电通孔112可以是电镀(plate)通孔，或其他可以导电的结构，本文中其他的导电通孔也可以是电镀通孔或其他可以导电的结构。导电通孔112中可以设置导电迹线114以实现导电的功能。堆积层120可以具有一个或多个形成在堆积层中的通孔122和/或导电迹线114，以在整个底部芯片封装10中布设信号、接地和/或电力，也就是导电迹线114可以从导电通孔112延伸到通孔122，以提供从导电通孔112至堆积层120的电连接。堆积层120可以在芯部110的相对的两侧均有设置。在底部的堆积层120的底表面(靠近第二侧10b的表面)上的导电迹线124采用一个或多个焊盘的形式，半导体芯片30可以与导电元件312连接在该焊盘上。例如，导电元件312可以包括焊球、焊料凸块、铜凸块、金凸块或其他任何适合的导电装置。导电迹线114可以连接至导电迹线124。此外导电迹线114也可以是与导电迹线124一体的，或者在不同的制程中分开形成的。导电迹线124上的焊盘可以是仅在导电迹线124上留出空位，而不做任何特殊的处理，例如焊盘区域与导电迹线124的其他区域是平齐的。当然也可以做其他处理，例如在导电迹线124上做出凸台或凹槽以用作焊盘；当然也可以将焊盘区域处理的更粗糙或更光滑，或设置若干小凸块等等。
例如，芯部110可以包括任何适合的材料，包括玻璃纤维片(fiberglass sheet)、预浸材料(prepreg)、FR-4材料、FR-5材料或它们的组合的环氧层压板(epoxy laminate)。导电迹线114，124、导电通孔112和导电通孔122可以包括任何适合的导电材料，包括铜、银、金、镍或它们的组合。堆积层120可以包括任何适合的介电材料，包括聚酰亚胺(polyimide)、预浸材料、聚合物(polymer)等。
根据一个实施例，底部芯片封装10可以进一步包括在第一侧10a和第二侧10b上的阻焊层(solder mask layer)130。为了互连的目的，阻焊层130可以包括用于暴露导电迹线124中相应的焊盘的开口。根据一个实施例，导电元件140的阵列可以设置在底部芯片封装10的第二侧10b上以便进一步与印刷电路板或主板的互连。
顶部天线封装20可以包括基板210。顶部天线封装20通过导电元件240电耦合到底部芯片封装10，导电元件240以一个或多个焊盘的形式耦合到堆积层120的顶表面(靠近第一侧10a的表面)上的导电迹线124，并且导电元件240以一个或多个焊盘的形式耦合到在基板210的底表面(朝向堆积层120的表面)上的导电迹线214。例如，导电元件240可以包括焊球、焊料凸块、铜凸块、金凸块或其他任何适合的导电装置。此外，基板210可以包括一个或多个导电通孔(例如电镀通孔)212以将信号从基板210的一侧按路线发送到基板210的另一侧。
例如，基板210可以是陶瓷(ceramic)基板、半导体基板、电介质(dielectric)基板、玻璃基板，但不限于此。根据本发明的实施例，顶部天线封装20可以是低温共烧陶瓷(LTCC，low temperature co-fired ceramic)，倒装芯片尺寸封装(FCCSP，flip-chipchip-scale-package)或扇出型芯片封装(fan-out type chip package)。
根据一个实施例，顶部天线封装20不包括半导体芯片或晶粒。顶部天线封装20还可以包括设置在基板210的表面上的导电迹线214中的辐射天线(radiative antenna)元件220。辐射天线元件220可以包括天线阵列或用于辐射和/或接收电磁信号(例如RF无线信号或毫米波(mmW)信号)的机构。尽管在该图中没有示出，但应该理解的是，辐射天线元件220可以根据设计要求设置在基板210的底表面处，或侧表面等其他位置处。例如，辐射天线元件220可以是任何适合的类型，例如贴片(patch)天线、缝隙耦合(slot-coupled)天线、堆叠式(stacked)贴片、偶极天线(dipole)、单极天线(monopole)等，并且可以具有不同的取向(orientation)和/或极化(polarization)。在一些实施例中，辐射天线元件220可以通过设置于基板210内的一个或多个导电通孔212或其他导电迹线将信号从基板210的一侧按路线发送到基板210的另一侧。
此外，辐射天线元件220可以包括多个天线模块，例如双频带(dual-band)天线元件和单频带(single-band)天线元件，并不限于此。
图2-9示出了根据本发明各种实施例的如图1所示的一些示例性半导体封装的变型，其中相同的数字标号表示相同的层、区域或元件。应该理解的是，除非另外特别指出，否则以下描述的各种示例性实施例的特征可以彼此组合。
如图2所示，半导体封装1b和半导体封装1a之间的差别在于，半导体封装1b的半导体芯片30设置在与顶部天线封装20相同的一侧上。例如，半导体芯片30和顶部天线封装20都安装在底部芯片封装10的第一侧10a上。当然，半导体芯片30和顶部天线封装20也可以都安装在底部芯片封装10的第二侧10b上。同样，半导体芯片30可以通过导电元件312与导电迹线124中相应的焊盘连接。虽然未在附图中示出，应该理解的是，可以在半导体芯片30和底部芯片封装10的第一侧10a之间设置底部填充层，例如可以使用模塑料或其他适合的材料作为底部填充层。在非限制性示例中，半导体芯片30可以直接安装在顶部天线封装20之下。将半导体芯片30和顶部天线封装20安装在同一侧，半导体芯片与顶部天线封装之间的信号传输距离更短，可以提高信号的处理效率。
如图3所示，并简要地参照图2，半导体封装1c与半导体封装1b之间的区别在于，半导体封装1c还包括位于顶部天线封装20与底部芯片封装10之间的模塑料410。根据一个实施例中，模塑料410可以包含环氧树脂或聚合物，但不限于此。模塑料410可以覆盖并封装半导体芯片30。根据一个实施例，模塑料410可以填充到半导体芯片30和底部芯片封装10的第一侧10a之间的间隙中。可以填充模塑料作为底部填充层。根据一个实施例，模塑料410可以包括贯穿模塑通孔410a。导电元件240可以设置在相应的贯穿模塑通孔410a内，贯穿模塑通孔410a可通过设置在其中的导电元件240为顶部天线封装20与底部芯片封装10提供电连接。使用模塑料可以进一步保护半导体芯片，并且使得半导体封装整体的机械强度更高，以及提高半导体封装的结构稳定性和耐用性。
如图4所示，并简要地参照图2，半导体封装1d和半导体封装1b之间的区别在于，半导体封装1d的半导体芯片30嵌入到封装基板100的芯部110中。应该理解的是，半导体芯片30也可以直接嵌入在堆积层120中。例如，半导体芯片30可以安装在封装基板100的芯部110上并且嵌入在电介质层(或介电层)的层内。在另一个实施例中，可以在封装基板100中形成空腔(图未示)，并且将半导体芯片30放置在该空腔内。半导体芯片30可以通过传统的接合(bonding)技术接合，例如使用引线或导电迹线与封装件基板100的导电迹线或其他导电结构连接。将半导体芯片嵌入在封装基板内可以为半导体芯片提供更可靠的保护，并且可以节省空间，减小整体半导体封装的体积，有助于半导体封装的小型化。
如图5所示，半导体封装1e包括多个半导体芯片，例如可以分别设置在底部芯片封装10的第一侧10a和第二侧10b上的半导体芯片30a和半导体芯片30b。半导体芯片30a可以通过导电元件312a电连接到封装件基板100。半导体芯片30b可以通过导电元件312b电连接到封装件基板100。此外，还可以继续在封装基板100内设置半导体芯片，例如如图4所示的在封装基板100的芯部110嵌入另外的半导体芯片。设置多个半导体芯片可以提高半导体封装的集成度，提高半导体封装的处理性能，并且可以增加半导体封装的设计弹性，设计人员或用户可根据自身需求和应用场景进行选择，从而使半导体封装适用于更多的场景，满足不同的需求。
如图6所示，半导体封装1f包括多个半导体芯片，例如半导体芯片30a和半导体芯片30b。半导体芯片30a可以设置在底部芯片封装10的第一侧10a上。半导体芯片30b可以嵌入封装基板100中。当然半导体芯片30a也可以设置在底部芯片封装10的第二侧10b上。半导体芯片30b嵌入到封装基板100中可以更好的保护半导体芯片30b，并避免半导体芯片30b占用表面位置，节省空间。
如图7所示，类似地，半导体封装1g包括底部芯片封装10和安装在底部芯片封装10的第一侧10a上的顶部天线封装20。根据所示实施例，顶部天线封装20在尺寸上可以比底部芯片封装10更大。此外，半导体芯片30可以设置在底部芯片封装10的第一侧10a上。当然，类似于图1和图4所示，在底部芯片封装10的第二侧10b上以及在封装基板100内设置额外的半导体芯片。较大的顶部天线封装尺寸可以提高收发信号的面积，提供更高的信号强度。当然顶部天线封装20的尺寸也可以与底部芯片封装10的尺寸相同，如图1至图6所示，这里的尺寸是指长宽的尺寸。顶部天线封装20的厚度与底部芯片封装10的厚度可以不同，例如顶部天线封装20较薄而底部芯片封装10厚，当然厚度也可以相等，或者顶部天线封装20较厚而底部芯片封装10薄。
如图8所示，半导体封装1h包括底部芯片封装10和安装在底部芯片封装10的第一侧10a上的多个顶部天线封装，例如顶部天线封装20a和顶部天线封装20b。半导体芯片30可以安装在底部芯片封装10的第二侧10b上。根据所示实施例，顶部天线封装20a和20b的尺寸可以小于底部芯片封装10的尺寸。具体的，可以是顶部天线封装20a的尺寸小于底部芯片封装10的尺寸，顶部天线封装20b的尺寸小于底部芯片封装10的尺寸。此外，半导体芯片30可以设置在底部芯片封装10的第二侧10b上。当然，类似于图1和图4所示，在底部芯片封装10的第一侧10a上以及在封装基板100内设置额外的半导体芯片。在底部芯片封装10的第一侧10a上设置半导体芯片时，可以设置两个，例如分别在顶部天线封装20a和20b的下方设置。此外在封装基板100内设置半导体芯片时，也可以不限制数量，例如设置两个或更多个。顶部天线封装20b可以具有与顶部天线封装20a相同或相似的层级和结构，关于顶部天线封装20b的结构可参考上述对顶部天线封装20a的描述，因此不再赘述。设置多个顶部天线封装，可以对不同的顶部天线封装设置不同的功能，从而满足多功能的要求，并且提高半导体封装的集成度，并且可以增加半导体封装的设计弹性，以满足不同的需求。
如图9所示，半导体封装1i包括底部芯片封装10和安装在底部芯片封装10的第一侧10a上的顶部天线封装20。顶部天线封装20可以包括设置在基板210的表面上的导电迹线214中的辐射天线元件220。辐射天线元件220可以包括天线阵列或用于辐射和/或接收电磁信号(例如RF无线信号或毫米波(mmW)信号)的机构。如图9所示，顶部天线封装20的尺寸也可以小于底部芯片封装10的尺寸，这里的尺寸是指长宽的尺寸。
半导体封装1i还可以包括设置在底部芯片封装10的第一侧10a上的导电迹线124中的辐射天线元件520。辐射天线元件520不与辐射天线元件220重叠(在竖直方向上的位置相互错开)。在非限制性的示例中，辐射天线元件220可以是双频带天线元件，并且辐射天线元件520可以是单频带天线元件。采用这种方式，可以综合分离天线和集成在底部芯片封装的天线的优势，从而保证收发信号的稳定，并且可以增加半导体封装的设计弹性，以满足不同的需求。
使用本发明是有优势的，因为通过与底部芯片封装10分隔开形成顶部天线封装20，可以实现较低的封装成本，较短的前置时间和较好的设计灵活性。顶部天线封装20和底部芯片封装10可以使用对于半导体封装相对来说可能最佳的材料、结构和/或工艺来制造。例如，底部芯片封装10可以用多层互连(例如在芯部110的任一侧上的多个堆积层)制造以适应密集布线。另一方面，在本实施例中，顶部天线封装20可以仅具有单层(例如一侧具有焊盘接口并且另一侧具有辐射天线元件的电介质带)。在非限制性示例中，可以在底部芯片封装10中使用低k电介质从而以减少寄生效应(例如减少的电阻-电容(RC，resistive-capacitive)延迟)的按照路线发送信号，而相对较高k材料可以用于顶部天线封装20以实现减小外形尺寸(form factor)的天线。
图10-13是示出了根据本发明的其他实施例的一些示例性顶部天线封装的示意性截面图，其中相同的数字标号表示相同的层、区域或元件。应该理解的是，除非另外特别指出，否则这里描述的各种示例性实施例的特征可以彼此组合。为了简单起见，图中仅示出了示例性顶部天线封装的相关部分。
应该理解的是，如图10-13所示的结构或特征不限于顶部天线封装。应该理解的是，如前面图中所示，图10-13所示的结构或特征可以用于底部芯片封装10中。还应该理解的是，在不脱离本发明的精神和范围的情况下，图10-13的一个图中描绘的一些特征可以与图10-13的另一个图中的其他特征组合。
如图10所示，顶部天线组件2a包括基板210。例如，基板210可以是陶瓷基板、半导体基板、电介质基板、玻璃基板，但不限于此。导电迹线214分别形成在基板210的两个相对的表面上。基板210可以包括一个或多个导电通孔(例如电镀通孔)212，以将信号从基板210的一侧按路线发送到基板210的另一侧。根据本发明的实施例，例如，顶部天线封装2a可以是具有芯片或电子元件的封装。在基板210的一个表面上，例如基板210的底表面上，可以在基板210的底表面上设置重布线(re-wiring)层300。
在非限制性示例中，重布线层300可以包括层压在基板210的底表面上的电介质层320，在电介质层320上的导电层340和在导电层340上的保护层360。电介质层320可以包括任何适合的绝缘层，例如氧化硅、氮化硅、聚酰亚胺等。导电层340可以包括铜、银或其他合金等，但不限于此。保护层360可以包括任何适合的钝化层或阻焊层。导电层340可以通过电介质层320中的导电通孔322电连接到导电迹线214。在非限制性示例中，半导体芯片40可以安装在重布线层300上。半导体芯片40可以通过接触元件342和导电元件412电连接到导电层340。在其他一些实施例中，半导体芯片40可以省略。
辐射天线元件220可以设置在基板210的表面上的导电迹线214中，例如基板210的顶表面上。辐射天线元件220可以包括天线阵列或用于辐射和/或接收电磁信号(例如RF无线信号或毫米波(mmW)信号)的机构。尽管在该图中没有示出，但应该理解的是，辐射天线元件220可以根据设计要求设置在基板210的底表面处，或侧表面等其他位置处。例如，辐射天线元件220可以是任何适合的类型，例如贴片天线、缝隙耦合天线、堆叠式贴片、偶极天线、单极天线等，并且可以具有不同的取向和/或极化。
如图11所示，类似地，顶部天线封装2b包括芯部或基板210。例如，基板210可以是陶瓷基板、半导体基板、电介质基板、玻璃基板，但不限于此。电介质层520和导电迹线214，224均分别形成在基板210的两个相对的表面上。可以设置保护层560以覆盖导电迹线224和电介质层520。电介质层520可以包括任何适合的绝缘层，例如氧化硅、氮化硅、聚酰亚胺等。保护层560可以包括任何适合的钝化层或阻焊层。基板210可以包括一个或多个导电通孔(例如电镀通孔)212以将信号从基板210的一侧按线路发送到基板210的另一侧。
根据本发明的实施例，例如，顶部天线封装2b可以是嵌入式芯片(embedded-chip)封装，嵌入式芯片封装是嵌入有半导体芯片40的封装。在非限制性示例中，半导体芯片40可以嵌入在基板210中。半导体芯片40可以通过接触元件422电连接到导电迹线214。此外还可以设置多个半导体芯片，例如可以在顶部天线封装2b的相对的两侧分别设置半导体芯片，以及在顶部天线封装2b的内部设置半导体芯片封装。在其他一些实施例中，半导体芯片40可以省略。半导体芯片40嵌入到基板210中可以更好的保护半导体芯片40，并避免半导体芯片40占用表面位置，节省空间。
辐射天线元件220可以设置在基板210上的导电迹线224中，例如设置在基板210的顶表面上。辐射天线元件220可以包括天线阵列或用于辐射和/或接收电磁信号(例如RF无线信号或毫米波(mmW)信号)的机构。尽管在该图中没有示出，但应该理解的是，辐射天线元件220可以根据设计要求设置在基板210的底表面处，或侧表面等其他位置处。例如，辐射天线元件220可以是任何适合的类型，例如贴片天线、缝隙耦合天线、堆叠式贴片、偶极天线、单极天线等，并且可以具有不同的取向和/或极化。
如图12所示，顶部天线封装2c可以是扇出型芯片封装，其中至少一些封装焊盘和/或将芯片连接到封装焊盘的导线位于芯片轮廓的横向外侧或者至少与芯片的轮廓相交。这样可以提高更多的导电层、导电元件，方便顶部天线封装与其他部件如主板、电路板等的连接。此外，顶部天线封装2c可以是晶圆级芯片尺寸封装(WLCSP，wafer level chip scalepackage)。在非限制性示例中，顶部天线封装2c可以包括由第一模塑料61封装的半导体芯片40。第一模塑料61可以覆盖半导体芯片40的无源(inactive)底部表面和四个侧壁表面，并且可以暴露半导体芯片40的有源(inactive)表面上。在半导体芯片40的有源表面上，设置有多个接合焊盘或输入/输出(I/O，input/output)焊盘402。在其他一些示例中，可以省略半导体芯片40。
重分布层(RDL，re-distribution layer)结构600可以设置在半导体芯片40的有源表面上和第一模塑料61的表面上，并且可以电连接到半导体芯片40的I/O焊盘402。在非限制性示例中，RDL结构600可以包括电介质层601，603和605以及在电介质层601，603和605中的导电层602，604。至少一个导电元件640例如焊料凸块，焊球或金属凸块/柱可以形成在电介质层605上以用于进一步地连接。电介质层601，603和605可以包括任何适合的绝缘层，例如氧化硅、氮化硅、聚酰亚胺等。导电层602，604可以包括铜、银或其他合金等，但不限于此。
在非限制性示例中，顶部天线封装2c可以包括第一模塑料61上的导电迹线614，在第一模塑料61和导电迹线614上的第二模塑料62，在第二模塑料62上的导电迹线624，在第二模塑料62和导电迹线624上的第三模塑料63，以及在第三模塑料63上的导电迹线634。贯穿模塑通孔612可以设置在第一模塑料61中用于RDL结构600与导电迹线614，624和634之间的信号传输，当然贯穿模塑通孔612是导电的通孔。采用这种结构，将重分布层设置在半导体芯片和第一模塑料上，不仅可以保护半导体芯片，还可以让顶部天线封装结构的更加紧凑，提高顶部天线封装的机械强度和稳固性。
辐射天线元件620可以设置在导电迹线624，634中。辐射天线元件620可以包括天线阵列或用于辐射和/或接收电磁信号(例如RF无线信号或毫米波(mmW)信号)的机构。尽管在该图中没有示出，但是应该理解的是，辐射天线元件620可以根据设计要求设置在导电迹线614，624和634的任何层中。例如，辐射天线元件620可以是任何适合的类型，例如贴片天线、缝隙耦合天线、堆叠式贴片、偶极天线、单极天线等，并且可以具有不同的取向和/或极化。
如图13所示，顶部天线封装2d可以具有与图12所示的类似的堆叠结构。图12中所示的顶部天线封装2d和顶部天线封装2c之间的区别在于顶部天线封装2d的半导体芯片40外部的安装在RDL结构600上。同样地，辐射天线元件620可以设置在导电迹线624，634中。辐射天线元件220可以包括天线阵列或用于辐射和/或接收电磁信号(例如RF无线信号或毫米波(mmW)信号)的机构。尽管在该图中没有示出，但是应该理解的是，辐射天线元件620可以根据设计要求设置在导电迹线614，624和634的任何层中。例如，辐射天线元件620可以是任何适合的类型，例如贴片天线、缝隙耦合天线、堆叠式贴片、偶极天线、单极天线等，并且可以具有不同的取向和/或极化。在其他一些示例中，可以省略半导体芯片40。将半导体芯片40安装在RDL结构之外，将会方便半导体芯片40的安装，便于顶部天线封装的制造。
例如，图14示出用于顶部天线封装的示例性扇出型芯片封装2e。如图14所示，扇出型芯片封装2e是嵌入有半导体芯片40的封装，其中至少一些封装焊盘724和/或将半导体芯片40连接到封装焊盘724的导线714位于半导体芯片40的轮廓的横向外侧或者至少与半导体芯片40的轮廓相交。扇出型芯片封装2e可以包括封装侧壁和芯片的无源上表面的模塑料710。半导体芯片40的有源表面未被模塑料710覆盖。半导体芯片40的有源表面上的输入/输出(I/O)焊盘402电连接到重分布层(RDL)结构700，RDL结构700构造在半导体芯片40的有源表面上和模塑料710的下表面上。RDL结构700包括至少一个电介质层720，在至少一个电介质层720中的导电线路714(导电线路714用于将半导体芯片40的I/O焊盘402连接至封装焊盘724)，以及在至少一个电介质层720中或在至少一个电介质层720上的至少一个辐射天线元件722。导电元件240例如凸块或者焊球，可以设置在封装焊盘724上用于进一步地连接。在其他一些示例中，可以省略半导体芯片40。此外，与图12或图13相比，图中暂未示出如上所述的导电迹线以及可设置在导电迹线中的辐射天线元件等，图14中可采用与图12和图13相类似或相同的导电迹线、辐射天线元件等结构。采用导电线路连接I/O焊盘与封装焊盘将节省生产步骤，从而降低成本。
本领域的技术人员将容易地观察到，在保持本发明教导的同时，可以做出许多该装置和方法的修改和改变。因此，上述公开内容应被解释为仅由所附权利要求书的界限和范围所限制。

Claims (18)

1.一种半导体封装，其特征在于，包括：
底部芯片封装，具有第一侧和与所述第一侧相对的第二侧，所述底部芯片封装进一步包括第一半导体芯片；以及
第一顶部天线封装，安装在底部芯片封装的第一侧上并且具有第一辐射天线元件。
2.根据权利要求1所述的半导体封装，其特征在于，所述第一半导体芯片包括射频集成电路芯片和/或系统单芯片晶粒。
3.根据权利要求1所述的半导体封装，其特征在于，所述底部芯片封装包括封装基板和至少一个堆积层，所述封装基板包括带有至少一个导电通孔的芯部。
4.根据权利要求3所述的半导体封装，其特征在于，所述堆积层包括至少一个通孔和在所述通孔中的第一导电迹线，所述第一导电迹线用于在整个底部芯片封装中布设信号、接地和/或电力。
5.根据权利要求4所述的半导体封装，其特征在于，所述堆积层的底表面上设有第二导电迹线，所述第二导电迹线上设有焊盘，所述焊盘上连接有导电元件，所述半导体芯片与所述导电元件连接。
6.根据权利要求3所述的半导体封装，其特征在于，所述芯部包括玻璃纤维片、预浸材料、FR-4材料、FR-5材料或它们的组合的环氧层压板。
7.根据权利要求1所述的半导体封装，其特征在于，所述第一顶部天线封装包括基板，所述基板包括陶瓷基板、半导体基板、电介质基板或玻璃基板。
8.根据权利要求1所述的半导体封装，其特征在于，所述第一顶部天线封装包括基板，所述基板包括至少一个导电通孔以将信号从所述基板的一侧按路线发送至所述基板的另一侧。
9.根据权利要求1所述的半导体封装，其特征在于，所述第一顶部天线封装包括基板，所述第一辐射天线元件设置在所述基板的表面上。
10.根据权利要求1所述的半导体封装，其特征在于，所述第一顶部天线封装是低温共烧陶瓷、倒装芯片尺寸封装或扇出型芯片封装。
11.根据权利要求1所述的半导体封装，其特征在于，所述第一半导体芯片安装在所述底部芯片封装的第一侧或第二侧上，或安装在所述底部封装芯片内。
12.根据权利要求1所述的半导体封装，其特征在于，所述第一顶部天线封装和所述底部芯片封装之间设有模塑料，其中所述模塑料覆盖并封装所述第一半导体芯片。
13.根据权利要求12所述的半导体封装，其特征在于，所述模塑料中设有用于将所述第一顶部天线封装与所述底部芯片封装电连接的贯穿模塑通孔。
14.根据权利要求1所述的半导体封装，其特征在于，还设有安装在所述底部芯片封装上的第二半导体芯片；
所述第一半导体芯片设置在所述底部芯片封装的第一侧上，所述第二半导体芯片设置在所述底部芯片封装的第二侧上；或者所述第一半导体芯片设置在所述底部芯片封装的第一侧或第二侧上，所述第二半导体芯片设置在所述底部芯片封装内。
15.根据权利要求1所述的半导体封装，其特征在于，所述第一顶部天线封装的尺寸大于所述底部芯片封装的尺寸。
16.根据权利要求1所述的半导体封装，其特征在于，还包括安装在所述底部芯片封装上的第二顶部天线封装。
17.根据权利要求9所述的半导体封装，其特征在于，还包括设置在所述底部芯片封装的第一侧上的第二辐射天线元件。
18.根据权利要求17所述的半导体封装，其特征在于，所述第一辐射天线元件是双频带天线元件，所述第二辐射天线元件是单频带天线元件。
CN201810499679.1A 2017-06-07 2018-05-23 半导体封装 Withdrawn CN109449141A (zh)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US201762516150P 2017-06-07 2017-06-07
US62/516,150 2017-06-07
US201762579947P 2017-11-01 2017-11-01
US62/579,947 2017-11-01
US201762584155P 2017-11-10 2017-11-10
US62/584,155 2017-11-10
US15/974,700 2018-05-09
US15/974,700 US10847869B2 (en) 2017-06-07 2018-05-09 Semiconductor package having discrete antenna device

Publications (1)

Publication Number Publication Date
CN109449141A true CN109449141A (zh) 2019-03-08

Family

ID=62245190

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810499679.1A Withdrawn CN109449141A (zh) 2017-06-07 2018-05-23 半导体封装

Country Status (4)

Country Link
US (2) US10847869B2 (zh)
EP (2) EP3413347B1 (zh)
CN (1) CN109449141A (zh)
TW (1) TW201903994A (zh)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110277356A (zh) * 2018-03-16 2019-09-24 中芯长电半导体（江阴）有限公司 天线馈电线的封装结构及封装方法
CN111430327A (zh) * 2020-03-05 2020-07-17 广东工业大学 一种高散热扇出型封装结构及封装方法
CN111786074A (zh) * 2019-04-04 2020-10-16 三星电机株式会社 天线模块
CN112018101A (zh) * 2019-05-28 2020-12-01 联发科技股份有限公司 半导体封装
WO2021042377A1 (zh) * 2019-09-06 2021-03-11 深圳市汇顶科技股份有限公司 集成装置及其制备方法
CN113302801A (zh) * 2019-05-30 2021-08-24 华为技术有限公司 封装结构、网络设备以及终端设备
WO2022007245A1 (zh) * 2020-07-08 2022-01-13 瑞声声学科技(深圳)有限公司 射频模组
WO2022007180A1 (zh) * 2020-07-08 2022-01-13 瑞声声学科技(深圳)有限公司 射频模组
CN114284738A (zh) * 2020-09-28 2022-04-05 联发科技股份有限公司 天线结构和天线封装
US11509038B2 (en) 2017-06-07 2022-11-22 Mediatek Inc. Semiconductor package having discrete antenna device
CN115425394A (zh) * 2022-08-05 2022-12-02 中国电子科技集团公司第十四研究所 一种基于层叠式结构的带状线以及基于异质基材三维堆叠的层叠式阵面天线单元
US11721882B2 (en) 2017-06-07 2023-08-08 Mediatek Inc. Semiconductor package having discrete antenna device

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2491447B (en) * 2010-03-24 2014-10-22 Murata Manufacturing Co RFID system
US10886594B2 (en) * 2018-03-16 2021-01-05 Sj Semiconductor (Jiangyin) Corporation Packaging structure and packaging method for antenna
US11043730B2 (en) * 2018-05-14 2021-06-22 Mediatek Inc. Fan-out package structure with integrated antenna
US11024954B2 (en) 2018-05-14 2021-06-01 Mediatek Inc. Semiconductor package with antenna and fabrication method thereof
US20190348747A1 (en) 2018-05-14 2019-11-14 Mediatek Inc. Innovative air gap for antenna fan out package
US11081453B2 (en) 2018-07-03 2021-08-03 Mediatek Inc. Semiconductor package structure with antenna
JP7091961B2 (ja) * 2018-09-13 2022-06-28 Tdk株式会社 オンチップアンテナ
US12015191B2 (en) * 2019-02-08 2024-06-18 Texas Instruments Incorporated Antenna-on-package integrated circuit device
US10903157B2 (en) * 2019-03-08 2021-01-26 Skc Co., Ltd. Semiconductor device having a glass substrate core layer
WO2020200444A1 (en) * 2019-04-03 2020-10-08 Huawei Technologies Co., Ltd. Partitioning of antenna device
WO2020200458A1 (en) * 2019-04-04 2020-10-08 Huawei Technologies Co., Ltd. Antenna device and method of its fabrication
TWI696255B (zh) * 2019-04-09 2020-06-11 矽品精密工業股份有限公司 電子封裝件及其製法
US10903561B2 (en) * 2019-04-18 2021-01-26 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
KR102593888B1 (ko) * 2019-06-13 2023-10-24 삼성전기주식회사 안테나 모듈 및 이를 포함하는 전자기기
US11508678B2 (en) 2019-08-01 2022-11-22 Mediatek Inc. Semiconductor package structure including antenna
TWI700801B (zh) * 2019-09-16 2020-08-01 矽品精密工業股份有限公司 電子封裝件及其製法
US11101541B2 (en) * 2019-10-03 2021-08-24 Advanced Semiconductor Engineering, Inc. Semiconductor assembly and method for manufacturing the same
US12021031B2 (en) 2019-11-27 2024-06-25 Mediatek Inc. Semiconductor package structure
CN113140887B (zh) * 2020-01-17 2022-11-22 清华大学 封装天线及其制造方法
US11239217B2 (en) * 2020-03-30 2022-02-01 Nanya Technology Corporation Semiconductor package including a first sub-package stacked atop a second sub-package
DE102021107672A1 (de) * 2020-04-07 2021-10-07 Mediatek Inc. Halbleiter-package-struktur
US11670596B2 (en) 2020-04-07 2023-06-06 Mediatek Inc. Semiconductor package structure
US11830851B2 (en) 2020-04-07 2023-11-28 Mediatek Inc. Semiconductor package structure
DE102021107982B4 (de) * 2020-04-07 2024-02-22 Mediatek Inc. Halbleiter-packagestruktur
KR20210131477A (ko) 2020-04-23 2021-11-03 삼성전자주식회사 반도체 장치
JP2022099099A (ja) * 2020-12-22 2022-07-04 富士フイルム株式会社 非接触式通信媒体
CN114024134B (zh) * 2021-10-26 2024-02-06 安徽蓝讯无线通信有限公司 一种用于通讯天线的ltcc封装结构

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104037166A (zh) * 2013-03-07 2014-09-10 日月光半导体制造股份有限公司 包含天线层的半导体封装件及其制造方法
CN104701269A (zh) * 2013-12-04 2015-06-10 台湾积体电路制造股份有限公司 叠层封装件结构中的翘曲控制
WO2015088486A1 (en) * 2013-12-09 2015-06-18 Intel Corporation Antenna on ceramics for a packaged die
US20160049723A1 (en) * 2014-08-13 2016-02-18 International Business Machines Corporation Wireless communications package with integrated antennas and air cavity
CN105720049A (zh) * 2014-12-15 2016-06-29 英特尔公司 负鼠晶片封装叠加设备
CN206179848U (zh) * 2016-08-16 2017-05-17 深圳市中兴微电子技术有限公司 一种PoP堆叠封装结构

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100796523B1 (ko) * 2006-08-17 2008-01-21 삼성전기주식회사 전자부품 내장형 다층 인쇄배선기판 및 그 제조방법
CN102237342B (zh) 2010-05-05 2016-01-20 中兴通讯股份有限公司 一种无线通讯模块产品
TWI523158B (zh) 2010-10-11 2016-02-21 日月光半導體製造股份有限公司 雙面封裝結構及應用其之無線通訊系統
KR20120104896A (ko) * 2011-03-14 2012-09-24 삼성전자주식회사 초고주파 패키지 모듈
US8816906B2 (en) * 2011-05-05 2014-08-26 Intel Corporation Chip packages including through-silicon via dice with vertically inegrated phased-array antennas and low-frequency and power delivery substrates
KR101434003B1 (ko) * 2011-07-07 2014-08-27 삼성전기주식회사 반도체 패키지 및 그 제조 방법
WO2013121732A1 (ja) * 2012-02-15 2013-08-22 パナソニック株式会社 無線モジュール
US20130293420A1 (en) * 2012-05-07 2013-11-07 Wilocity Ltd. Techniques for maximizing the size of an antenna array per radio module
CN103258817B (zh) 2012-09-20 2016-08-03 日月光半导体制造股份有限公司 半导体封装结构及其制造方法
US8890284B2 (en) * 2013-02-22 2014-11-18 Infineon Technologies Ag Semiconductor device
US20170040266A1 (en) * 2015-05-05 2017-02-09 Mediatek Inc. Fan-out package structure including antenna
DE112016006695T5 (de) 2016-04-01 2018-12-06 Intel IP Corporation Gehäuse auf Antennengehäuse
US10847869B2 (en) 2017-06-07 2020-11-24 Mediatek Inc. Semiconductor package having discrete antenna device
US11509038B2 (en) 2017-06-07 2022-11-22 Mediatek Inc. Semiconductor package having discrete antenna device
KR101942736B1 (ko) 2017-08-04 2019-04-17 삼성전기 주식회사 반도체 패키지 연결 시스템

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104037166A (zh) * 2013-03-07 2014-09-10 日月光半导体制造股份有限公司 包含天线层的半导体封装件及其制造方法
CN104701269A (zh) * 2013-12-04 2015-06-10 台湾积体电路制造股份有限公司 叠层封装件结构中的翘曲控制
WO2015088486A1 (en) * 2013-12-09 2015-06-18 Intel Corporation Antenna on ceramics for a packaged die
US20160049723A1 (en) * 2014-08-13 2016-02-18 International Business Machines Corporation Wireless communications package with integrated antennas and air cavity
CN105720049A (zh) * 2014-12-15 2016-06-29 英特尔公司 负鼠晶片封装叠加设备
CN206179848U (zh) * 2016-08-16 2017-05-17 深圳市中兴微电子技术有限公司 一种PoP堆叠封装结构

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11509038B2 (en) 2017-06-07 2022-11-22 Mediatek Inc. Semiconductor package having discrete antenna device
US11721882B2 (en) 2017-06-07 2023-08-08 Mediatek Inc. Semiconductor package having discrete antenna device
CN110277356A (zh) * 2018-03-16 2019-09-24 中芯长电半导体（江阴）有限公司 天线馈电线的封装结构及封装方法
CN110277356B (zh) * 2018-03-16 2021-12-28 盛合晶微半导体(江阴)有限公司 天线馈电线的封装结构及封装方法
CN111786074A (zh) * 2019-04-04 2020-10-16 三星电机株式会社 天线模块
CN111786074B (zh) * 2019-04-04 2024-04-05 三星电机株式会社 天线模块
CN112018101A (zh) * 2019-05-28 2020-12-01 联发科技股份有限公司 半导体封装
CN112018101B (zh) * 2019-05-28 2023-02-03 联发科技股份有限公司 半导体封装
US11967778B2 (en) 2019-05-30 2024-04-23 Huawei Technologies Co., Ltd. Packaging structure, network device, and terminal device
CN113302801A (zh) * 2019-05-30 2021-08-24 华为技术有限公司 封装结构、网络设备以及终端设备
WO2021042377A1 (zh) * 2019-09-06 2021-03-11 深圳市汇顶科技股份有限公司 集成装置及其制备方法
CN111430327A (zh) * 2020-03-05 2020-07-17 广东工业大学 一种高散热扇出型封装结构及封装方法
WO2022007180A1 (zh) * 2020-07-08 2022-01-13 瑞声声学科技(深圳)有限公司 射频模组
WO2022007245A1 (zh) * 2020-07-08 2022-01-13 瑞声声学科技(深圳)有限公司 射频模组
CN114284738A (zh) * 2020-09-28 2022-04-05 联发科技股份有限公司 天线结构和天线封装
CN115425394A (zh) * 2022-08-05 2022-12-02 中国电子科技集团公司第十四研究所 一种基于层叠式结构的带状线以及基于异质基材三维堆叠的层叠式阵面天线单元
CN115425394B (zh) * 2022-08-05 2024-02-27 中国电子科技集团公司第十四研究所 一种基于层叠式结构的带状线以及基于异质基材三维堆叠的层叠式阵面天线单元

Also Published As

Publication number Publication date
US20210036405A1 (en) 2021-02-04
US20180358685A1 (en) 2018-12-13
US10847869B2 (en) 2020-11-24
EP3413347A1 (en) 2018-12-12
TW201903994A (zh) 2019-01-16
US11721882B2 (en) 2023-08-08
EP4293821A3 (en) 2024-05-22
EP3413347B1 (en) 2023-12-20
EP4293821A2 (en) 2023-12-20

Similar Documents

Publication Publication Date Title
CN109449141A (zh) 半导体封装
US9935065B1 (en) Radio frequency device packages and methods of formation thereof
US11509038B2 (en) Semiconductor package having discrete antenna device
US8648454B2 (en) Wafer-scale package structures with integrated antennas
EP3474370B1 (en) Antenna-in-package with frequency-selective surface structure
US8952521B2 (en) Semiconductor packages with integrated antenna and method of forming thereof
CN110649001B (zh) 一种集成天线结构的2.5d多芯片封装结构及制造方法
US10879197B2 (en) Package structure and method of fabricating package structure
CN107093598A (zh) 包括天线的半导体装置
CN103650132B (zh) 无线模块
TWI723885B (zh) 半導體封裝
US20170236790A1 (en) Semiconductor Device on Leadframe with Integrated Passive Component
CN110491864B (zh) 半导体封装结构
KR20230127138A (ko) 패키지 기판 상에 안테나를 갖는 안테나 인 패키지
EP2469592A1 (en) Integrated circuit chip package device
US8558353B2 (en) Integrated circuit having an uppermost layer comprising landing pads that are distributed thoughout one side of the integrated circuit
US11538772B2 (en) Semiconductor device package and method of manufacturing the same
US20040125574A1 (en) Multi-chip semiconductor package and method for manufacturing the same
TWI789768B (zh) 天線模組及其製造方法暨電子裝置
CN116230558B (zh) 单极化空气耦合天线封装结构及制备方法
CN115411491A (zh) 天线模块及其制造方法、电子装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB03 Change of inventor or designer information
CB03 Change of inventor or designer information

Inventor after: Han Fuyi

Inventor after: Zhou Zheya

Inventor after: Guo Zhehong

Inventor after: Wu Wenzhou

Inventor after: Chen Nancheng

Inventor after: Lin Minzhen

Inventor after: Liu Xingzhi

Inventor before: Han Fuyi

Inventor before: Zhou Zheya

Inventor before: Guo Zhehong

Inventor before: Wu Wenzhou

Inventor before: Chen Nancheng

WW01 Invention patent application withdrawn after publication
WW01 Invention patent application withdrawn after publication

Application publication date: 20190308