CN105720049A - 负鼠晶片封装叠加设备 - Google Patents

负鼠晶片封装叠加设备 Download PDF

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Publication number
CN105720049A
CN105720049A CN201511035977.8A CN201511035977A CN105720049A CN 105720049 A CN105720049 A CN 105720049A CN 201511035977 A CN201511035977 A CN 201511035977A CN 105720049 A CN105720049 A CN 105720049A
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CN
China
Prior art keywords
encapsulation
wafer
package substrate
coupled
package
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Pending
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CN201511035977.8A
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English (en)
Inventor
C·盖斯勒
T·梅耶
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Intel Corp
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Intel Corp
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Publication of CN105720049A publication Critical patent/CN105720049A/zh
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Abstract

一种设备，包括耦合至第二封装的第一封装，其中第一封装和第二封装的每个都具有第一侧和相对的第二侧；第一晶片，耦合至该第一封装；以及第二晶片，耦合至该第二封装的该第二侧，其中该第一封装以堆叠布置的方式耦合至该第二封装使得该第二封装的该第一侧面向该第一封装的该第二侧。一种方法，包括将第一封装以堆叠配置耦合至第二封装，其中该第一封装包括第一封装衬底和第一晶片，并且该第二封装包括第二封装衬底和第二晶片，其中该第二晶片设置在与该第一封装衬底相对的该第二封装衬底的一侧上。

Description

负鼠晶片封装叠加设备
技术领域
集成电路封装。
背景技术
对于移动应用来说，小封装形状因数(占用面积和z-高度)和低封装成本是新产品的重要要求。使用封装叠加(PackageonPackage)(PoP)组件(在该组件中一个封装以堆叠布置(在z方向上一个在另一个上方)的方式连接至另一封装)以减少模块的占用面积(例如在应用处理器顶部上的存储器)。在减小xy-方向占用面积的同时，PoP配置增加了该模块的z-方向厚度或高度(“z-高度”)。现有PoP模块技术的目前状况是具有大约一毫米或更大的z-高度。典型的PoP解决方案还允许在顶部和底部封装之间的有限数量的互连。典型地，这些互连位于该底部封装的扇出(fan-out)区域或周边区域中。可以使用用于互连的附加再布线层或更紧密的几何形状以增加互连带宽，但是这样的解决方案易于增加封装成本。
附图说明
图1示出了封装叠加(PoP)组件的实施例的横截面侧视图，该组件包括底部或支撑封装，该封装具有相对于所附接的封装衬底的悬挂或负鼠(opossum)配置的晶片(die)。
图2示出了PoP组件的另一实施例的横截面侧视图，该组件使用底部或支撑封装，该封装具有相对于所附接的封装衬底的悬挂或负鼠配置的晶片。
图3示出了PoP组件的另一实施例的横截面侧视图，其中下面的或支撑的封装基于晶圆级封装，尤其是具有至顶部封装的周边互连的嵌入式晶圆级球栅阵列(例如eWLB)封装。
图4示出了PoP组件的另一实施例的横截面侧视图，该组件具有作为底部封装的负鼠扇出晶圆级封装，该底部封装具有至顶部封装的区域互连。
图5示出了使用eWLB叠加eWLB负鼠配置的预-PoP组件的横截面侧视图。
图6示出了模制载体的侧视图，该载体具有设置在其表面上的粘性箔和放置在该粘性箔上的若干通孔条(viabar)。
图7示出了图6经过了通孔条和模制材料从粘结层分离并且在该结构上引入再分配层和将晶片连接至其之后的结构。
图8示出了图7经过模制材料薄化之后的结构。
处理顺序也可以是不同的：在放置焊球和负鼠晶片之前薄化本体。
图9图示了计算装置的实施例。
具体实施方式
图1示出了封装叠加(PoP)组件的实施例的横截面侧视图，该组件包括底部或支撑封装，该封装具有相对于所附接的封装衬底的悬挂或负鼠配置的晶片。参考图1，PoP组件100包括以堆叠布置连接至封装230的封装110(如所示出的封装110在z-方向上位于封装130之上或上面)。
封装110包括封装衬底115，分别通过例如晶片的接触点和封装衬底之间的、可选地包括底部填充的凸块或回流工艺，将晶片120电性和物理地连接至该封装衬底的表面。具有代表性地，晶片120是存储器晶片。封装110还包括可操作地将封装110连接至底部或支撑封装130的互连150(例如焊料凸块)。
在图1中示出的PoP组件100的封装130包括封装衬底135，通过可选地包括底部填充的凸块或回流工艺将晶片140(例如倒装芯片微处理器)电性和物理地连接至该封装衬底135。如图1中示出的，晶片140连接至封装衬底135的一侧使得晶片140相对于z-方向位于封装衬底135的下方并且因此如所示出的相对于封装衬底135处于负鼠或悬挂晶片配置。换句话说，在每个封装衬底包括晶片侧，各自的晶片连接至封装衬底的该晶片侧(晶片120连接至封装衬底115以及晶片140连接至封装衬底135)，和相对侧或背侧的情况下，封装衬底115的背侧面对封装衬底135的背侧。
在PoP组件100中，晶片140关于其与封装衬底145的附连并且相对于晶片120与封装衬底115的附连而言是处于悬挂或负鼠配置的，如所示出的，其中封装110在封装130之上或上方。封装衬底135还包括在封装衬底的晶片侧上的接触焊盘155。在示出的实施例中，PoP组件100连接至衬底175，该衬底175典型地例如是用在移动应用中的印刷电路板，该移动应用例如是电话或其它便携式计算装置。通过在封装衬底135的接触焊盘155和衬底175的相应接触焊盘之间的焊料连接160(焊球)将PoP组件100连接至衬底175。在一个实施例中，包括至衬底和再分配层的任何互连的晶片140的厚度或高度h1小于焊料连接160的厚度或高度h2。
参考组件100，关于封装110至封装130的连接，可以通过到达接触或接触焊盘(布置在每个封装的区域表面周围)的焊料连接来完成该连接。具有代表性地，图1示出了具有内部区域180和周边区域185的封装衬底115，内部区域180和周边区域185共同限定该封装的区域表面。如所示出的，接触焊盘布置在内部区域180的周围并且还有周边区域185的周围。在衬底制造阶段期间通过将迹线或互连布线或分配至内部区域185并形成至该迹线或互连的接触焊盘，可以形成这样的接触焊盘。使用封装衬底115的内部区域180用于衬底和封装130之间的互连点的能力提供了相比于仅具有周边布置的接触焊盘(仅在周边区域185中)的封装衬底而言增加的互连点数量。图1示出了封装衬底135，该封装衬底135具有设置在与晶片140所连接的衬底一侧相对的、封装衬底的表面上的接触焊盘145。接触焊盘145与封装衬底115的接触焊盘125(包括在封装衬底的内部区域中)对准，并且焊料连接150(焊球)通过各自的接触焊盘连接这些封装。
图2示出了PoP组件的另一实施例的横截面侧视图，该组件使用底部或支撑封装，该封装具有相对于所附接的封装衬底悬挂或负鼠配置的晶片。参考图2，组件200包括封装210，封装210以堆叠布置的方式(如示出的在z-方向一个在其它的之上或上方)连接至封装230。封装210包括封装衬底215，通过例如可选地包括底部填充工艺的凸块或回流工艺，将晶片220电性和物理地连接至该封装衬底215的表面。具有代表性地，晶片220是倒装芯片存储器晶片。图2还示出了封装210，该封装210包括与晶片220所连接的侧相对的衬底侧上的接触焊盘225。接触焊盘225设置在封装衬底内部区域280的周边的区域285中。在一个实施例中，将接触焊盘225设置为沿着具有矩形或正方形的封装衬底215的表面的四个侧边的周边或边缘。
在图2中的PoP组件200的封装230包括封装衬底235，通过可选地包括底部填充工艺的凸块或回流工艺，将晶片240(例如倒装芯片微处理器)连接至该封装衬底235。如示出的，晶片240连接至封装衬底235的一侧使得晶片240相对于z-方向位于封装衬底235下面并因此相对于封装衬底235处于负鼠或悬挂配置。封装230的封装衬底235包括接触焊盘245，该接触焊盘245设置在与晶片240所附接的侧相对的衬底侧上。接触焊盘245设置在封装衬底表面上的周边布置中并且与封装210的接触焊盘225对准。图2示出了设置在封装210的接触焊盘225和封装230的接触焊盘245之间的焊料连接250(焊球)以电性连接这些封装。封装230的封装衬底235还包括设置在封装衬底的晶片侧上的接触焊盘255。图2示出了连接至接触焊盘255的焊料连接260，该接触焊盘255可操作地将PoP组件200连接至诸如印刷电路板的衬底。
在图1和图2的每一个中示出的实施例中，每个组件代表性地包括封装，例如设置在具有负鼠或悬挂晶片配置的倒装芯片球栅阵列封装上的商业存储器封装。通过使用负鼠或悬挂晶片配置以用于PoP组件的底部或支撑封装(例如图1的封装130，图2的封装230)，最小化了组件的z-高度。在一个实施例中，对于图1中的封装组件100和图2中的封装组件200二者来说代表性的z高度是大约1毫米(mm)。
图3示出了PoP组件的另一实施例的横截面侧视图，其中下面的或支撑封装基于晶圆级封装，尤其是嵌入式晶圆级球栅阵列(例如eWLB)封装。对于eWLB，封装是形成在关于晶片接触的再分配层周围的。图3示出了PoP组件300的横截面侧视图，该组件300包括以堆叠方式电性连接至封装330的封装310，该封装310在z-方向布置在封装330之上和上方。封装310包括封装衬底315。例如是存储器晶片的晶片320电性和物理地连接至封装衬底315表面(如示出的是顶表面)上的接触。封装衬底315包括接触焊盘325，接触焊盘325设置在与晶片320所附接的侧相对的一侧上的封装衬底的周边区域周围。周边区域385是内部区域380的周边，并且在一个实施例中，其围绕四边形矩形封装衬底的每边的周边或边缘。
图3中的PoP组件300的封装330包括例如直接连接至再分配层335的微处理器的晶片340。再分配层335包括晶片侧(连接至晶片340)上的接触焊盘和与借由其间的电迹线和互连将晶片340连接至的一侧相对的一侧上的接触焊盘345。通孔条348连接至接触焊盘345，通孔条348嵌入或设置在模制材料343中。如图所示的，通孔条348形成在封装衬底的周边区域周围并且与封装衬底315的接触焊盘325对准。在另一实施例中，可以使用穿透模制通孔(TMV)替换通孔条。
通过接触焊盘325和通孔条348之间的焊料连接350将封装衬底310连接至封装衬底330。接触焊盘设置在包括晶片340的封装330的一侧上，焊料连接360连接至接触焊盘以将组件300电性连接至作为印刷电路板的衬底。
图4示出了PoP组件的另一实施例的横截面侧视图。组件400包括以堆叠配置连接至封装430的封装410，如所示出的封装410相对于z-方向在封装430之上。在一个实施例中，封装410包括诸如存储器晶片的晶片420，电性和物理地连接至封装衬底415的晶片侧或第一侧上的接触点。封装衬底415具有与晶片侧相对的封装衬底的第二侧上的接触焊盘425。这些接触焊盘设置在封装衬底的内部区域480和周边区域485周围。在一个实施例中，封装410是倒装芯片球栅阵列封装。
在图4中示出的组件400中的封装430包括设置在eWLB布置中的晶片440，eWLB布置包括再分配层435和嵌入在模制材料443中的通孔条448。电介质材料的再分配层包括连接至晶片440的接触点的第一侧(如示出的底侧)上的接触点、导电互连/迹线和互连以向再分配层435的第二侧(如所示的顶侧)上的第二接触点再分配该连接。这些接触点相应的一些连接到各自的通孔条448。通孔条448在一侧连接至再分配层435并且在相对侧提供用于连接封装430和封装410的接触点或焊盘。图4示出了设置在封装410的接触焊盘425和封装430的通孔条448之间的焊料连接450(焊球)。图4还示出了连接至再分配层435的晶片侧(与通孔条448相对的侧)上的接触焊盘的焊料连接460。在一个实施例中，焊料连接460是可操作地以将组件400连接至诸如印刷电路板的衬底。
通过使用如图3和图4中的包括负鼠或悬挂配置的晶片的eWLB封装，可以实现PoP组件的z-高度是1mm或更小。另外，底部封装的负鼠或悬挂晶片配置(如图3和图4中所示的)提供了封装间的界面区域，用于互连的内部区域380(图3)和内部区域480(图4)。尤其是图4示出了使用该内部界面区域以用于具有球栅阵列布置的封装间的互连。
关于上面的实施例所描述的优点包括：封装堆叠的z-高度是1mm或更小；用于顶部封装的面积阵列能力；顶部封装直接接触至底部封装衬底，提供从顶部封装至底部封装的减少的互连；直接的晶片附接的可能性；以及谨慎地附接无源器件的机会而同时保持最小的封装高度。
图5示出了每个都使用了eWLB叠加eWLB负鼠配置的三个PoP组件的横截面侧视图。封装组件500A包括以堆叠配置电连接至底部封装530A的顶部封装510A(如所示出的)。封装510A包括例如是存储器晶片的晶片520A，在器件侧上电性和物理地连接至再分配层515A。再分配层515包括与连接至晶片520A的一侧相对的再分配层的一侧上的接触点525A。封装510A还示出了嵌入晶片520A的模制材料527A。
封装530A包括在晶片侧上连接至再分配层535A的晶片540A，其中再分配层535A的相对侧连接至嵌入在模制材料543A中的通孔条548A。如图所示，通过封装510A的接触焊盘525A和与封装530A的通孔条548A相关的接触点之间的焊料连接550A(焊球)，封装510A连接至封装535A。如图所示，封装530A的晶片540A如所示的以负鼠或悬挂配置的方式设置在再分配层535A的下方。
PoP组件500B包括以堆叠配置(如所示的封装510B设置在封装530B上方或之上)连接至封装530B的封装510B。在一个实施例中，封装510B类似于封装510A并且包括连接至再分配层515B的晶片520B和嵌入在模制材料527B中的晶片。再分配层515B包括设置在与晶片520B所连接的侧相对的再分配层的一侧上的接触焊盘525B。
在一个实施例中，图5中示出的PoP组件500B的封装530B类似于组件500A的封装530A，并且包括电性连接至再分配层535B的晶片540B和电性连接至嵌入在模制材料543B中的通孔条548B的再分配层。在组件500B中，封装510B电性连接至使用焊盘上焊料(SOP)或半球形焊球550B的封装530B。以这种方式，介于封装510B的接触焊盘525B与封装530B的通孔条548B的接触点之间的互连的z-高度被最小化。因而，PoP组件500B的z-高度小于封装组件500A的z-高度。
PoP组件500C包括以堆叠配置的方式连接至封装530C的第一封装510C，如所示的封装510C位于封装530C之上或上方。在本实施例中，封装510C和封装530C的每一个都包括负鼠或悬挂配置的晶片。封装510C包括连接至再分配层515C的晶片520C。图5还示出了连接在再分配层515C的晶片侧上的通孔条528C。在本实施例中，晶片520C和通孔条528C二者均嵌入在模制材料527C中。
在一个实施例中，PoP组件500C中的封装530C分别类似于组件500B和组件500A的封装530B和封装530A。封装530C包括连接至再分配层535C的晶片540C和从再分配层535C的相对侧延伸并嵌入在模制材料543C中的通孔条548C。图5示出了连接在封装510C的通孔条528C的接触点与封装530C的通孔条548C的接触点之间的焊盘上焊料(SOP)或半球形焊球550C。如图所示，PoP组件500C具有小于PoP组件500B或PoP组件500A的z-高度或厚度。
尽管用于形成eWLB封装的技术是众所周知的，图6-8示出了形成eWLB封装的工艺的横截面侧视图，该eWLB封装具有诸如图5中的封装530A或封装530B的负鼠或悬挂晶片配置。图6示出了模制载体的侧视图，该模制载体具有设置在其表面上的粘结箔以及放置在该粘结箔上的若干通孔条。例如，模制载体610是粘结箔620可能固定在其上的不锈钢材料。通孔条630设置在粘结箔620上，且具有与该箔接触的各自的接触点或焊盘。在粘结箔620上设置通孔条630之后，将例如液态或粒状模制混合物的模制材料引入到粘结箔620上以嵌入通孔条630。
图7示出了图6经过从粘结层上分离通孔条和模制材料并在该结构上引入再分配层并将晶片连接至其上之后的结构。在一个实施例中，通过使用例如一定热预算的脱粘工艺将模制材料640从粘结层620分离。参考图7，通过向由移除粘结层620而产生的表面上引入电介质层650，并使用光刻技术将接触图案化至通孔条630的接触点或焊盘，随后通过镀层技术以形成导电通孔和迹线而引入再分配层。导电通孔和/或接触点或焊盘还形成在与通孔条630和模制材料640接触的表面相对的电介质层650的表面上或附近。图7示出了晶片660，该晶片660电性和物理地连接至这种接触点或焊盘655，还有连接至其它一些接触点或焊盘655的焊料连接670(焊球)。
图8示出了图7经过薄化模制材料之后的结构。薄化模制材料640以暴露每个通孔条630的接触表面。在薄化模制材料之后，封装被组装并且可以连接至用于PoP组件的第二封装。在另一实施例中，处理顺序还可以是不同的：在放置焊球和负鼠晶片之前薄化该本体。如图8中所示，该封装包括负鼠或悬挂晶片配置的晶片(如示出的在z-方向上在再分配层下方)。
图9示出了根据一个实施例的计算装置700。计算装置700容纳板702。板702可以包括若干部件，包括但不限于处理器704并且包括至少一个通信芯片706。处理器704物理并且电性地耦合至板702。在一些实现中，至少一个通信芯片706还物理和电性地耦合至板702。在进一步的实施例中，通信芯片706是处理器704的一部分。可以使用例如在上面实现中描述的PoP组件以包括处理器404和另一芯片(例如通信芯片406、存储器芯片)。
依赖于其应用，计算装置700可能包括可能物理和电性地或可能不物理和电性地耦合至板702的其它部件。这些其它部件包括但不限于挥发存储器(例如DRAM)、非挥发存储器(例如ROM)、闪存、图形处理器、数字信号处理器、密码处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)装置、罗盘、加速器、陀螺仪、扬声器、照相机和大容量存储装置(例如硬盘驱动器、光盘(CD)、数字多功能盘(DVD)等等)。
通信芯片706使无线通信能够用于出入计算装置700的数据的传输。术语“无线”及其派生词可用于描述电路、装置、系统、方法、技术、通信信道等，其可以通过使用穿过非固体媒介的调制电磁辐射来通信数据。该术语不意味着相关装置不包含任何线路，但在一些实施例中它们可能不包括任何线路。通信芯片706可能执行若干无线标准或协议的任一个，包括但不限于Wi-Fi(IEEE802.11系列)、WiMAX(IEEE802.16系列)、IEEE802.20、长期演进技术(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙及其派生物，还有被指定为3G、4G、5G及以上的任何其它无线协议。计算装置700可能包括多个通信芯片706。例如，第一通信芯片706可能致力于例如Wi-Fi和蓝牙的较短范围的无线通信，而第二通信芯片706可能致力于例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO及其它较长范围的无线通信。.
计算装置700的处理器704包括封装在处理器704之内的集成电路晶片。术语“处理器”可能涉及任意装置或装置的一部分，该装置处理来自于寄存器和/或存储器的电子数据以将电子数据转变为可能存储在寄存器和/或存储器中的其它电子数据。
通信芯片706还包括封装在通信芯片706之内的集成电路晶片。
在进一步的实施例中，容纳在计算装置700之内的另一部件可能包含集成电路晶片，该晶片包括诸如晶体管或金属互连的一个或多个器件。
在各种实现中，计算装置700可能是膝上型电脑、上网本、笔记本、超级本、智能手机、平板电脑、个人数字助手(PDA)、超移动PC、移动电话、台式电脑、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字照相机、便携式音乐播放器或数字录像机。在进一步的实现中，计算装置700可能是处理数据的任何其它电子装置。
实例
实例1是一种设备，包括耦合至第二封装的第一封装，其中第一封装和第二封装的每个具有第一侧和相对的第二侧；第一晶片，耦合至该第一封装；以及第二晶片，耦合至该第二封装的该第二侧，其中该第一封装以堆叠布置的方式耦合至该第二封装使得该第二封装的该第一侧面向该第一封装的该第二侧。
在实例2中，实例1的设备中的该第一晶片耦合至该第一封装的该第一侧。
在实例3中，实例2的设备中的该第一封装通过每个封装的表面的内部周围的接触耦合至该第二封装。
在实例4中，实例2的设备中的该第一封装通过周边排列的接触点而通过接触耦合至该第二封装。
在实例5中，实例1的设备中的该第一晶片耦合至该第一封装的该第二侧。
在实例6中，实例5的设备中的该第一封装通过周边排列的接触点耦合至该第二封装。
在实例7中，实例1的设备中的该第二封装包括该第一侧上的多个接触点以及通孔条，该通孔条耦合至多个接触点的相应的一些接触点，并耦合至该第一封装的该第二侧上的接触点。
在实例8中，实例7的设备中的该通孔条耦合至该第一封装的该第二侧上的接触点上的焊料连接。
在实例9中，实例7的设备中的该第一晶片耦合至该第一封装的该第一侧。
在实例10中，实例7的设备中的该第一晶片耦合至该第一封装的该第二侧。
实例11是一种设备，包括封装叠加配置，包括以堆叠布置的方式耦合至第二封装的第一封装，其中该第一封装位于该第二封装上，该第一封装包括第一封装衬底和第一晶片并且该第二封装包括第二封装衬底和第二晶片，其中该第二晶片设置在与该第一封装衬底相对的第二封装衬底的一侧上。
在实例12中，实例11的设备中的该第一晶片耦合至与该第二封装衬底相对的该第一封装衬底的一侧。
在实例13中，实例12的设备中的该第一封装通过每个封装的表面的内部周围的接触耦合至该第二封装。
在实例14中，实例12的设备中的该第一封装通过穿过周边排布的接触点而通过接触耦合至该第二封装。
在实例15中，实例11的设备中的该第一晶片耦合至面向该第二封装衬底的第一封装衬底的一侧。
实例16是一种方法，包括采用堆叠配置将第一封装耦合至第二封装，其中该第一封装包括第一封装衬底和第一晶片，并且该第二封装包括第二封装衬底和第二晶片，其中该第二晶片设置在与该第一封装衬底相对的该第二封装衬底的一侧上。
在实例17中，实例16的方法中的该第一晶片耦合至与该第二封装衬底相对的该第一封装衬底的一侧。
在实例18中，实例16的方法中将该第一封装耦合至该第二封装包括通过每个封装的表面的内部周围的接触进行耦合。
在实例19中，实例16的方法中将该第一封装耦合至该第二封装包括通过周边排列的接触点而通过接触进行耦合。
在实例20中，实例16的方法中的该第一晶片耦合至面向该第二封装衬底的该第一封装衬底的一侧。
在实例21中，通过实例16-20的任一方法制造的集成电路封装。
包括摘要中描述的内容的本发明的图示实现的上述说明不意在是穷举的或者将本发明限制在所公开的明确的形式。尽管本文例如为了图示的目的描述了本发明的具体实现，但是在本发明的范围内各种等同的修改是可能的，如所属领域技术人员将会认识到的。
可以根据上面的详细描述可以对本发明作出这些修改。在下面权利要求中使用的术语不应当解释为将本发明限制于说明书和权利要求中公开的具体实现。相反，根据所建立的权利要求解释的原则解释本发明的范围，通过下面的权利要求整体地确定本发明的范围。

Claims (21)

1.一种设备，包括：
第一封装，耦合至第二封装，其中该第一封装和该第二封装的每个都具有第一侧和相对的第二侧；
第一晶片，耦合至该第一封装；以及
第二晶片，耦合至该第二封装的该第二侧，
其中该第一封装以堆叠布置的方式耦合至该第二封装使得该第二封装的该第一侧面向该第一封装的该第二侧。
2.如权利要求1的设备，其中该第一晶片耦合至该第一封装的该第一侧。
3.如权利要求2的设备，其中该第一封装通过每个封装的表面的内部周围的接触耦合至该第二封装。
4.如权利要求2的设备，其中该第一封装通过周边排列的接触点而通过接触耦合至该第二封装。
5.如权利要求1的设备，其中该第一晶片耦合至该第一封装的该第二侧。
6.如权利要求5的设备，其中该第一封装通过周边排列的接触点耦合至该第二封装。
7.如权利要求1的设备，其中该第二封装包括该第一侧上的多个接触点以及通孔条，该通孔条耦合至所述多个接触点的相应的一些并耦合至该第一封装的该第二侧上的接触点。
8.如权利要求7的设备，其中该通孔条耦合至该第一封装的该第二侧上的接触点上的焊料连接。
9.如权利要求7的设备，其中该第一晶片耦合至该第一封装的该第一侧。
10.如权利要求7的设备，其中该第一晶片耦合至该第一封装的该第二侧。
11.一种设备，包括：
封装叠加配置，包括以堆叠布置的方式耦合至第二封装的第一封装，其中该第一封装位于该第二封装上，该第一封装包括第一封装衬底和第一晶片并且该第二封装包括第二封装衬底和第二晶片，其中该第二晶片设置在与该第一封装衬底相对的第二封装衬底的一侧上。
12.如权利要求11的设备，其中该第一晶片耦合至与该第二封装衬底相对的该第一封装衬底的一侧。
13.如权利要求12的设备，其中该第一封装通过每个封装的表面的内部周围的接触耦合至该第二封装。
14.如权利要求12的设备，其中该第一封装通过周边排列的接触点而通过接触耦合至该第二封装。
15.如权利要求11的设备，其中该第一晶片耦合至面向该第二封装衬底的第一封装衬底的一侧。
16.一种方法，包括：
将第一封装以堆叠配置耦合至第二封装，其中该第一封装包括第一封装衬底和第一晶片，并且该第二封装包括第二封装衬底和第二晶片，其中该第二晶片设置在与该第一封装衬底相对的该第二封装衬底的一侧上。
17.如权利要求16的方法，其中该第一晶片耦合至与该第二封装衬底相对的该第一封装衬底的一侧。
18.如权利要求16的方法，其中将该第一封装耦合至该第二封装包括通过每个封装的表面的内部周围的接触进行耦合。
19.如权利要求16的方法，其中将该第一封装耦合至该第二封装包括通过周边排列的接触点而通过接触进行耦合。
20.如权利要求16的方法，其中该第一晶片耦合至面向该第二封装衬底的该第一封装衬底的一侧。
21.一种通过权利要求16-20的任一方法制造的集成电路封装。
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