TWI607547B - 負鼠式晶粒堆疊式封裝設備 - Google Patents

負鼠式晶粒堆疊式封裝設備 Download PDF

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Publication number
TWI607547B
TWI607547B TW104136686A TW104136686A TWI607547B TW I607547 B TWI607547 B TW I607547B TW 104136686 A TW104136686 A TW 104136686A TW 104136686 A TW104136686 A TW 104136686A TW I607547 B TWI607547 B TW I607547B
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package
die
coupled
substrate
package substrate
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TW104136686A
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TW201633496A (zh
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克里斯坦 吉瑟勒
特羅斯登 梅耶爾
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英特爾公司
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Description

負鼠式晶粒堆疊式封裝設備 發明領域
積體電路封裝。
發明背景
對於行動應用而言，小型封裝形狀因數(佔據面積及z高度)及低封裝成本為新產品之重要要求。堆疊式封裝(PoP)總成用來減小模組佔據面積(例如，應用處理器頂部之記憶體)，在堆疊式封裝總成中，一個封裝以堆疊配置連接至另一封裝(在z方向上重疊)。雖然減小xy方向上之佔據面積，但PoP組態增加模組之z方向上之厚度或高度(「z高度」)。當前技術現狀中的PoP模組技術具有約一毫米或更大之z高度。典型PoP解決方案亦允許頂部封裝與底部封裝之間的有限數目之互連。通常，該等互連位於底部封裝之扇出區域或周邊區域中。用於互連之額外再選路層或更緊密的幾何配置可用來增加互連頻寬，但此類解決方案往往增加封裝成本。
依據本發明之一實施例，係特地提出一種設備，其包含：一第一封裝，其耦接至一第二封裝，其中該第一 封裝及該第二封裝中之每一者具有一第一側面及一對置之第二側面；一第一晶粒，其耦接至該第一封裝；以及一第二晶粒，其耦接至該第二封裝之該第二側面，其中該第一封裝以一堆疊配置耦接至該第二封裝，使得該第二封裝之該第一側面面向該第一封裝之該第二側面。
100、300、500C‧‧‧PoP總成
110、130、210、230、310、330、410、430、510B、530A、530B、530C‧‧‧封裝
115、135、145、215、235、315、415‧‧‧封裝基板
120、140、220、240、320、340、420、440、520A、520B、520C、540A、540B、540C、660‧‧‧晶粒
125、155、225、245、255、325、345、425、525B、655‧‧‧接觸墊
150、160、250、260、350、360、450、460、550A、670‧‧‧焊料接頭
175‧‧‧基板
180、280、380、480‧‧‧內部區域
185、385、485‧‧‧周邊區域
200、500B‧‧‧PoP總成/總成
285‧‧‧周邊之區域
335、435、515A、515B、515C、535A、535B、535C‧‧‧再分配層
343、443、527A、527B、527C、543A、543B、543C、640‧‧‧模製材料
348、448、528C、548A、548B、548C、630‧‧‧通孔桿
400‧‧‧總成
500A‧‧‧封裝總成/總成
510A‧‧‧頂部封裝/封裝
510C‧‧‧第一封裝/封裝
525A‧‧‧接觸點
550B、550C‧‧‧半球形焊球
610‧‧‧模製載體
620‧‧‧黏著箔片
650‧‧‧介電質層
700‧‧‧計算裝置
702‧‧‧板
704‧‧‧處理器
706‧‧‧通訊晶片
h1、h2‧‧‧厚度或高度
x、z‧‧‧方向
圖1展示堆疊式封裝(PoP)總成之實施例之橫截面側視圖，該PoP總成包括具有晶粒之底部封裝或支撐封裝，該晶粒相對於其所附接至之封裝基板處於懸掛式組態或負鼠式組態。
圖2展示採用具有晶粒之底部封裝或支撐封裝的PoP總成之另一實施例之橫截面側視圖，該晶粒相對於其所附接至之封裝基板處於懸掛式組態或負鼠式組態。
圖3展示PoP總成之另一實施例之橫截面側視圖，其中下伏封裝或支撐封裝係基於晶圓級封裝，尤其係基於具有至頂部封裝之周邊互連的嵌入式晶圓級球柵陣列(例如，eWLB)封裝。
圖4展示PoP總成之另一實施例之橫截面側視圖，該PoP總成具有作為底部封裝之負鼠式扇出晶圓級封裝，該底部封裝具有至頂部封裝之區域互連。
圖5展示使用堆疊式eWLB負鼠式組態之預PoP總成之橫截面側視圖。
圖6展示具有黏著箔片以及置放於該黏著箔片上之若干通孔桿(via bar)的模製載體之側視圖，該黏著箔片設 置於該模製載體之表面上。
圖7展示在將通孔桿及模製材料與黏著層分離，且在該結構上引入再分配層以及將晶粒連接至該再分配層之後的圖6之結構。
圖8展示在使模製材料變薄之後的圖7之結構。
處理順序亦可不同：在置放焊球及負鼠式晶粒前使主體變薄。
圖9例示計算裝置之實施例。
較佳實施例之詳細說明
圖1展示堆疊式封裝(PoP)總成之實施例之橫截面側視圖，該PoP總成包括具有晶粒之底部封裝或支撐封裝，該晶粒相對於其所附接至之封裝基板處於懸掛式組態或負鼠式組態。參看圖1，PoP總成100包括以堆疊配置連接至封裝230之封裝110(在如所例示之z方向上位於封裝130上方或位於封裝130上之封裝110)。
封裝110包括封裝基板115，晶粒120經由例如晶粒與封裝基板之相應接觸點之間的視情況包括底部填充之凸塊製程或回焊製程電氣地且實體地連接至該封裝基板之表面。代表性地，晶粒120為記憶體晶粒。封裝110亦包括互連150(例如，焊料凸塊)，該等互連可操作以將封裝110連接至底部封裝或支撐封裝130。
圖1中所例示之PoP總成100之封裝130包括封裝基板135，晶粒140(例如，倒裝晶片微處理器)經由視情況包 括底部填充之凸塊製程或回焊製程電氣地且實體地連接至該封裝基板。如圖1中所例示，晶粒140連接至封裝基板135之側面，使得晶粒140相對於z方向位於封裝基板135之下且因此相對於封裝基板135處於負鼠式晶粒組態或懸掛式晶粒組態，如所觀察。換言之，在每一封裝基板包括相應晶粒連接至之晶粒側(晶粒120連接至封裝基板115且晶粒140連接至封裝基板135)及對置側或背側的情況下，封裝基板115之背側面向封裝基板135之背側。
在PoP總成100中，晶粒140就該晶粒至封裝基板145之附接而言且相對於晶粒120至封裝基板115之附接處於懸掛式組態或負鼠式組態(如所觀察)，其中封裝110位於封裝130上或位於封裝130上方。封裝基板135亦包括在封裝基板之晶粒側上之接觸墊155。在所展示之實施例中，PoP總成100連接至基板175，該基板為例如用於代表性地使用於諸如電話或其他攜帶型計算裝置之行動應用中的印刷電路板。PoP總成100經由焊料接頭160(焊球)連接至基板175，該等焊料接頭位於封裝基板135之接觸墊155與基板175之對應接觸墊之間。在一個實施例中，包括至基板及再分配層之任何互連的晶粒140之厚度或高度h1小於焊料接頭160之厚度或高度h2。
參看總成100，就封裝110至封裝130之連接而言，該連接可經由至在每一封裝之區域表面上各處配置的觸點或接觸墊之焊料接頭來進行。代表性地，圖1展示具有內部區域180及周邊區域185之封裝基板115，內部區域180 與周邊區域185共同界定封裝之區域表面。如所例示，接觸墊在內部區域180上各處配置且亦在周邊區域185上各處配置。此類接觸墊可在基板製造階段期間藉由佈線或分配至內部區域185之跡線或互連及形成對該等跡線或互連之接觸墊來形成。相較於僅具有在周邊設置之接觸墊(僅在周邊區域185內)的封裝基板，能夠使用封裝基板115之內部區域180用於基板與封裝130之間的互連點提供數目增加之互連點。圖1展示具有接觸墊145之封裝基板135，該等接觸墊設置於該封裝基板之與晶粒140所連接至之基板側面對置之表面上。接觸墊145與封裝基板115之接觸墊125(包括於該封裝基板之內部區域中)對準，且焊料接頭150(焊球)經由相應接觸墊連接該等封裝。
圖2展示PoP總成之另一實施例之橫截面側視圖，該PoP總成採用具有晶粒之底部封裝或支撐封裝，該晶粒相對於其所附接至之封裝基板處於懸掛式組態或負鼠式組態。參看圖2，總成200包括以堆疊配置連接至封裝230之封裝210(一者在如所例示之z方向上位於另一者上方或位於另一者上)。封裝210包括封裝基板215，晶粒220經由例如視情況包括底部填充製程之凸塊製程或回焊製程來電氣地且實體地連接至該封裝基板之表面。代表性地，晶粒220為倒裝晶片記憶體晶粒。圖2亦展示包括接觸墊225之封裝210，該等接觸墊位於基板之與晶粒220所連接至的側面對置之側面上。接觸墊225設置於在封裝基板之內部區域280周邊之區域285內。在一個實施例中，接觸墊225沿具有矩 形形狀或正方形形狀之封裝基板215之表面的四個側面之周邊或邊緣來設置。
圖2中之PoP總成200之封裝230包括封裝基板235，晶粒240(例如，倒裝晶片微處理器)經由視情況包括底部填充製程之凸塊製程或回焊製程連接至該封裝基板。如所例示，晶粒240連接至封裝基板235之側面，使得晶粒240相對於z方向位於封裝基板235之下且因此相對於封裝基板235處於負鼠式組態或懸掛式組態。封裝230之封裝基板235包括接觸墊245，該等接觸墊設置於基板之與晶粒240所附接至之側面對置的側面上。接觸墊245以周邊配置設置於封裝基板之表面上且與封裝210之接觸墊225對準。圖2展示設置於封裝210之接觸墊225與封裝230之接觸墊245之間以電氣地連接該等封裝之焊料接頭250(焊球)。封裝230之封裝基板235亦包括設置於封裝基板之晶粒側上的接觸墊255。圖2展示連接至接觸墊255之焊料接頭260，該等焊料接頭可操作以將PoP總成200連接至諸如印刷電路板之基板。
在圖1及圖2中之每一者中所展示之實施例中，每一總成代表性地包括設置於倒裝晶片球柵陣列封裝上之諸如商用記憶體封裝之封裝，該封裝具有負鼠式晶粒組態或懸掛式晶粒組態。藉由對於PoP總成之底部封裝或支撐封裝(例如，圖1之封裝130，圖2之封裝230)利用負鼠式晶粒組態或懸掛式晶粒組態，總成之z高度得以最小化。在一個實施例中，用於圖1中之封裝總成100及圖2中之封裝總成200的代表性z高度為約一毫米(mm)。
圖3展示PoP總成之另一實施例之橫截面側視圖，其中下伏封裝或支撐封裝係基於晶圓級封裝，尤其係基於嵌入式晶圓級球柵陣列(例如，eWLB)封裝。對於eWLB，封裝相關於晶粒觸點圍繞再分配層形成。圖3展示包括以堆疊配置電氣地連接至封裝330之封裝310的PoP總成300的橫截面側視圖，其中封裝310在z方向上位於封裝330上且位於封裝330上方。封裝310包括封裝基板315。例如記憶體晶粒之晶粒320電氣地且實體地連接至封裝基板315之表面(如所觀察之頂部表面)上的觸點。封裝基板315包括接觸墊325，該等接觸墊在與晶粒320所附接至之側面對置的側面上各處設置於封裝基板之周邊區域上。周邊區域385在內部區域380之周邊，且在一個實施例中，圍繞每一側面之周邊或邊緣或為具有四個側面之矩形封裝基板。
圖3中之PoP總成300之封裝330包括直接連接至再分配層335之(例如)微處理器之晶粒340。再分配層335包括晶粒側上之接觸墊(以連接至晶粒340)以及位於與晶粒340所連接至之側面對置的側面上之接觸墊345，該等接觸墊之間具有電跡線及互連。嵌入模製材料343中或設置於模製材料343中之通孔桿348連接至接觸墊345。如所例示，通孔桿348圍繞封裝基板之周邊區域形成且與封裝基板315之接觸墊325對準。在另一實施例中，穿模通孔(TMV)可作為通孔桿之替代物來使用。
連接至封裝基板330之封裝基板310連接至接觸墊325與通孔桿348之間的焊料接頭350。接觸墊之晶粒340 設置於封裝330之側面上，焊料接頭360連接至該等接觸墊以將總成300電氣地連接至為印刷電路板之基板。
圖4展示PoP總成之另一實施例之橫截面側視圖。總成400包括相對於z方向以堆疊組態連接至封裝430之封裝410，如所觀察，封裝410位於封裝430上方。在一個實施例中，封裝410包括諸如記憶體晶粒之晶粒420，該晶粒電氣地且實體地連接至在晶粒或封裝基板415之第一側面上之接觸點。封裝基板415具有位於封裝基板之與晶粒側對置的第二側面上之接觸墊425。此類接觸墊在封裝基板之內部區域480及周邊區域485上各處設置。在一個實施例中，封裝410為倒裝晶片球柵陣列封裝。
圖4中所例示之總成400中之封裝430包括以eWLB配置設置之晶粒440，該eWLB配置包括再分配層435及嵌入模製材料443中之通孔桿448。介電材料之再分配層包括在第一側面(如所觀察之底部側面)上之接觸點，該等接觸點連接至晶粒440之接觸點、導電互連/跡線及互連以將至第二接觸點之連接再分配於再分配層435之第二側面(如所觀察之頂部側面)上。此類接觸點中之相應接觸點連接至個別通孔桿448。通孔桿448於一個側面上連接至再分配層435，且於對置側面上提供用於將封裝430連接至封裝410之接觸點或接觸墊。圖4展示設置於封裝410之接觸墊425與封裝430之通孔桿448之間的焊料接頭450(焊球)。圖4亦展示於再分配層435之晶粒側(與通孔桿448對置之側面)上連接至接觸墊之焊料接頭460。在一個實施例中，焊料接頭460可 操作以將總成400連接至諸如印刷電路板之基板。
藉由使用包括如圖3及圖4中之處於負鼠式組態或懸掛式組態之晶粒的eWLB封裝，可實現PoP總成之1mm或更小之z高度。此外，底部封裝之負鼠式晶粒組態或懸掛式晶粒組態(如在圖3及圖4中所觀察)提供封裝、內部區域380(圖3)與內部區域480(圖4)之間的界面區域用於互連。圖4尤其展示利用內部界面區域用於具有球柵陣列配置之封裝之間的互連。
相關於以上實施例所描述之優點包括：封裝堆疊之1毫米或更小之z高度；用於頂部封裝之區域陣列容量；頂部封裝至底部封裝基板之直接接觸，從而提供自頂部封裝至底部封裝之減少之互連；直接晶粒附接之可能性；以及附接離散被動裝置，同時維持最小封裝高度之機會。
圖5展示三個PoP總成之橫截面側視圖，每一總成使用處於eWLB負鼠式組態之eWLB。封裝總成500A包括以堆疊組態電氣地連接至底部封裝530A之頂部封裝510A(如所觀察)。封裝510A包括(例如)為記憶體晶粒之晶粒520A，該晶粒在裝置側面上電氣地且實體地連接至再分配層515A。再分配層515包括在再分配層之與連接至晶粒520A之側面對置之側面上的接觸點525A。封裝510A亦展示晶粒520A所嵌入之模製材料527A。
封裝530A包括在晶粒側上連接至再分配層535A之晶粒540A，其中再分配層535A之對置側面連接至嵌入模製材料543A中之通孔桿548A。如所例示，封裝510A經由在 封裝510A之接觸墊525A與相關聯於封裝530A之通孔桿548A的接觸點之間的焊料接頭550A(焊球)連接至封裝535A。如所例示，封裝530A之晶粒540A處於負鼠式組態或懸掛式組態，設置於再分配層535A之下，如所觀察。
PoP總成500B包括以堆疊組態連接至封裝530B之封裝510B(如所觀察，封裝510B設置於封裝530B上或封裝530B上方)。在一個實施例中，封裝510B類似於封裝510A且包括連接至再分配層515B之晶粒520B，且該晶粒嵌入模製材料527B中。再分配層515B包括設置於再分配層之與晶粒520B所連接至之側面對置的側面上之接觸墊525B。
在一個實施例中，圖5中所例示之PoP總成500B之封裝530B類似於總成500A之封裝530A，且包括電氣地連接至再分配層535B之晶粒540B以及電氣地連接至嵌入模製材料543B中的通孔桿548B之再分配層。在總成500B中，封裝510B使用銅焊墊(SOP)或半球形焊球550B來電氣地連接至封裝530B。以此方式，封裝510B之接觸墊525B與封裝530B之通孔桿548B的接觸點之間的互連之z高度得以最小化。因而，PoP總成500B之z高度小於封裝總成500A之z高度。
PoP總成500C包括以堆疊組態連接至封裝530C之第一封裝510C，其中封裝510C位於封裝530C上或封裝530C上方，如所觀察。在此實施例中，封裝510C及封裝530C中之每一者包括處於負鼠式組態或懸掛式組態之晶粒。封裝510C包括連接至再分配層515C之晶粒520C。圖5亦展示 連接於再分配層515C之晶粒側上的通孔桿528C。在此實施例中，晶粒520C及通孔桿528C兩者均嵌入模製材料527C中。
在一個實施例中，PoP總成500C中之封裝530C類似於總成500B之封裝530B及總成500A之封裝530A。封裝530C包括連接至再分配層535C之晶粒540C以及通孔桿548C，該等通孔桿自再分配層535C之對置側面延伸且嵌入模製材料543C中。圖5展示連接於封裝510C之通孔桿528C的接觸點與封裝530C之通孔桿548C的接觸點之間的銅焊墊(SOP)或半球形焊球550C。如所例示，PoP總成500C之z高度或厚度小於PoP總成500B或PoP總成500A之z高度或厚度。
雖然已知用於形成eWLB封裝之技術，但圖6至圖8例示形成諸如圖5中之封裝530A或封裝530B的具有負鼠式晶粒組態或懸掛式晶粒組態之eWLB封裝的製程之橫截面側視圖。圖6展示具有黏著箔片以及置放於該黏著箔片上之若干通孔桿的模製載體之側視圖，該黏著箔片設置於該模製載體之表面上。模製載體610為(例如)黏著箔片620可附著至之不銹鋼材料。通孔桿630設置於黏著箔片620上，其中相應接觸點或接觸墊與該箔片接觸。在將通孔桿630設置於黏著箔片620上之後，在黏著箔片620上引入例如為液態或粒狀模製化合物之模製材料以使通孔桿630嵌入。
圖7展示在將通孔桿及模製材料與黏著層分離，且在該結構上引入再分配層以及將晶粒連接至該再分配層 之後的圖6之結構。在一個實施例中，模製材料640藉由使用(例如)一定熱預算之脫裂製程與黏著層620分離。參看圖7，藉由以下操作來引入再分配層：將介電質層650引入至藉由移除黏著層620而產生之表面上，且使用光微影技術將對通孔桿630之接觸點或接觸墊之觸點圖案化，繼之以電鍍技術以形成導電通孔及跡線。導電通孔及/或接觸點或接觸墊亦形成於介電質層650之表面上或介電質層650之表面附近，該表面與同通孔桿630及模製材料640接觸之表面對置。圖7展示電氣地且實體地連接至此類接觸點或接觸墊655之晶粒660，以及連接至接觸點或接觸墊655中之其他者的焊料接頭670(焊球)。
圖8展示在使模製材料變薄之後的圖7之結構。模製材料640經變薄以暴露通孔桿630中之每一者的接觸表面。在使模製材料變薄之後，封裝經組裝且可連接至用於PoP總成之第二封裝。在另一實施例中，處理順序亦可不同：在置放焊球及負鼠式晶粒之前使主體變薄。如圖8中所例示，該封裝包括處於負鼠式晶粒組態或懸掛式晶粒組態之晶粒(如所觀察，在z方向上位於再分配層之下)。
圖9例示根據一個實行方案之計算裝置700。計算裝置700容納板702。板702可包括許多部件，包括但不限於處理器704及至少一個通訊晶片706。處理器704實體地且電氣地耦接至板702。在一些實行方案中，至少一個通訊晶片706亦實體地且電氣地耦接至板702。在其他實行方案中，通訊晶片706為處理器704之部分。可利用諸如在如上所描 述之實行方案中之PoP總成以包括處理器404及另一晶片(例如，通訊晶片406，記憶體晶片)。
取決於其應用，計算裝置700可包括其他部件，該等其他部件可或可不實體地且電氣地耦接至板702。此等其他部件包括但不限於依電性記憶體(例如，DRAM)、非依電性記憶體(例如，ROM)、快閃記憶體、圖形處理器、數位信號處理器、加密處理器、晶片組、天線、顯示器、觸控螢幕顯示器、觸控螢幕控制器、電池、音訊編解碼器、視訊編解碼器、功率放大器、全球定位系統(GPS)裝置、羅盤、加速計、迴轉儀、揚聲器、攝影機及大容量儲存裝置(諸如硬碟片驅動機、光碟片(CD)、數位通用碟片(DVD)等)。
通訊晶片706致能用於將資料傳送至及傳送出計算裝置700之無線通訊。「無線」一詞及其派生詞可用以描述可經由非固態媒體藉由使用經調變電磁輻射來傳達資料的電路、裝置、系統、方法、技術、通訊頻道等。該術語並不暗示相關聯裝置不含有任何線，但是在一些實施例中，該等相關聯裝置可不含有任何線。通訊晶片706可實行若干無線標準或協定中之任何者，包括但不限於Wi-Fi(IEEE 802.11族)、WiMAX(IEEE 802.16族)、IEEE 802.20、長期演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍牙、其衍生物以及指定為3G、4G、5G及以上的任何其他無線協定。計算裝置700可包括多個通訊晶片706。例如，第一通訊晶片706可專用於較短範圍無線通訊，諸如Wi-Fi 及藍牙，且第二通訊晶片706可專用於較長範圍無線通訊，諸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO及其他。
計算裝置700之處理器704包括封裝於處理器704內的積體電路晶粒。「處理器」一詞可指代處理來自暫存器及/或記憶體的電子資料以將該電子資料變換成可儲存在暫存器及/或記憶體中的其他電子資料的任何裝置或裝置之部分。
通訊晶片706亦包括封裝於通訊晶片706內的積體電路晶粒。
在其他實行方案中，計算裝置700內容納之另一部件可含有包括諸如電晶體或金屬互連之一或多個裝置之積體電路晶粒。
在各種實行方案中，計算裝置700可為膝上型電腦、隨身型易網機、筆記型電腦、超極緻筆電、智慧型電話、平板電腦、個人數位助理(PDA)、超級行動PC、行動電話、桌上型電腦、伺服器、印表機、掃描器、監視器、機上盒、娛樂控制單元、數位攝影機、攜帶型音樂播放器或數位視訊記錄器。在其他實行方案中，計算裝置700可為處理資料的任何其他電子裝置。
實例
實例1為一種設備，其包括：第一封裝，其耦接至第二封裝，其中該第一封裝及該第二封裝中之每一者具有第一側面及對置之第二側面；第一晶粒，其耦接至該第 一封裝；以及第二晶粒，其耦接至該第二封裝之該第二側面，其中該第一封裝以堆疊配置耦接至該第二封裝，使得該第二封裝之該第一側面面向該第一封裝之該第二側面。
在實例2中，實例1之設備中之第一晶粒耦接至第一封裝之第一側面。
在實例3中，實例2之設備中之第一封裝經由在每一封裝之表面的內部各處之觸點耦接至第二封裝。
在實例4中，實例2之設備中之第一封裝經由在周邊配置之接觸點經由觸點耦接至第二封裝。
在實例5中，實例1之設備中之第一晶粒耦接至第一封裝之第二側面。
在實例6中，實例5之設備中之第一封裝經由在周邊配置之接觸點經由觸點耦接至第二封裝。
在實例7中，實例1之設備中之第二封裝包括在第一側面上之多個接觸點以及耦接至該等多個接觸點中之相應接觸點且耦接至在第一封裝之第二側面上之接觸點的通孔桿。
在實例8中，實例7之設備中之通孔桿耦接至位於第一封裝之第二側面上的接觸點上之焊料接頭。
在實例9中，實例7之設備中之第一晶粒耦接至第一封裝之第一側面。
在實例10中，實例7之設備中之第一晶粒耦接至第一封裝之第二側面。
實例11為一種設備，其包括堆疊式封裝組態，該 堆疊式封裝組態包括第一封裝，該第一封裝以堆疊配置耦接至第二封裝，其中第一封裝位於第二封裝上，該第一封裝包括第一封裝基板及第一晶粒且該第二封裝包括第二封裝基板及第二晶粒，其中第二晶粒設置於第二封裝基板之與第一封裝基板對置之側面上。
在實例12中，實例11之設備中之第一晶粒耦接至第一封裝基板之與第二封裝基板對置之側面。
在實例13中，實例12之設備中之第一封裝經由在每一封裝之表面的內部各處之觸點耦接至第二封裝。
在實例14中，實例12之設備中之第一封裝經由在周邊配置之接觸點經由觸點耦接至第二封裝。
在實例15中，實例11之設備中之第一晶粒耦接至第一封裝基板之面向第二封裝基板之側面。
實例16為一種方法，其包括將第一封裝以堆疊組態耦接至第二封裝，其中該第一封裝包括第一封裝基板及第一晶粒，且該第二封裝包括第二封裝基板及第二晶粒，其中第二晶粒設置於第二封裝基板之與第一封裝基板對置之側面上。
在實例17中，實例16之方法中之第一晶粒耦接至第一封裝基板之與第二封裝基板對置之側面。
在實例18中，實例16之方法中之將第一封裝耦接至第二封裝包括經由在每一封裝之表面的內部各處之觸點來耦接。
在實例19中，實例16之方法中之將第一封裝耦接 至第二封裝包括經由在周邊配置之接觸點經由觸點來耦接。
在實例20中，實例16之方法中之第一晶粒耦接至第一封裝基板之面向第二封裝基板之側面。
在實例21中，藉由實例16至實例20中之任一者之方法製造之積體電路封裝。
包括摘要中所述內容之本發明之所例示實行方案之以上描述不欲為窮舉性的或將本發明限於所揭示之精確形式。雖然本文出於例示性目的描述本發明之特定實行方案或用於本發明之實例，但是本發明範疇內之各種等效修改為可能的，如相關技術中之技術者將認識到的。
可根據以上詳細描述對本發明做出此等修改。以下申請專利範圍中所使用之術語不應理解為將本發明限於說明書及申請專利範圍中所揭示之特定實行方案。實情為，本發明之範疇將完全由以下申請專利範圍決定，申請專利範圍應根據請求項解釋之所確立原則來理解。
h1、h2‧‧‧厚度或高度
100‧‧‧PoP總成
110、130‧‧‧封裝
115、135、145‧‧‧封裝基板
120、140‧‧‧晶粒
125、155‧‧‧接觸墊
150、160‧‧‧焊料接頭
175‧‧‧基板
180‧‧‧內部區域
185‧‧‧周邊區域

Claims (18)

  1. 一種電子設備，其包含：一第一封裝，其耦接至一第二封裝，其中該第一封裝及該第二封裝中之每一者具有一第一側面及一對置之第二側面；一第一晶粒，其耦接至該第一封裝；以及一第二晶粒，其耦接至該第二封裝之該第二側面，其中該第一封裝以一堆疊配置耦接至該第二封裝，使得該第二封裝之該第一側面面向該第一封裝之該第二側面，且其中該第二封裝包含在該第一側面上之多個接觸點以及耦接至該等多個接觸點中之相應接觸點且耦接至在該第一封裝之該第二側面上之接觸點的通孔桿。
  2. 如請求項1之設備，其中該第一晶粒耦接至該第一封裝之該第一側面。
  3. 如請求項2之設備，其中該第一封裝經由在每一封裝之一表面的內部各處之觸點耦接至該第二封裝。
  4. 如請求項2之設備，其中該第一封裝經由在周邊配置之接觸點經由觸點耦接至該第二封裝。
  5. 如請求項1之設備，其中該第一晶粒耦接至該第一封裝之該第二側面。
  6. 如請求項5之設備，其中該第一封裝經由在周邊配置之接觸點耦接至該第二封裝。
  7. 如請求項1之設備，其中該等通孔桿耦接至位於該第一封裝之該第二側面上的該等接觸點上之焊料接頭。
  8. 一種電子設備，其包含：一堆疊式封裝組態，其包含一第一封裝，該第一封裝以一堆疊配置耦接至一第二封裝，其中該第一封裝位於該第二封裝上，該第一封裝包含一第一封裝基板及一第一晶粒，且該第二封裝包含一第二封裝基板及一第二晶粒，其中該第二晶粒設置於該第二封裝基板之與該第一封裝基板相反之一側面上，且其中該第二封裝包含在其另一側面上之多個接觸點以及耦接至該等多個接觸點中之相應接觸點且耦接至在該第一封裝之一側面上之接觸點的通孔桿。
  9. 如請求項8之設備，其中該第一晶粒耦接至該第一封裝基板之與該第二封裝基板相反之側面。
  10. 如請求項9之設備，其中該第一封裝經由在每一封裝之一表面的內部各處之觸點耦接至該第二封裝。
  11. 如請求項9之設備，其中該第一封裝經由在周邊配置之接觸點經由觸點耦接至該第二封裝。
  12. 如請求項8之設備，其中該第一晶粒耦接至該第一封裝基板之面向該第二封裝基板之一側面。
  13. 一種用以形成一堆疊式封裝組態之方法，其包含下列步驟：將一第一封裝以一堆疊組態耦接至一第二封裝，其中該第一封裝包含一第一封裝基板及一第一晶粒，且該 第二封裝包含一第二封裝基板及一第二晶粒，其中該第二晶粒設置於該第二封裝基板之與該第一封裝基板相反之一側面上，且其中該第二封裝包含在其另一側面上之多個接觸點以及耦接至該等多個接觸點中之相應接觸點且耦接至在該第一封裝之一側面上之接觸點的通孔桿。
  14. 如請求項13之方法，其中該第一晶粒耦接至該第一封裝基板之與該第二封裝基板相反之側面。
  15. 如請求項13之方法，其中將該第一封裝耦接至該第二封裝包含經由在每一封裝之一表面的內部各處之觸點來耦接。
  16. 如請求項13之方法，其中將該第一封裝耦接至該第二封裝包含經由在周邊配置之接觸點經由觸點來耦接。
  17. 如請求項13之方法，其中該第一晶粒耦接至該第一封裝基板之面向該第二封裝基板之一側面。
  18. 一種藉由如請求項13之方法製造之積體電路封裝。
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