CN1324110A - 集成电路封装的堆叠模组 - Google Patents
集成电路封装的堆叠模组 Download PDFInfo
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- CN1324110A CN1324110A CN00107649A CN00107649A CN1324110A CN 1324110 A CN1324110 A CN 1324110A CN 00107649 A CN00107649 A CN 00107649A CN 00107649 A CN00107649 A CN 00107649A CN 1324110 A CN1324110 A CN 1324110A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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Abstract
本发明涉及一种堆叠模组,它包括至少一层基底,该基底的正面至少设有一对集成电路晶片,并且涂有封胶。从而适用性更广泛,制程简单,又节省材料。
Description
本发明涉及一种堆叠模组。
目前，如图1所示，习知堆叠模组IA技术(以四层堆叠为例)，其中晶片11a被粘附在基底10a的正面上，并经封胶制程以固定晶片，另外，以相同程序，使晶片11b粘附在基底10b的正面并封胶，晶片11c粘附在基底10c的正面并封胶；晶片11d粘附在基底10d的正面并封胶，而后借具有连接基底10a与基座10b的突起物13a，连接基底10b与基底10c突起物13b，连接基底10c与基底10d的突起物13c共同将基底10a至10d形成四个一组的堆叠包装状态。
另外，依据相同堆叠模组IB技术(如图2所示)，晶片11e亦可粘附并封胶在基底10e的背面，并加以堆叠。
然而，上述习知堆叠模组具有缺点，因为该集成电路晶片粘附基底时，仅利用基底单面实施，层层堆叠之后，其整体包装的厚度相对过度膨胀，无法适用在对厚度有所限制的场合，如笔记型电脑、行动电话、个人数位助理或数位相机等装置。
再者，由于需要在数层基底上粘贴晶片封胶，并植上突起物后方能彼此堆叠，在制程上必须：每个基底先做完一次晶片粘着并封胶-植入突起物-彼此堆叠，其制程甚为繁复琐碎，影响产量。
鉴此，本发明的目的是提供一种集成电路封装的堆叠模组，它可有效使整体堆叠包装的厚度变薄，以适应在更多的场合，并能节省应用的材料及可缩短制程。
本发明的目的是这样实现的：一种集成电路封装的堆叠模组，它包括至少一层基底，该基底的正面至少设有一对集成电路晶片，并且涂有封胶。所述各基底相互堆叠，且相邻两基底之间设有突起物。
由于采用上述方案：适用性更广泛，制程简单，又节省材料。
下面结合附图和实施例对本发明进一步说明。
图1一种习知堆叠模组剖视图。
图2另一种习知堆叠模组剖视图。
图3本发明第一实施例示意图。
图4习知堆叠模组技术双层堆叠剖视图。
图5本发明第二实施例示意图。
如图3所示，第一实施例的堆叠模组2A，包含复数个基底20a及20b，该基底20a(基底20b)至少在其正面与背面粘贴有晶片21a、21b(晶片21c、21d)并粘有封胶22、且基底20a借突起物23a与已粘贴封胶晶片21c在上面并粘贴封胶，晶片21d在背面的基底20b互相以突出物23a连接堆叠而成。
依上述堆叠模组实施在本发明制程，可在一基底正面粘贴晶片及对晶片封胶时，同时进行背面的晶片粘贴及封胶，以缩短制程。
又，可由习知堆叠模组IC需二层基底10a、10b叠起来封装二晶片11a、11b，并以突出物13a连接堆叠的情形，如图4所示。
第二实施例是由上述习知技术缩减为如：堆叠模组2B，仅需一层基底20a就可封装二晶片21a、21b成为单一模组，如图5所示，大量节省基底与突起物的材料用料。
再者，可将堆叠包装每二层基底缩减为单层基底，如图5所示，因此，可大大地降低整体堆叠包装高度，增加更多的应用机会。
Claims (2)
1．一种集成电路封装的堆叠模组，其特征是：它包括至少一层基底，该基底的正面至少设有一对集成电路晶片，并且涂有封胶。
2．按权利要求1所述的集成电路封装的堆叠模组，其特征是：所述各基底相互堆叠，且相邻两基底之间设有突起物。
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| Application Number | Priority Date | Filing Date | Title |
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| CN00107649A CN1324110A (zh) | 2000-05-17 | 2000-05-17 | 集成电路封装的堆叠模组 |
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| CN00107649A CN1324110A (zh) | 2000-05-17 | 2000-05-17 | 集成电路封装的堆叠模组 |
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| CN1324110A true CN1324110A (zh) | 2001-11-28 |
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| CN00107649A Pending CN1324110A (zh) | 2000-05-17 | 2000-05-17 | 集成电路封装的堆叠模组 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105720049A (zh) * | 2014-12-15 | 2016-06-29 | 英特尔公司 | 负鼠晶片封装叠加设备 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105720049A (zh) * | 2014-12-15 | 2016-06-29 | 英特尔公司 | 负鼠晶片封装叠加设备 |
| EP3055881A4 (en) * | 2014-12-15 | 2017-09-13 | INTEL Corporation | Opossum-die package-on-package apparatus |
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