CN1846311A - 可堆叠的电子组件 - Google Patents

可堆叠的电子组件 Download PDF

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CN1846311A
CN1846311A CNA200480025558XA CN200480025558A CN1846311A CN 1846311 A CN1846311 A CN 1846311A CN A200480025558X A CNA200480025558X A CN A200480025558XA CN 200480025558 A CN200480025558 A CN 200480025558A CN 1846311 A CN1846311 A CN 1846311A
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wafer
substrate
level package
solder sphere
described substrate
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马克·艾里斯贝里
查尔斯·E·施密茨
琪·社·陈
维克多·艾利森
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Sanmina SCI Communication Equipment Co Ltd
Sanmina Corp
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Sanmina SCI Communication Equipment Co Ltd
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Abstract

本发明的实施中提供了一种可堆叠的芯片级封装，该可堆叠的芯片级封装用于提高存储密度，被装在有限区域或模块内。一种新的交替布线方案实现在堆叠式结构的每一级别下使用相同的走线，以有效地访问芯片级封装堆内的单个存储器器件。使用球栅阵列芯片级封装结构连同热相适应的材料降低了热裂化的风险，同时改善了散热。而且，该结构允许在芯片级封装上安装支撑部件，例如电容器和电阻器。

Description

可堆叠的电子组件
技术领域
本发明的多个实施例涉及可堆叠的电子组件。本发明的至少一个实施例涉及一种使用了这些可堆叠的组件的存储器模块块，使得较高的存储密度成为可能。
有关技术的描述
半导体小片(dice)，例如存储器小片，经常被封装以便保护和易于使用。一种类型封装为球栅阵列(BGA)封装，其中半导体小片置于基底(substrate)上。半导体小片具有多个通过接在基底和小片上的金属走线(trace)之间的金属丝而电连接的连结垫(bond pad)。基底上的走线在接触垫处终止，在其处附接导电元件例如焊接球被。接着BGA封装可以被置于电路板上并通过导电元件而电连接。BGA封装可以以多种方式被电连接至电路板的金属走线上，这些方式包括给导电元件(例如，焊接球)施加热或超声波
封装半导体小片时要考虑的一项为热裂化。当两种材料的热膨胀系数之间的差异使其之间的焊接点裂开时，可发生热裂化。例如，如果半导体小片被直接地焊接在具有基本上不同的膨胀系数的基底上，那么温度周期变化最终可使得焊接点例如焊接球裂开，从而引起电断开。为了解决封装半导体小片时的该问题，半导体小片和基底之间的区域通常未充满环氧树脂和/或其他材料，以协助防止热裂纹。
此外，半导体小片一般对物理撞击和环境条件相当脆弱而敏感。因此，小片或硅片一般被装在环氧树脂或塑料内以吸收和耗散撞击力并保护其不受环境条件的影响。
然而，将器件或小片未充满和/或封装将增加器件所保留的热。维持低工作温度一般增加了电子器件的可靠性、性能，和寿命。因此，由未充满和/或封装所引起的温度增加是保护电子器件而增加可靠性的不期望的副作用。
一种半导体部件为存储器部件，其一般包括密封或未被密封置于基底上的存储器小片。多年来，存储器部件在提供增加的存储能力同时保持了相同的尺寸。一般地，其通过减少各存储部件的尺寸而完成。
存储器部件经常被用于存储器模块中，其中许多这些存储器部件被置于单个基底上。然而，能够放置在一基底上的存储器部件的数量被模块的尺寸所限制。模块一般必须满足工业标准所建立的功能和物理规格或由特定应用所带来的限制。因此，存储器模块的存储能力经常受到物理尺寸局限的限制。特别地，存储器模块上可利用的表面面积限定了可以置于其上的存储器部件的数量。
一种增加存储器模块存储能力的技术为在彼此的顶部堆叠式存储器部件。对于相同表面面积，这提供了较大的存储能力。然而，可堆叠式的存储器部件的数量受到存储器模块的高度限制的限制和受到使用现有的为非堆叠式结构所设计的总线接口来访问堆叠式存储设备的复杂程度的限制。
因此，现有技术仍然在寻找一种增加存储设备堆叠式，并同时符合存储器模块的封装要求的经济的解决方案。
发明概述
本发明的一方面提供了一种可堆叠的半导体器件结构，其中每一半导体器件被焊接在芯片级球栅阵列封装(chip-scale ball grid arraypackage)上。本发明的第二方面通过使用受控热膨胀基底提供了一种降低焊接点热裂化的方法，该基底基本上与装在其上的半导体器件的膨胀系数相匹配。本发明的第三方面提供了一种半导体小片安装技术，其通过暴露了装在芯片级封装上的半导体小片的所有六个表面来改善散热。本发明的第四方面提供了一种芯片级球栅阵列封装，其允许部件例如电容器和电阻器装在其上。本发明的第五方面提供一种交错布线方案(staggered routing scheme)，实现在堆叠式结构的每一级别使用相同的走线。
本发明的一实施方案提供了一种具有堆叠式芯片级球栅阵列封装的存储器模块，这增加了该模块的存储容量，同时符合模块的尺寸要求。
附图简述
图1示出根据本发明的一个实施例的具有置于基底上的半导体小片的芯片级球栅阵列封装的侧视图。
图2示出根据本发明的一个实施例具有置于基底上的半导体小片的芯片级球栅阵列封装的表面图。
图3示出根据本发明的一个实施例使用存储器小片的一对堆叠式芯片级球栅阵列封装的侧视图。
图4示出根据本发明第二实施例的具有置于基底上的半导体小片的芯片级的球栅阵列封装的表面图。
图5示出根据本发明第二实施例的使用存储器小片的一对堆叠式芯片级球栅阵列封装的侧视图。
图6示出根据本发明一个实施例的在存储器模块的两个表面上的有堆叠式的存储器部件的存储器模块。
图7示出根据本发明一个实施例的用于可堆叠式封装的布线方案。
图8示出根据本发明一个实施例的堆叠式存储器部件。
详细描述
以下描述中给出了许多具体的细节以提供对本发明的全面理解。然而，本领域技术人员应该认识到，本发明在不具备这些具体的细节的情况下可以被实现。在其他实施例中，已知的方法、步骤，和/或部件并未得到详细的描述从而不至于使本发明的内容不必要地模糊。
在以下描述中，某个术语被用于描述本发明的一个或更多实施例的某些特征。例如，“小片”表示半导体器件，例如硅存储器器件，其未被用保护性的塑料、环氧树脂或其他材料封装或覆盖。术语“下侧联接元件”被用于表示相对刚性的电联接元件例如导电凸起、导电球(例如焊接球或金球)和导电棒。
本发明的一方面提供了一种可堆叠式半导体器件结构，其中每一半导体器件被焊接到具有球栅阵列连接的芯片级封装(CSP)上。本发明的第二方面提供了一种通过使用基本上与装于其上的半导体小片的膨胀系数相匹配的受控热膨胀基底而降低焊接点热裂化的方法。本发明的第三方面提供一种小片安装技术，其通过暴露装在芯片级封装内的小片的所有六个面而改善散热。本发明的第四方面提供了一种芯片级封装，其允许其上安装信号调节(过滤)部件，例如电容器和电阻器。本发明的第五方面提供了一种交错布线方案，实现对于堆叠式结构的每一级别使用相同的走线布线。
本发明的一实施方案提供了一种具有堆叠式存储部件的存储器模块，堆叠式这增加了模块的存储容量，同时符合模块的尺寸要求。
图1示出了根据本发明的一个实施例的芯片级球栅阵列封装100的侧视图，其包括置于基底104上的半导体小片102。芯片级球栅阵列封装100包括多个位于基底104的第一表面之上的焊接球108。一个或更多的焊接球108可以被电联接至半导体小片102和/或接触垫110。
本发明实施的一方面提供了焊接球108，其具有比半导体小片102高的轮廓以机械地保护半导体小片102不受直接地撞击等，而没有包封的缺点。焊接球108应当足够大从而它们高于在芯片级基底104的第一表面上的半导体小片102。将半导体小片102装在与焊接球108的相同的侧产生了倒装芯片组件，其中，接着半导体封装通过焊接球被联接至其它基底。此外，较高轮廓的焊接球使得封装100在没有半导体小片102干扰的情况下被装在其它基底上。
本发明的另一方面提供了一种降低半导体小片和基底之间的接触点的热裂化的方法，该基底上装有半导体小片。传统的芯片安装技术一般使用丝焊将半导体小片电连接至基底上的接触点。然而，该安装技术一般需要半导体小片和安装面之间的间隔注射或未填满固定材料例如环氧树脂以将半导体小片固定到基底。然而，如上所述，这是不期望的，因为它倾向于阻碍半导体器件的散热。
如图1所示，使用刚性下侧联接元件106比如金球或焊接球、导电聚合物接触件和/或底部凸起金属化(under bump metallization)将半导体小片102装在基底104上。为了防止联接元件106因为热循环而裂开，本发明的一个特征在于提供基底104具有与半导体小片102的热膨胀系数匹配的热膨胀系数基底。这样半导体小片102和基底104以类似的速度膨胀和收缩，由此降低了施加在联接元件106上的应力。为了实现它，本发明的一方面使用了受控热膨胀(CTE)基底，该基底基本上匹配装在其上的半导体小片的膨胀系数。
一般的安装基底具有近似为每摄氏度百万分之16至18(ppm/℃)的膨胀系数，同时硅半导体具有约3ppm/℃的额定膨胀系数。通过温度循环，这种膨胀系数上的不一致通常导致所述安装基底和硅半导体器件之间的电气互连部分裂开。使用Coffin-Manson型分析，例如，可确定匹配的膨胀系数的适当范围。可接受的匹配根据温度范围(超过其将循环材料)、在器件使用寿命期间温度循环的数量、基底的尺寸、将第一基底联接至第二基底所使用的材料等而变化。两种材料(例如硅半导体和安装基底)越接近严格匹配，情况越好。可容易调整特殊应用的热-机械可靠性以满足特定工作环境的需要(例如，焊接球和/或金球相互连接和/或导电聚合物材料)。
在本发明的一个实施方案中，芯片级球栅阵列封装包括受控CTE安装基底，该基底具有6到9ppm/℃之间的膨胀系数，且硅半导体器件具有约3ppm/℃的额定膨胀系数。该安装基底的膨胀系数可以通过改变其组成而调整。
根据已知为Thermount 85NT的CTE材料Coffin-Manson型分析，对于使用具有约为3ppm/℃膨胀系数的硅半导体器件的存储器模块，约8ppm/℃的膨胀系数为可接受的。例如该匹配对于双列直插存储器模块(DIMM)应用为可接受的。
一般地，本发明使用了由特制的CTE所制造的基底材料以确保给定器件在工作环境下的可靠性。一些可以被使用的材料类型包括：
Arlon(Thermount)85NT，其具有6.0至9.0ppm/℃的热膨胀系数，取决于树脂含量；
Arlon(Thermount)55NT，其具有7.0至10.0ppm/℃的热膨胀系数，取决于树脂含量；
CMC(铜-钼-铜芯)，其具有大于或等于5.5ppm/℃的热膨胀基本系数，其中通过改变铜厚度来改变CTE从而改变该系数(例如，(铜-钼-铜)5/90/5＝5.58ppm/℃，13/74/13＝5.8ppm/℃)；
CTC(铜-因瓦合金-铜)芯，具有大于或等于5.1ppm/℃的热膨胀基本系数，其中通过改变铜厚度来改变CTE而改变该系数(例如，(铜-因瓦合金-铜)20/60/20＝5.2ppm/℃)；
陶瓷芯，具有4.5-6.5ppm/℃的热膨胀系数(例如，AlN为4.5，铝为6.5)。
本发明的另一方面通过让半导体小片102的六个面暴露而提供半导体小片102改善的散热。不同于一般是未填满或完全封装的现有技术，本发明暴露了半导体小片的所有六个侧，包括半导体小片下侧的大部分。即，使用焊接球、底部凸起金属化和/或其它相似的电联接元件106来安装半导体小片102，在芯片级基底104和半导体小片102的下侧之间会产生间隙。由于小片102的所有表面(包括下侧面)现在接触气流，半导体小片102的散热得到改善。注意焊接球108比所安装的半导体小片102轮廓高，这意味着半导体小片102的上表面也接触气流。
图2示出了根据本发明的一实施例使用了置于基底上的半导体小片的芯片级球栅阵列封装的表面视图。芯片级球栅阵列封装可包括沿基底104表面的多个焊接球108。在一实施方式中，如图2所示，可沿行与列排列多个焊接球108，而在其它实施方式中，可以以其它结构排列多个焊接球108。
图3示出了根据本发明一实施例的使用存储器小片的堆叠式芯片级球栅阵列封装。多个芯片级球栅阵列封装302和304被垂直地堆叠，第一封装302的第一表面被联接至第二封装304的相对第二表面等等，以为了得到堆中的每一连续层。特别地，第二封装304的第二表面上的接触垫(例如图1中的110)被电联接至第一封装302的第一表面上的相应垫。由于相比半导体小片305，焊接球308具有更大的垂直轮廓或高度，这允许将第一封装302堆叠在第二封装304之上。以这种方式，可堆叠多个封装以增加可装在给定区域上的半导体器件的密度。例如，当半导体小片301和305为存储器小片时，堆栈多个存储器件相比单层芯片构造，增加了存储器模块的容量。
本发明的一方面提供了一种芯片级的球栅阵列封装，其允许部件例如电容器和电阻器装在其上。通过使用连接件303将半导体小片305安装在基底304上，在半导体小片305之上基底上，表面空间是空置的。在一实施方式中，半导体小片上方的表面空间常包括垫306，其中信号调节部件装于其上。该表面区域具有一个或更多垫306以连结位于其上的信号过滤部件。这允许安装片上电子部件310，例如电容器和电阻器，其可以被用于对来自或去往半导体小片305的信号进行调节。能够将部件310装在自身的封装基底(例如芯片级基底)上，对于现有技术中限制为将所述部件仅安装在封装的外部来说，是一个优点。在本发明的一实施方式中，该部件310为信号调节电容器和上拉/下拉电阻器。
根据其它方式实施，在不脱离本发明范围的情况下，可以使用其它球栅阵列配置。
图4示出了根据本发明第二实施例的具有装于基底上的半导体小片的芯片级球栅阵列封装的表面图。该配置包括具有多个焊接球连接件404和406的基底402，该焊接球连接件404和406被设置为两列，位于装在基底402上的半导体小片408的两侧中的任一侧。该半导体小片408可以通过刚性下侧联接元件410和412装在基底402上，所述联接元件410和412也沿着半导体小片408的长度方向排成两列。下侧联接元件410和412被电联接至多个焊接球404和406。所述焊接球被电联接至基底402相对面上的垫上。
在本发明的一实施方式中，不管需要多少长度来有效地解决要堆叠的芯片级封装的最大数量，球/电互连接件(例如404和406)的外侧列为每侧两倍宽。例如，一般的二百五十六(256)兆字节(Mb)同步动态(SD)随机存取存储器(RAM)硅器件所需的基本I/O计数为四十八(48)，其中两个用于独特的“寻址”。由此，在一高执行中，仅需要四十八(48)个I/O球/电互连接件404和406。因为每一额外的器件需要独特的时钟实现寻址互连接和独特的芯片选择寻址互连接，所以，两个高的堆将需要该堆中的所有芯片级封装具有五十(50)个互连接件404和406。四个高的堆将需要五十四(54)个球/电互连接件404和406等。
图5示出了根据本发明第二实施例的使用存储器小片的堆叠式芯片级球栅阵列封装的侧视图。多个芯片级封装502和504为如图4中所示那样的芯片级封装，其以与图3中所示的堆叠式封装类似的方式并如所示出的那样堆叠。每一基底502和504包括沿着装在其上的半导体器件510和512的两侧的两列焊接球506。多个下侧电互连接件508将半导体器件510和512联接至其各自的基底502和504。每一基底也包括位于与半导体器件相对的表面上的多个垫514，该垫514被用于联接信号过滤部件516。
图6示出根据本发明的一实施例的在存储器模块614的两个表面上具有多个堆叠式存储器部件602、604、606、608、610和612的存储器模块600。多个堆叠式芯片级球栅阵列封装602、604、606、608、610和612可以被装在基底614的一个或更多表面上。
在本发明的一实施方式中，半导体器件(例如102)可以为装在堆叠式芯片级封装(例如602、604、606、608、610和612)上的随机存取存储器器件。接着堆叠式封装(例如602、604、606、608、610和612)被装在一基底的两侧或任一侧上，以形成存储器模块600，例如单列直插存储器模块(SIMM)或双列直插存储器模块(DIMM)。存储器模块600的尺寸要求可限制被堆叠的封装数量(例如100)。
在其它实施方式中，堆叠式封装可被直接装在计算机主板或其它类型模块中。
图7示出根据本发明一实施例用于封装堆700的布线方案。实施可堆叠式封装结构的一个困难在于提供一种独立地访问每一半导体器件(例如存储器器件)的简单方法。现有技术的可堆叠式结构一般在堆的每一级别需要定制的芯片级封装基底，以能够独立地访问每一芯片。即对于位于封装堆内的每一芯片上的相同管脚，必须在模块基底的接口上使用不同的电接触以独立地访问每一芯片。这一般使得例如用跨接线或走线穿孔(tracepunching)对封装堆的每一级别定制芯片级封装基底成为必要，以提供从模块板的接口至芯片的合适的布线。然而，制造和组装该堆叠式半导体小片级封装昂贵而麻烦，这是因为对于堆叠式封装的每一级别的一般都需要定制的芯片级封装基底。
根据本发明的一实施例，基底在堆叠式封装700的每一级别使用相同的芯片级封装基底701a-d，其中半导体小片703a-d以相同的方式被装在每一芯片级基底701a-d上。对于堆叠式封装700的每一级别使用相同的基底701a-d和以相同的方式安装小片703a-d避免了必须定制每一级别的成本和困难。由此，多个芯片级球栅阵列封装701a-d可以被制造，随后无须考虑任何特别的顺序而被组装入堆中。
在堆叠式封装700的每一级别使用相同的芯片级封装由于新的布线方案而成为可能，该布线方案允许独立地访问每一半导体小片703a-d并无须定制基底701a-d。新布线方案通过堆叠式封装700的所有级别提供了级联连接以将每一半导体小片703a-d电联接至主要访问点(例如基底701a上的焊接球)。
根据新布线方案的实施方式，每一基底701a-d包括多个装在基底701a-d的第一表面上的焊接球705和多个位于基底701a-d的第二相对面上的相应垫707。互连接件709用以将焊接球705电连接至垫707上。如图7所示的级联方案允许从主要访问点(例如基底701a上的焊接球)独立地访问每一半导体小片基底。该级联方案将最接近半导体小片的焊接球电联接至半导体小片的接触件上。例如，焊接球711被电连接至半导体小片703a上的接触件702。这种布线方案的实施使得位于芯片级封装基底的第一表面上的焊接球被电联接至位于该芯片级封装基底的第二表面上的接近半导体小片的垫。例如，焊接球713被电联接至垫715。类似地，焊接球717和719被联接至接近半导体小片703a的垫。在堆叠式封装700中的每一芯片级封装基底701a-d执行这种布线方案。当芯片级封装基底如图所示那样被堆叠在相互间的顶部上时，第一基底(例如701a)的第二表面上的每一垫(例如707)被电联接至第二基底(例如701b)的第一表面上的相应焊接球(例如720b)。从而，级联布线方案使得一基底(例如701a)的焊接球(例如713)被电联接至第二基底(例如701b)的接近半导体小片接口点的焊接球(例如722)。结果，焊接球713被电连接至连接件706，焊接球717被电连接至连接件710，和焊接球719被电连接至连接件714。可在半导体小片的另一侧执行类似的方案，从而小片连接件704、708、712和716被电联接至基底701a上的焊接球。接着，半导体器件的堆叠式封装可以通过基底701a的第一表面上的焊接球而被联接至另一基底或接口上。
注意到焊接球可以不同方式并的使用不同的焊接球布局级联，而在不脱离本发明范围。例如，使用类似于图4和5中所示的芯片级封装可执行级联布线方案。通过跨越多个封装层在焊接球之间来回曲折前进以有效地实施图7中所示的布线方案，可以以两个焊接球列(例如404)来实施该级联方案。即，一基底的第一表面上的电垫被电连接至该基底的第二表面上焊接球且基本上与其它垫和焊接球的直线排列成对角线。在其他实施方案中，也可以通过跨越多个芯片级封装层沿着单个列(例如半导体封装400的外列之一)互连接焊接球，来实施图7所示的布线方案。总而言之，图7和8中所示出的交错布线方案可以由多种方式包括跨越堆的各层的单列、单行和/或对角/Z字形互连接来实现。
在其它实施方式中，仅仅焊接球一部分使用级联方案互连接，而剩余焊接球部分以非级联的方式横跨堆叠式封装连接。即，堆的所有层的相同位置的一些焊接球一般可以被连接。
图8示出了根据本发明一实施方式的堆叠式存储器封装800。存储器小片802a-d被装在芯片级封装基底804a-d上。在一实施方式中，存储器部件802a-d共享共用的数据线或总线，该总线用以向存储器器件802a-d写入数据(例如比特)和/或从存储器器件802a-d读出数据(例如比特)。为了向特定的存储器器件正确地写入和/或从其读出，对单个芯片的选择和时钟启用实施图7所示的级联方案。单个封装的存储器小片802a-d可以被启用和/或不启用，在焊接球806-813处提供合适信号。例如，存储器小片802a可以通过在焊接球806处启用时钟(Clock)A和在焊接球807处启用芯片选择(Select)A而被访问。类似地，存储器器件802b可以通过在焊接球808处启用ClockB和在焊接球809处启用芯片Select B而被访问，存储器器件802c可以通过在焊接球810处启用ClockC和在焊接球811处启用芯片SelectC而被访问，和存储器器件802d可以通过在焊接球812处启用ClockD和在焊接球813处启用芯片SelectD而被访问。
许多情况下，堆叠式存储器或半导体封装的尺寸受特定实施中安装其的可利用的空间限制。从而，本发明的一种实施应用了间隔紧密的部件以最大化堆叠式封装的半导体或存储器密度。例如，在本发明的一实施方式中，基底(例如图2中的104或图4中的402)0.2mm厚十(10)mm宽其长度约为十二(12)毫米(mm)。此外，焊接球(例如图3中的308或图5中的506)直径可以约为0.5mm，而特定芯片级封装(例如图1中的100)的高度或厚度约为0.5mm。类似地，两个堆叠的芯片级封装(例如如图3和5所示的封装)的厚度或高度约为1.00mm等。
尽管一些示例性实施例已经被描述并在附图中被示出，然而应该理解这些实施例仅仅为示例性的并不用于限制本广泛性的发明，且因为多种其它变型为可能的，该发明并不限定于图示和已描述的特定结构和设置。本领域技术人员将理解，在不脱离本发明的范围和精神的情况下，可以对于上述优选实施例进行多种变化及修改。例如，虽然半导体小片已被用于阐释本发明，然而在本发明的一个或更多方面，在不脱离本发明的情况下，任何其它的电子器件或部件也可以被替换使用。因此，应该理解，在落入所附权利要求的范围内的情况下，除了本文中所特别描述地外还可以以其它方式实现本发明。

Claims (26)

1、一种芯片级封装，包括：
基底，其具有第一表面和相对的第二表面，所述基底由受控的热膨胀材料构成；
存储器小片，使用多个刚性下侧联接元件其被装在所述基底的第一表面上，所述基底具有的膨胀系数基本与所述存储器小片的膨胀系数相匹配；
多个焊接球，其按球栅阵列构造装在所述基底的第一表面上，所述焊接球的至少一个被电联接至所述下侧联接元件的至少一个；
多个垫，其被联接至所述基底的第二表面，在交错的布线方案中，每一垫被电联接至所述多个焊接球的一个或更多个；和
一个或更多电子部件，其装在所述基底的第二表面上，位于基本上与所述存储器小片相对的区域，其中，电子部件和所述存储器小片从所述基底突出的的结合距离要小于焊接球和垫从所述基底突出的距离。
2、如权利要求1的芯片级封装，进一步包括：
所述第一表面上的电导走线，其将至少一个焊接球电连接至所述存储器小片。
3、如权利要求1的芯片级封装，其中，所述基底包括受控热膨胀材料，所述材料与所述存储器小片的膨胀系数充分匹配。
4、如权利要求1的芯片级封装，其中，所述下侧联接元件使得所述存储器小片的下侧表面被基本暴露。
5、一种芯片级封装，包括：
基底，其具有第一表面和相对的第二表面；
半导体器件，使用焊接球其被装在所述基底的第一表面上；
多个焊接球，其按球栅阵列构造被装在所述基底的第一表面上，所述焊接球的至少一个被电连接至所述半导体器件；
多个垫，其被联接至所述基底的第二表面，在交错布线方案中，每一垫被电联接至所述多个焊接球的一个或更多个；和
一个或更多电子部件，其被装在所述基底的第二表面上。
6、如权利要求5的芯片级封装，其中，所述电子部件在基本上与所述半导体器件相对的区域被装在所述基底的第二表面上。
7、如权利要求6的芯片级封装，其中，所述电子部件包括电容器和电阻器。
8、如权利要求5的芯片级封装，其中，电子部件和所述半导体器件从所述基底突出的结合距离要小于焊接球和垫从所述基底突出的距离。
9、如权利要求5的芯片级封装，其中，所述基底包括受控热膨胀材料，其的膨胀系数基本上与所述半导体器件的膨胀系数相匹配。
10、如权利要求5的芯片级封装，其中，所述半导体器件为硅器件，和所述基底包括受控热膨胀材料，所述材料基本上与所述硅器件的膨胀系数相匹配。
11、如权利要求5的芯片级封装，进一步包括：
所述第一表面上的电导走线，其将至少一个焊接球电连接至所述半导体器件。
12、如权利要求5的芯片级封装，其中，所述半导体器件为硅存储器器件。
13、如权利要求5的芯片级封装，其中，使用刚性下侧联接元件，所述半导体器件被联接至所述第一表面。
14、如权利要求13的芯片级封装，其中，所述刚性下侧联接元件使得所述半导体器件的下侧表面被基本上暴露。
15、一种可堆叠的电子组件，包括：
多个芯片级封装，以堆叠式构造排列所述多个芯片级封装，每一芯片级封装包括
基底，具有第一表面和相对的第二表面，所述基底由受控热膨胀材料形成；
半导体器件，使用下侧联接元件其被联接到所述基底的第一表面上的走线，所述基底具有的膨胀系数基本上与所述半导体器件的膨胀系数相匹配；
多个焊接球，其按球栅阵列构造被装在所述基底的第一表面上，至少一个焊接球被电联接至所述半导体器件；
多个垫，其被联接至所述基底的第二表面，在交错布线方案中，每一垫被电连接至所述多个焊接球的一个或更多；和
一个或更多电子部件，其被装在所述基底的第二表面上，位于基本与所述半导体器件相对的区域，其中，电子部件和所述半导体器件从所述基底突出的结合距离要小于焊接球和垫从所述基底突出的距离。
16、如权利要求15的可堆叠的电子组件，其中，所述多个芯片级封装具有相同的布线走线。
17、如权利要求15的可堆叠的电子组件，其中，第一芯片级封装的第一表面上的所述焊接球被联接至第二芯片级封装的第二表面上的所述垫。
18、如权利要求15的可堆叠的电子组件，其中，所述交错布线方案允许从第一芯片级封装中的多个焊接球来访问堆中的所述每一芯片级封装的相同的下侧联接元件。
19、如权利要求15的可堆叠的电子组件，其中，所述下侧联接元件使得所述半导体器件的下侧表面被暴露。
20、一种存储器模块包括：
主基底，其具有接口以将所述存储器模块联接至其它器件；和一个或更多的存储器器件堆，其被联接至所述主基底的第一表面，至少一个存储器器件堆包括
多个芯片级封装，所述多个芯片级封装以堆叠式构造排列并在所述芯片级封装的第一表面和相对的第二表面上具有相同布线走线，每一芯片级封装包括
基底，其具有第一表面和相对的第二表面，
存储器半导体小片，使用下侧联接元件其被电联接至所述基底的第一表面上的走线，和
多个焊接球，其被装在所述基底的第一表面上，所述焊接球的至少一个被电联接至所述存储器半导体小片。
21、如权利要求20的存储器模块，其中
所述基底由受控热膨胀材料形成，
所述基底具有的膨胀系数基本与所述存储器半导体小片的膨胀系数相匹配，
所述多个焊接球按球栅阵列构造装在所述基底的第一表面上，和
每一芯片级封装进一步包括
多个垫，其被联接至所述基底的第二表面上，在交错布线方案中，每一垫被电联接至所述多个焊接球的一个或更多个，和
一个或更多电子部件，其被装在所述基底的第二表面上，位于基本上与所述存储器半导体小片相对的区域，其中，电子部件和所述存储器半导体小片从所述基底突出的结合距离要小于焊接球和垫从所述基底突出的距离。
22、如权利要求21的存储器模块，其中，所述交错布线方案允许从第一芯片级封装的多个焊接球来访问堆中的所述所有芯片级封装的相同下侧联接元件。
23、如权利要求20的存储器模块，其中，所述存储器模块为双列直插存储器模块。
24、如权利要求20的存储器模块，进一步包括：
一个或更多存储器器件堆，其被联接至所述主基底的第二表面。
25、如权利要求20的存储器模块，其中，所述芯片级封装被堆叠，其一芯片级封装的第一表面上的所述焊接球被联接至另一芯片级封装的第二表面上的垫。
26、如权利要求20的存储器模块，其中，所述下侧联接元件使得所述存储器半导体小片的下侧表面暴露。
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