CN105679749A - 层叠封装件和具有该层叠封装件的移动计算装置 - Google Patents

层叠封装件和具有该层叠封装件的移动计算装置 Download PDF

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Publication number
CN105679749A
CN105679749A CN201510888713.0A CN201510888713A CN105679749A CN 105679749 A CN105679749 A CN 105679749A CN 201510888713 A CN201510888713 A CN 201510888713A CN 105679749 A CN105679749 A CN 105679749A
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China
Prior art keywords
chip dies
pcb
chip
circuit board
printed circuit
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CN201510888713.0A
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English (en)
Inventor
权兴奎
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN105679749A publication Critical patent/CN105679749A/zh
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    • G—PHYSICS
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    • G06F1/1633—Constructional details or arrangements of portable computers not specific to the type of enclosures covered by groups G06F1/1615 - G06F1/1626
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Abstract

提供了一种层叠封装件和具有该层叠封装件的移动计算装置，所述层叠封装件可以包括：第一印刷电路板(PCB)；底部封装件，包括附着到第一印刷电路板的第一芯片裸片和第二芯片裸片；顶部封装件，包括第二印刷电路板和附着到第二印刷电路板的第三芯片裸片，并且覆盖在底部封装件之上；和/或第一堆叠连接焊球和第二堆叠连接焊球，电连接在第一印刷电路板和第二印刷电路板之间，并且仅形成在底部封装件的各个侧面之中的相互面对的两个侧面周围。

Description

层叠封装件和具有该层叠封装件的移动计算装置
本申请要求于2014年12月5日提交到韩国知识产权局(KIPO)的第10-2014-0173629号韩国专利申请的优先权，该韩国专利申请的全部内容通过引用包含于此。
技术领域
发明构思的一些示例实施例可以总体上涉及层叠封装件。发明构思的一些示例实施例可以总体上涉及仅在保护材料的侧面之中的相互面对的两个侧面周围设置堆叠连接球的层叠封装件，其中，堆叠连接球用于堆叠底部封装件和顶部封装件，保护材料包括附着到底部封装件的印刷电路板的芯片裸片(chipdie)。发明构思的一些示例实施例可以总体上涉及具有该层叠封装件的移动计算装置。
背景技术
半导体芯片的封装可以涉及用于将芯片裸片连接到外部系统的中间步骤工序。随着诸如智能电话和平板个人计算机(PC)的便携式装置的使用看起来增加，制造者可以尝试开发更轻且更小的便携式装置。相当大量的集成电路可以用于便携式装置中，每个集成电路可以封装到半导体封装件中。
层叠封装件(PoP)可以节省系统板的空间，并且可以对于制造智能电话和平板PC以减小便携式电子装置尺寸来说是必需的。具体来讲，存储器封装件(例如，顶部封装件)可以堆叠在逻辑封装件(例如，底部封装件)之上以减小印刷电路板(PCB)的表面积。为了减小包括多个层叠封装件的便携式电子装置的尺寸，会需要减小多个层叠封装件中的每个层叠封装件的尺寸和高度。
发明内容
发明构思的一些示例实施例可以提供层叠封装件。
发明构思的一些示例实施例可以提供仅在保护材料的侧面之中的相互面对的两个侧面周围设置堆叠连接球的层叠封装件，其中，堆叠连接球用于堆叠底部封装件和顶部封装件，保护材料包括附着到底部封装件的印刷电路板的芯片裸片。
发明构思的一些示例实施例可以提供具有层叠封装件的移动计算装置。
在一些示例实施例中，层叠封装件可以包括：第一印刷电路板(PCB)；底部封装件，包括附着到第一PCB的第一芯片裸片和第二芯片裸片；顶部封装件，包括第二PCB和附着到第二PCB的第三芯片裸片，并且覆盖在底部封装件之上；和/或第一堆叠连接焊球和第二堆叠连接焊球，电连接在第一PCB和第二PCB之间，并且仅形成在底部封装件的侧面之中的相互面对的两个侧面周围。
在一些示例实施例中，第一芯片裸片可以包括调制解调器芯片裸片。第二芯片裸片可以包括动态随机存取存储器(DRAM)芯片裸片或伪静态随机存取存储器(SRAM)芯片裸片。底部封装件可以包括系统级封装(SiP)。
在一些示例实施例中，第一芯片裸片可以通过第一凸点以倒装芯片结构附着到第一PCB。第二芯片裸片通过第二凸点以倒装芯片结构附着到第一PCB。
在一些示例实施例中，第一芯片裸片可以通过第一凸点以倒装芯片结构附着到第一PCB。第二芯片裸片可以通过第二凸点以倒装芯片结构附着到第一PCB。可以用毛细底部填充(CUF)材料填充第一芯片裸片和第一PCB之间的空的空间与第二芯片裸片和第一印刷电路板之间的空的空间。
在一些示例实施例中，第一芯片裸片可以通过第一凸点以倒装芯片结构附着到第一PCB。第二芯片裸片可以通过第二凸点以倒装芯片结构附着到第一PCB。可以利用模塑底部填充(MUF)材料包封第一芯片裸片和第一印刷电路板之间的空的空间、第二芯片裸片和第一印刷电路板之间的空的空间、第一芯片裸片以及第二芯片裸片。
在一些示例实施例中，第一芯片裸片可以通过凸点以倒装芯片结构附着到第一PCB。第二芯片裸片可以通过引线键合附着到第一PCB。可以利用模塑底部填充(MUF)材料包封第一芯片裸片和第一印刷电路板之间的空的空间、第一芯片裸片以及第二芯片裸片。
在一些示例实施例中，顶部封装件还可以包括附着到第二PCB的存储控制器。存储控制器可以被构造成控制第三芯片裸片的操作。第三芯片裸片可以包括基于闪存的存储芯片裸片。
在一些示例实施例中，可以仅通过第一堆叠连接焊球发送用于第三芯片裸片和存储控制器的操作的所有信号和所有电源电压。
在一些示例实施例中，每个第二堆叠连接焊球可以处于电气浮置状态。
在一些示例实施例中，可以通过第一堆叠连接焊球发送用于第三芯片裸片和存储控制器的操作的所有信号与用于第三芯片裸片和存储控制器中的至少一个的操作的第一电源电压的一部分。可以通过第二堆叠连接焊球发送用于第三芯片裸片和存储控制器中的至少一个的操作的第一电源电压的剩余部分。
在一些示例实施例中，通过附着到第一PCB的底表面的各个焊球输入的第一电源电压的所述剩余部分可以通过第一PCB发送到底部封装件和第二堆叠连接焊球。
在一些示例实施例中，第一芯片裸片和第二芯片裸片可以仅通过形成在第一PCB中的信号线来相互发送信号或可以相互接收信号。
在一些示例实施例中，移动计算装置可以包括：系统板；第一封装件，附着到系统板；和/或电源管理集成电路(PMIC)，附着到系统板并被配置成通过系统板将第一电源电压供应到第一封装件。第一封装件可以包括：第一印刷电路板(PCB)；底部封装件，包括附着到第一PCB的第一芯片裸片和第二芯片裸片；顶部封装件，包括第二PCB和附着到第二PCB的第三芯片裸片，并且覆盖在底部封装件之上；和/或第一堆叠连接焊球和第二堆叠连接焊球，电连接在第一PCB和第二PCB之间，并且仅形成在底部封装件的侧面之中的相互面对的两个侧面周围。
在一些示例实施例中，第一芯片裸片可以包括调制解调器芯片裸片。第二芯片裸片可以包括动态随机存取存储器(SRAM)芯片裸片或伪静态随机存取存储器(SRAM)芯片裸片。底部封装件可以包括系统级封装(SiP)。
在一些示例实施例中，顶部封装件还可以包括附着到第二PCB的存储控制器。存储控制器可以被配置成控制第三芯片裸片的操作。第三芯片裸片可以包括基于闪存的存储芯片裸片。
在一些示例实施例中，可以仅通过第一堆叠连接焊球发送用于第三芯片裸片和存储控制器的操作的所有信号与用于第三芯片裸片和存储控制器的操作的所有第一电源电压。
在一些示例实施例中，移动计算装置还可以包括附着到系统板的第二封装件并包括应用处理器芯片裸片。PMIC可以被配置成通过系统板将第二电源电压供应到应用处理器芯片裸片。系统板可以包括信号线，信号线被配置成发送在应用处理器芯片裸片和第一封装件之间发送或接收的信号。信号线可以通过第一PCB连接到第一堆叠连接焊球之中的对应的连接焊球。
在一些示例实施例中，系统板可以包括接地线。第一电源电压可以包括操作电压和接地电压。来自第一堆叠连接焊球之中的与接地电压有关的连接焊球可以通过第一PCB连接到接地线。可以通过第一PCB将操作电压供应到第一堆叠连接焊球之中对应的连接焊球。
在一些示例实施例中，可以仅通过第一堆叠连接焊球来发送用于第三芯片裸片和存储控制器的操作的所有信号与来自第一电源电压之中的用于第三芯片裸片和存储控制器中的至少一个的操作的第二电源电压。可以仅通过来自第二堆叠连接焊球之中的各个连接焊球来发送来自第一电源电压之中的用于第三芯片裸片和存储控制器中的至少一个的操作的第三电源电压。可以通过附着到第一PCB的底表面的焊球输入的第三电源电压通过第一PCB被发送到所述各个连接焊球和底部封装件。
在一些示例实施例中，移动计算装置还可以包括附着到系统板的第二封装件并且包括应用处理器芯片裸片。PMIC可以被配置成通过系统板将第四电源电压供应到应用处理器芯片裸片。系统板可以包括信号线，其中，信号线发送在应用处理器芯片裸片和第一封装件之间发送或接收的信号。信号线可以通过第一PCB连接到第一堆叠连接焊球之中的对应的连接焊球。
在一些示例实施例中，电子装置可以包括：第一印刷电路板(PCB)；第一芯片裸片，在第一PCB上；第二芯片裸片，在第一PCB上；第二PCB，在第一芯片裸片和第二芯片裸片上；至少一个第三芯片裸片，在第二PCB上；和/或第一堆叠连接焊球和第二堆叠连接焊球，电连接在第一PCB和第二PCB之间。第一堆叠连接焊球可以在第一芯片裸片和第二芯片裸片的与第二堆叠连接焊球相对的侧面上。
在一些示例实施例中，第二芯片裸片可以在第一芯片裸片上。
在一些示例实施例中，第一芯片裸片可以包括调制解调器芯片裸片。第二芯片裸片可以包括动态随机存取存储器(DRAM)芯片裸片或伪静态随机存取存储器(SRAM)芯片裸片。
在一些示例实施例中，第一芯片裸片可以通过第一凸点以倒装芯片结构附着到第一PCB。第二芯片裸片可以通过第二凸点以倒装芯片结构附着到第一PCB。
在一些示例实施例中，第一芯片裸片可以通过第一凸点以倒装芯片结构附着到第一PCB。第二芯片裸片可以通过第二凸点以倒装芯片结构附着到第一PCB。用毛细底部填充(CUF)材料填充第一芯片裸片和第一印刷电路板之间的空的空间以及第二芯片裸片和第一印刷电路板之间的空的空间。
在一些示例实施例中，第一芯片裸片可以通过第一凸点以倒装芯片结构附着到第一PCB。第二芯片裸片可以通过第二凸点以倒装芯片结构附着到第一PCB。可以利用模塑底部填充(MUF)材料包封第一芯片裸片和第一PCB之间的空的空间、第二芯片裸片和第一PCB之间的空的空间、第一芯片裸片以及第二芯片裸片。
在一些示例实施例中，第一芯片裸片可以通过凸点以倒装芯片结构附着到第一PCB。第二芯片裸片可以通过引线键合附着到第一PCB。可以利用模塑底部填充(MUF)材料包封第一芯片裸片和第一印刷电路板之间的空的空间、第一芯片裸片以及第二芯片裸片。
在一些示例实施例中，电子装置还可以包括在第二PCB上的存储控制器。存储控制器可以被配置成控制至少一个第三芯片裸片的操作。
附图说明
通过下面结合附图对示例实施例的详细描述，以上和/或其它方面和优势将变得更明显并且更容易理解，在附图中：
图1至图14是根据发明构思的一些示例实施例的底部封装件的剖视图；
图15至图18是根据发明构思的一些示例实施例的包括底部封装件和顶部封装件的层叠封装件的剖视图；
图19至图20是根据发明构思的一些示例实施例的包括底部封装件和顶部封装件的层叠封装件的剖视图；
图21是示出根据发明构思的一些示例实施例的设置在底部封装件的两个面对的侧面周围的第一堆叠连接焊球和第二堆叠连接焊球的实施例示例的平面图；
图22和图23是包括利用激光打孔技术暴露的并且连接到第一堆叠连接焊球和第二堆叠连接焊球的焊球的底部封装件的剖视图；
图24是根据发明构思的一些示例实施例的包括在移动计算装置中的封装组件的剖视图；
图25是包括图24中示出的封装件组件的移动计算装置的框图。
具体实施方式
现在将参照附图更充分地描述示例实施例。然而，实施例可以以许多不同形式来实现并且不应被解释为受限于这里阐述的实施例。相反，提供这些示例实施例使得该公开将是彻底的和完整的，并将向本领域的技术人员充分传达范围。在附图中，为了清晰起见，会夸大层和区域的厚度。
将理解的是，当元件被称为“在”另一组件“上”、“连接到”、“电连接到”或“结合到”另一组件时，该元件可以直接在所述另一组件上、连接到、电连接到或结合到所述另一组件，或者可以存在中间组件。相反，当组件被称为“直接在”另一组件“上”、“直接连接到”、“直接电连接到”或“直接结合到”另一组件时，不存在中间元件。如在这里所使用的，术语“和/或”包括一个或更多个相关所列项的任意组合和所有组合。
将理解的是，尽管在这里可以使用术语第一、第二、第三等来描述各种元件、组件、区域、层和/或部分，但是这些元件、组件、区域、层和/或部分不应该受到这些术语的限制。这些术语仅用来将一个元件、组件、区域、层和/或部分与另一元件、组件、区域、层和/或部分区分开。例如，在不脱离示例实施例的教导的情况下，第一元件、组件、区域、层和/或部分可以被称为第二元件、组件、区域、层和/或部分。
为了易于描述，这里可使用诸如“在……之下”、“在……下方”、“下面的”、“在……上方”、“上面的”等空间相对术语来描述如图中所示的一个组件和/或特征与另一个组件和/或特征(或其他组件和/或特征)的关系。将理解的是，除了附图中描绘的方位之外，空间相对术语还意在包含装置在使用或操作中的不同方位。
在这里所使用的术语仅出于描述特定示例实施例的目的并且不意图限制示例实施例。如在这里所使用的，除非上下文另外清楚地指示，否则单数形式“一个(种、者)”和“所述”也意图包括复数形式。还将理解的是，当在本说明书中使用术语“包括”和/或“包含”或其变型时，说明存在陈述的特征、整体、步骤、操作、元件和/或组件，但是不排除存在或添加一个或更多个其他的特征、整体、步骤、操作、元件、组件和/或它们的组。
这里可以参照作为理想化的示例实施例(和中间结构)的示意图的剖视图来描述示例实施例。如此，预计将出现例如由制造技术和/或公差导致的图示的形状的变化。因此，示例实施例不应该被解释为局限于这里示出的区域的具体形状，而是将包括例如由制造导致的在形状上的偏差。例如，示出为矩形的注入区域将通常在其边缘处具有圆形或弯曲的特征和/或注入浓度的梯度，而不是从注入区到非注入区的二元变化。同样地，由注入形成的埋区可能导致在埋区与进行注入所发生的表面之间的区域中的一些注入。因此，在附图中示出的区域实际上是示意性的，它们的形状不意图示出装置的区域的实际形状，它们的形状不意图限制示例实施例的范围。
除非另有定义，否则这里使用的所有术语(包括技术术语和科学术语)具有与示例实施例所属领域的普通技术人员通常理解的含义相同的含义。还将理解的是，术语(例如，在通用字典中所定义的那些术语)应该被理解为具有与在相关领域的环境中它们的含义一致的含义，并且除非在这里清楚地这样定义，否则不应该以理想化的或过于形式化的含义来解释。
现在将参照附图中示出的示例实施例，其中，同样的附图标记可以始终指示同样的组件。
图1至图14是根据发明构思的一些示例实施例的底部封装件的剖视图。
参照图1，底部封装件100A可以包括第一印刷电路板(PCB)110、均附着或安装在第一PCB110的顶表面上的第一芯片裸片130和第二芯片裸片140。焊球112可以附着到第一PCB110的底表面。焊球131可以附着到第一PCB110的顶表面。焊球112或焊球131可以是凸点、焊料凸点或铜凸点。焊球112包括焊球11至焊球14。
本说明书中描述的焊球、凸点、焊料凸点或铜凸点是互连件的一些示例实施例。焊球112可以通过焊盘附着到第一PCB110的底表面。具有导电性的焊盘可以是引脚或接地焊盘(landpad)。
芯片裸片可以是芯片或裸片。根据一些示例实施例，图1至图14中示出的底部封装件100A至底部封装件100J、底部封装件100A-1、底部封装件100B-1、底部封装件100C-1和底部封装件100D-1可以以系统级封装(SiP)来实现；然而，示例实施例不限于此。
第一芯片裸片130可以以倒装芯片结构附着到第一PCB110。根据一些示例实施例，第一芯片裸片130可以通过焊球131附着到第一PCB110。根据一些示例实施例，第一芯片裸片130可以以调制解调器芯片裸片或支持宽带码分多址(WCDMA)通信方法的调制解调器芯片裸片来实现；然而，示例实施例不限于此。
因为第一芯片裸片130通过焊球131附着到第一PCB110，第一PCB110的顶部与第一芯片裸片130之间的空的空间可以用底部填充材料133来填充。例如，底部填充材料133可以通过毛细底部填充(CUF，capillaryunderfill)工艺来填充所述空间。因此，通过CUF工艺填充空的空间的底部填充材料被称作CUF材料。
第二芯片裸片140可以通过裸片粘接材料141附着到第一PCB110。根据一些示例实施例，裸片粘接材料141可以是膜或液体环氧粘合剂；然而，示例实施例不限于此。根据一些示例实施例，第二芯片裸片140可以以动态随机存取存储器(DRAM)芯片裸片或伪静态随机存取存储器(SRAM)芯片裸片来实现；然而，示例实施例不限于此。伪SRAM可以包括具有SRAM接口的DRAM微型核。
第二芯片裸片140可以利用引线键合与第一PCB110接触。此外，第二芯片裸片140可以利用引线143来向第一PCB110发送信号或从第一PCB110接收信号。第一芯片裸片130和第二芯片裸片140可以并排附着到第一PCB110。
图1示出了一种示例实施例，在该示例实施例中，第一芯片裸片130以倒装芯片结构附着到第一PCB110，第二芯片裸片140通过裸片粘接材料141附着到第一PCB110；然而，示例实施例不限于此。第一芯片裸片130和第二芯片裸片140可以通过呈现在第一PCB110中的信号线SL相互电连接。因此，第一芯片裸片130和第二芯片裸片140可以通过信号线SL相互发送或接收信号。
电源电压可以包括操作电压和接地电压。电源电压可以提供电力。第一操作电压VDD1可以通过焊球11和第一PCB110供应到第一芯片裸片130，接地电压VSS可以通过焊球13和第一PCB110供应到第一芯片裸片130。第二操作电压VDD2可以通过焊球12和第一PCB110供应到第二芯片裸片140，接地电压VSS可以通过焊球14和第一PCB110供应到第二芯片裸片140。
即，与第一芯片裸片130的第一操作电压VDD1和接地电压VSS(例如，电源电压)有关的接触件或引脚可以通过焊球11和13引脚输出，与第二芯片裸片140的第二操作电压VDD2和接地电压VSS(例如，电源电压)有关的接触件或引脚可以通过焊球12和14引脚输出。
参照图2，底部封装件100B包括附着到第一PCB110的第一芯片裸片130和第二芯片裸片140。参照图1和图2，可以通过焊球16和第一PCB110将操作电压VDD提供到附着到第一PCB110的第一芯片裸片130和第二芯片裸片140，并可以通过焊球17和第一PCB110将接地电压VSS提供到附着到第一PCB110的第一芯片裸片130和第二芯片裸片140。即，与第一芯片裸片130和第二芯片裸片140中的每个芯片裸片的操作电压VDD和接地电压VSS有关的接触件或引脚可以通过焊球16和17引脚输出。
参照图3，底部封装件100C可以包括堆叠在第一芯片裸片130上或上方的第二芯片裸片140。第二芯片裸片140可以通过裸片粘接材料141堆叠在第一芯片裸片130的顶表面上方。第二芯片裸片140可以通过引线和焊盘连接到第一PCB110。即，第二芯片裸片140可以通过引线键合连接到第一PCB110。
第一芯片裸片130和第二芯片裸片140可以通过呈现在第一PCB110中的信号线SL来相互连接。因此，第一芯片裸片130和第二芯片裸片140可以通过呈现在第一PCB110中的信号线SL来相互发送或接收信号。
第一操作电压VDD1可以通过焊球21供应到第一芯片裸片130，接地电压VSS可以通过焊球23供应到第一芯片裸片130。第二操作电压VDD2可以通过焊球22供应到第二芯片裸片140，接地电压VSS可以通过焊球24供应到第二芯片裸片140。
参照图3和图4，底部封装件100D包括堆叠在第一芯片裸片130上或上方的第二芯片裸片140。附着到第一PCB110的第一芯片裸片130和第二芯片裸片140通过焊球26被提供有操作电压VDD，并且通过焊球27被提供有接地电压VSS。
参照图5，底部封装件100E包括附着到第一PCB110的第一芯片裸片130和第二芯片裸片140。第一芯片裸片130和第二芯片裸片140中的每个可以以倒装芯片结构附着到第一PCB110。
第二芯片裸片140可以通过焊球131a附着到第一PCB110。第一PCB110的顶部与第二芯片裸片140之间的空的空间可以用底部填充材料133a来填充。例如，底部填充材料133a可以是CUF材料。第一芯片裸片130和第二芯片裸片140可以通过呈现在第一PCB110中的信号线SL来相互发送或接收信号。
第一操作电压VDD1通过焊球31供应到第一芯片裸片130，接地电压VSS通过焊球33供应到第一芯片裸片130。第二操作电压VDD2通过焊球32供应到第二芯片裸片140，接地电压VSS通过焊球34供应到第二芯片裸片140。
参照图6，底部封装件100F包括附着到第一PCB110的第一芯片裸片130和第二芯片裸片140。附着到第一PCB110的第一芯片裸片130和第二芯片裸片140通过焊球36被提供有操作电压VDD，并且通过焊球37被提供有接地电压VSS。
参照图7，底部封装件100G包括附着到第一PCB110的第一芯片裸片130和第二芯片裸片140。第一芯片裸片130和第二芯片裸片140中的每个以倒装芯片结构附着到第一PCB110。
可以通过模塑底部填充(MUF，moldedunderfill)工艺利用MUF材料MOLD来对第一芯片裸片130和第二芯片裸片140进行模塑。此时，第一芯片裸片130和第二芯片裸片140中的每个芯片裸片与第一PCB110之间的空的空间可以用MUF材料MOLD来填充。例如，MUF材料MOLD可以是环氧树脂模塑化合物(EMC)；然而，示例实施例不限于此。
第一操作电压VDD1通过焊球41供应到第一芯片裸片130，接地电压VSS通过焊球43供应到第一芯片裸片130。第二操作电压VDD2通过焊球42供应到第二芯片裸片140，接地电压VSS通过焊球44供应到第二芯片裸片140。
参照图8，底部封装件100H包括附着到第一PCB110的第一芯片裸片130和第二芯片裸片140。第一芯片裸片130和第二芯片裸片140中的每个以倒装芯片结构附着到第一PCB110。
可以利用MUF材料MOLD来对第一芯片裸片130和第二芯片裸片140进行模塑。此时，第一芯片裸片130和第二芯片裸片140中的每个芯片裸片与第一PCB110之间的空的空间可以用MUF材料MOLD来填充。附着到第一PCB110的第一芯片裸片130和第二芯片裸片140通过焊球46被提供有操作电压VDD，并且通过焊球47被提供有接地电压VSS。
参照图9，底部封装件100I包括附着到第一PCB110的第一芯片裸片130和第二芯片裸片140。第一芯片裸片130和第二芯片裸片140中的每个以倒装芯片结构附着到第一PCB110。
第一芯片裸片130与第一PCB110之间的空的空间可以通过CUF工艺填充有底部填充材料133，第二芯片裸片140与第一PCB110之间的空的空间可以通过CUF工艺填充有底部填充材料133a。可以通过MUF工艺利用MUF材料MOLD来包封第一芯片裸片130的外围和第二芯片裸片140的外围。
第一操作电压VDD1可以通过焊球51供应到第一芯片裸片130，接地电压VSS可以通过焊球53供应到第一芯片裸片130。第二操作电压VDD2可以通过焊球52供应到第二芯片裸片140，接地电压VSS可以通过焊球54供应到第二芯片裸片140。
参照图10，底部封装件100J包括附着到第一PCB110的第一芯片裸片130和第二芯片裸片140。第一芯片裸片130和第二芯片裸片140中的每个以倒装芯片结构附着到第一PCB110。
可以通过CUF工艺和MUF工艺来包封第一芯片裸片130和第二芯片裸片140。附着到第一PCB110的第一芯片裸片130和第二芯片裸片140通过焊球56被提供有操作电压VDD，并且通过焊球57被提供有接地电压VSS。
参照图1和图11，底部封装件100A-1包括以倒装芯片结构附着到第一PCB110的第一芯片裸片130和通过引线键合连接到第一PCB110的第二芯片裸片140。
可以由通过MUF工艺形成的保护材料150来包围第一芯片裸片130和第二芯片裸片140。例如，保护材料150可以是环氧树脂模塑化合物(EMC)；然而，示例实施例不限于此。
参照图2和图12，底部封装件100B-1包括以倒装芯片结构附着到第一PCB110的第一芯片裸片130和通过引线键合连接到第一PCB110的第二芯片裸片140。可以由通过MUF工艺形成的保护材料150来包围第一芯片裸片130和第二芯片裸片140。例如，保护材料150可以是EMC；然而，示例实施例不限于此。
参照图3和图13，底部封装件100C-1包括堆叠在第一芯片裸片130上或上方的第二芯片裸片140。可以由通过MUF工艺形成的保护材料150来包围第一芯片裸片130和第二芯片裸片140。例如，保护材料150可以是EMC；然而，示例实施例不限于此。
参照图4和图14，底部封装件100D-1包括堆叠在第一芯片裸片130上或上方的第二芯片裸片140。可以由通过MUF工艺形成的保护材料150来包围第一芯片裸片130和第二芯片裸片140。例如，保护材料150可以是EMC；然而，示例实施例不限于此。
图15至图18是根据发明构思的一些示例实施例的包括底部封装件和顶部封装件的层叠封装件的剖视图。参照图11和图15，顶部封装件TPG的第二PCB170可以通过互连件160(例如，堆叠连接焊球160)电连接到第一PCB110。如图17中所示，堆叠连接焊球160可以包括第一堆叠连接焊球SJB1和第二堆叠连接焊球SJB2。如上所述，堆叠连接焊球可以连接在形成在第一PCB110的顶表面上的焊盘与形成在第二PCB170的底表面上的焊盘之间。顶部封装件TPG可以堆叠在底部封装件100A-1之上。
顶部封装件TPG可以包括附着到第二PCB170的至少一个第三芯片裸片。在图15至图18中为了便于描述，示出了四个第三芯片裸片173、177、181和185与四个裸片粘接材料171、175、179和183；然而，示例实施例不限于此。因此，顶部封装件TPG中包括的第三芯片裸片的数量和裸片粘接材料的数量可以根据一些示例实施例而不同地改变。
四个第三芯片裸片173、177、181和185中的每个可以是基于闪存的存储芯片裸片(例如，逻辑NOTAND(NAND)闪存芯片裸片或逻辑NOTOR(NOR)闪存芯片裸片)；然而，示例实施例不限于此。四个第三芯片裸片173、177、181和185中的每个可以通过引线187相互连接。此外，四个第三芯片裸片173、177、181和185中的每个可以通过引线187向第二PCB170发送信号或从第二PCB170接收信号。
裸片粘接材料171、175、179和183中的每个可以是膜或液体环氧树脂粘合剂；然而，示例实施例不限于此。
顶部封装件TPG还可以包括利用裸片粘接材料189-1附着到第二PCB170的存储控制器189-2。当四个第三芯片裸片173、177、181和185中的每个是NAND闪存芯片裸片时，存储控制器189-2可以是NAND闪存控制器。存储控制器189-2可以通过引线189-3向第二PCB170发送信号或从第二PCB170接收信号。
可以利用保护材料190来对四个第三芯片裸片173、177、181和185、存储控制器189-2以及引线187和引线189-3进行模塑。可以通过MUF工艺形成保护材料190；然而，示例实施例不限于此。例如，保护材料190可以是EMC；然而，示例实施例不限于此。
图17是当从A方向观察包括底部封装件100A-1和顶部封装件TPG的层叠封装件时的剖视图。即，图17是层叠封装件的前剖视图，图19是层叠封装件的横向剖视图。
图21是示出设置在底部封装件的两个面对的侧面周围的第一堆叠连接焊球SJB1和第二堆叠连接焊球SJB2的实施例示例的平面图。参照图17和图21，可以仅在保护材料150的四个侧面之中的相互面对的两个侧面周围形成第一堆叠连接焊球SJB1和第二堆叠连接焊球SJB2，其中，保护材料150包括第一芯片裸片130和第二芯片裸片140。即，第一堆叠连接焊球SJB1和第二堆叠连接焊球SJB2可以以蝶形结构(butterflystructure)形成。
参照图17，用于发送电源电压(例如，第三操作电压VDD3和接地电压VSS)和信号SIG的焊盘可以通过第一堆叠连接焊球SJB1和第一PCB110由焊球112之中的至少两个焊球引脚输出，其中，所述电源电压和信号SIG对包括在顶部封装件TPG中的第三芯片裸片173、177、181和185中的至少一个的操作和存储控制器189-2的操作是必需的。
此外，仅发送对第三芯片裸片173、177、181和185中的至少一个的操作所必需的电源电压(例如，操作电压和接地电压)的焊盘可以通过第二堆叠连接焊球SJB2之中的至少两个连接焊球连接到第一PCB110中的金属线。操作电压VDD、VDD1或VDD2和接地电压VSS可以供应到第一芯片裸片130、第二芯片裸片140以及第三芯片裸片173、177、181和185中的至少一个。
参照图18，连接在底部封装件100A-1＇与顶部封装件TPG之间的第二堆叠连接焊球SJB2可以不发送任意操作电压或任意信号。此时，第二堆叠连接焊球SJB2可以被称作电气浮置状态。操作电压VDD、VDD1或VDD2与接地电压VSS可以通过对应的焊球仅供应到第一芯片裸片130和第二芯片裸片140。
在本说明书中操作电压VDD、VDD1、VDD2和VDD3中的每个共同地涉及一个或更多个操作电压，发送操作电压VDD、VDD1、VDD2和VDD3中的每个操作电压的焊球共同地涉及一个或更多个焊球。此外，发送信号SIG的焊球涉及发送多个信号的焊球。
图19和图20是根据发明构思的一些示例实施例的包括底部封装件和顶部封装件的层叠封装件的剖视图。
层叠封装件可以包括参照图1至图14描述的包括第一芯片裸片130和第二芯片裸片140的底部封装件(100A至100J、100A-1、100B-1、100C-1或100D-1,统一地“100”)和参照图15描述的顶部封装件。根据一些示例实施例，将要包括在层叠封装件中的底部封装件的结构可以根据层叠封装件的设计规格而不同地改变。
参照图19，仅发送对第三芯片裸片173、177、181和185中的至少一个第三芯片裸片的操作所必需的电源电压(例如，操作电压和接地电压)的焊盘可以通过第二堆叠连接焊球SJB2之中的至少两个连接焊球连接到第一PCB110中的金属线。
第二堆叠连接焊球SJB2之中的至少两个连接焊球不通过第一PCB110的焊球独立地引脚输出。因此，操作电压VDD、VDD1或VDD2与接地电压VSS可以同时供应到顶部封装件TPG与包括第一芯片裸片130和第二芯片裸片140的底部封装件100。
参照图20，连接在底部封装件100与顶部封装件TPG之间的第二堆叠连接焊球SJB2可以不发送任意操作电压和任意信号。参照图17至图20，发送信号SIG的所有第一焊盘可以仅连接到第一堆叠连接焊球SJB1，其中，信号SIG对于包括在顶部封装件TPG中的第三芯片裸片173、177、181和185与存储控制器189-2的操作是必需的。
如图17和图19中所示，发送第三操作电压VDD3和接地电压VSS(例如，电源电压)的第二焊盘可以连接到第一堆叠连接焊球SJB1，其中，第三操作电压VDD3和接地电压VSS对于包括在顶部封装件TPG中的第三芯片裸片173、177、181和185和/或存储控制器189-2的操作是必需的，发送电源电压(VDD、VDD1和VDD2中的至少一个与接地电压VSS)的第三焊盘可以连接到第二堆叠连接焊球SJB2，其中，电源电压对于包括在顶部封装件TPG中的第三芯片裸片173、177、181和185和/或存储控制器189-2的操作是必需的。此时，第二焊盘的数量可以大于第三焊盘的数量。
如图18和图20中所示，发送第三操作电压VDD3和接地电压VSS(例如，电源电压)的第二焊盘可以仅连接到第一堆叠连接焊球SJB1，其中，第三操作电压VDD3和接地电压VSS对于包括在顶部封装件TPG中的第三芯片裸片173、177、181和185和存储控制器189-2的操作是必需的，第二堆叠连接焊球SJB2可以保持电气浮置状态。如图21中所示，第一堆叠连接焊球SJB1和第二堆叠连接焊球SJB2仅设置在两个面对的侧面周围。可以仅通过第一堆叠连接焊球SJB1来发送向顶部封装件TPG发送的信号SIG或从顶部封装件TPG发送的信号SIG。
图22和图23是包括连接到第一堆叠连接焊球和第二堆叠连接焊球并且利用激光打孔技术暴露的焊球的底部封装件的剖视图。
在图22中，对于底部封装件100-1，第一芯片裸片130接收通过对应的第一焊球输入的电源电压，第二芯片裸片140接收通过对应的第二焊球输入的电源电压。在图23中，对于底部封装件100-2，第一芯片裸片130接收通过对应的公共的焊球输入的电源电压，第二芯片裸片140接收通过所述公共的焊球输入的电源电压。
如图22和图23中所示，在利用保护材料150对包括在底部封装件100-1和底部封装件100-2中的每个底部封装件中的第一芯片裸片130、第二芯片裸片140、焊球131和引线143进行模塑之后，可以利用激光打孔技术来暴露可以连接到第一堆叠连接焊球SJB1和第二堆叠连接焊球SJB2的焊球145。因此，通过激光打的通孔暴露的焊球145可以通过红外(IR)回流电连接到第一堆叠连接焊球SJB1和第二堆叠连接焊球SJB2。焊球145可以形成在第一PCB110的顶表面上。
图24是根据发明构思的一些示例实施例的包括在移动计算装置中的封装件组件的剖视图。参照图1至图24，包括在移动计算装置中的封装件组件200可以包括系统板210、包括底部封装件100和顶部封装件TPG的层叠封装件(或第一封装件)、电源管理集成电路(PMIC)205和第二封装件230。例如，系统板210可以执行PCB的功能。
本说明书中描述的移动计算装置可以在移动电话、智能电话、平板PC、移动互联网装置(MID)、可穿戴式装置或可穿戴式计算机、膝上型计算机、物联网(IoT)装置或万物互联(IoE)装置中实现。
第一封装件可以通过焊球112附着到系统板210。PMIC205可以通过对应的焊球附着到系统板210。第二封装件230可以通过焊球231附着到系统板210。
从PMIC205输出的第一电源电压PW1可以通过嵌入在系统板210中的第一电压线、焊球112中对应的焊球以及第一PCB110来供应到第一堆叠连接焊球SJB1中的至少一个。
从PMIC205输出的第二电源电压PW2可以通过嵌入在系统板210中的第二电压线中的至少一条和焊球231来供应到第二封装件230。从PMIC205输出的第三电源电压PW3可以通过嵌入在系统板210中的第三电压线和对应的焊球来供应到无线芯片裸片250。
由第一堆叠连接焊球SJB1之中的对应的连接焊球输出的信号可以通过嵌入在系统板210中的信号线来发送到第二封装件230，从第二封装件230输出的信号可以通过嵌入在系统板210中的信号线SL1来发送到第一堆叠连接焊球SJB1之中的对应的连接焊球。第一封装件中包括的第一芯片裸片130可以通过嵌入在系统板210中的信号线SL2向无线芯片裸片250发送信号或从无线芯片裸片250接收信号。
第一封装件、PMIC205、第二封装件230和无线芯片裸片250中的每个的接地线可以连接到嵌入在系统板210中的接地线GND。第一封装件的接地线可以连接到第一芯片裸片130的接地线、第二芯片裸片140的接地线与第三芯片裸片173、177、181和185中的每个的接地线。
第二封装件230可以包括通过焊球231连接到系统板210的第三PCB233、通过互连件连接到第三PCB233的第四芯片裸片235、保护第四芯片裸片235的保护材料237和连接第三PCB233与第四PCB241的互连件239。
互连件239可以指堆叠连接焊球。根据一些示例实施例，第四芯片裸片235可以以倒装芯片结构附着到第三PCB233。根据一些示例实施例，第四芯片裸片235可以利用裸片粘接材料附着到第三PCB233。此时，第四芯片裸片235可以通过引线向第三PCB233发送信号或从第三PCB233接收信号。根据一些示例实施例，第四芯片裸片235可以指应用处理器(AP)芯片裸片或SoC；然而，示例实施例不限于此。
第二封装件230还可以包括第五芯片裸片243，第五芯片裸片243可以附着在第四PCB241上。根据一些示例实施例，第五芯片裸片243可以指易失性存储芯片裸片或非易失性存储芯片裸片。例如，第五芯片裸片243可以以DRAM芯片裸片实现。
根据一些示例实施例，第五芯片裸片243可以以倒装芯片结构附着到第四PCB241。根据一些示例实施例，第五芯片裸片243可以利用裸片粘接材料附着到第四PCB241。此时，第五芯片裸片243可以通过引线向第四PCB241发送信号或从第四PCB241接收信号。第二封装件230还可以包括保护第五芯片裸片243的保护材料245。根据一些示例实施例，第二封装件230可以以层叠封装件实现。
保护材料237和保护材料245中的每个可以以EMC实现。可以通过毛细填充(CUF)工艺用底部填充材料来填充第三PCB233与第四芯片裸片235之间的空间。
图25是包括图24中示出的封装件组件的移动计算装置的框图。参照图24和图25，移动计算装置300可以包括底部封装件100、顶部封装件TPG、PMIC205、第四芯片裸片235(例如，应用处理器235)、第五芯片裸片243(例如，DRAM243)、无线芯片裸片250(例如，射频集成电路(RFIC)250)和显示器310。PMIC205可以将相应的电源电压供应到底部封装件100、顶部封装件TPG、第四芯片裸片235(例如，应用处理器235)、第五芯片裸片243(例如，DRAM243)、无线芯片裸片250(例如，RFIC250)和显示器310中的每个。
底部封装件100的结构和顶部封装件TPG的结构如参照图1至图24所描述的。第四芯片裸片235(例如，应用处理器235)可以控制对第五芯片裸片243(例如，DRAM243)的写入操作和读取操作。第四芯片裸片235(例如，应用处理器235)可以向显示器310发送将要显示在显示器310中的显示数据。
第四芯片裸片235(例如，应用处理器235)可以控制包括在底部封装件100中的第一芯片裸片130和/或第二芯片裸片140的操作。第四芯片裸片235(例如，应用处理器235)可以控制包括在顶部封装件TPG中的存储控制器189-2和/或第三芯片裸片173、177、181和185的操作。第四芯片裸片235(例如，应用处理器235)可以控制无线芯片裸片250(例如，RFIC250)的操作。
根据发明构思的一些示例实施例的层叠封装件可以仅在保护材料的各个侧面之中的相互面对的两个侧面周围设置堆叠连接球，其中，堆叠连接球用于堆叠底部封装件和顶部封装件，保护材料包括附着到底部封装件的印刷电路板的芯片裸片。根据发明构思的一些示例实施例的层叠封装件可以将对于包括在顶部封装件中的至少一个芯片裸片的操作所必需的所有焊盘仅连接到堆叠连接球之中的第一堆叠连接球，从而减小根据发明构思的一些示例实施例的层叠封装件的尺寸和高度。
虽然已经参照发明构思的一些示例实施例具体地示出并描述了发明构思的一些示例实施例，但是本领域的普通技术人员将理解的是，在不脱离如权利要求限定的发明构思的精神和范围的情况下，可以在某方面做出形式和细节上的各种改变。
应该理解的是，这里描述的示例实施例应该仅以描述性意义来考虑，而不是为了限制的目的。对示例实施例中的特征或方面的描述通常应该被认为可用于其它示例实施例中的其它类似特征或方面。

Claims (25)

1.一种层叠封装件，所述层叠封装件包括：
第一印刷电路板；
底部封装件，包括附着到第一印刷电路板的第一芯片裸片和第二芯片裸片；
顶部封装件，包括第二印刷电路板和附着到第二印刷电路板的第三芯片裸片，并且覆盖在底部封装件之上；以及
第一堆叠连接焊球和第二堆叠连接焊球，电连接在第一印刷电路板和第二印刷电路板之间，并且仅形成在底部封装件的侧面之中的相互面对的两个侧面周围。
2.根据权利要求1所述的层叠封装件，其中，第一芯片裸片包括调制解调器芯片裸片，
其中，第二芯片裸片包括动态随机存取存储器芯片裸片或伪静态随机存取存储器芯片裸片，
其中，底部封装件包括系统级封装。
3.根据权利要求1所述的层叠封装件，其中，第一芯片裸片通过第一凸点以倒装芯片结构附着到第一印刷电路板，
其中，第二芯片裸片通过第二凸点以倒装芯片结构附着到第一印刷电路板。
4.根据权利要求1所述的层叠封装件，其中，第一芯片裸片通过第一凸点以倒装芯片结构附着到第一印刷电路板，
其中，第二芯片裸片通过第二凸点以倒装芯片结构附着到第一印刷电路板，
其中，用毛细底部填充材料填充第一芯片裸片和第一印刷电路板之间的空的空间以及第二芯片裸片和第一印刷电路板之间的空的空间。
5.根据权利要求1所述的层叠封装件，其中，第一芯片裸片通过第一凸点以倒装芯片结构附着到第一印刷电路板，
其中，第二芯片裸片通过第二凸点以倒装芯片结构附着到第一印刷电路板，
其中，利用模塑底部填充材料包封第一芯片裸片和第一印刷电路板之间的空的空间、第二芯片裸片和第一印刷电路板之间的空的空间、第一芯片裸片以及第二芯片裸片。
6.根据权利要求1所述的层叠封装件，其中，第一芯片裸片通过凸点以倒装芯片结构附着到第一印刷电路板，
其中，第二芯片裸片通过引线键合附着到第一印刷电路板，
其中，利用模塑底部填充材料包封第一芯片裸片和第一印刷电路板之间的空的空间、第一芯片裸片和第二芯片裸片。
7.根据权利要求1所述的层叠封装件，其中，顶部封装件还包括附着到第二印刷电路板的存储控制器，
其中，存储控制器被构造成控制第三芯片裸片的操作，
其中，第三芯片裸片包括基于闪存的存储芯片裸片。
8.根据权利要求7所述的层叠封装件，其中，仅通过第一堆叠连接焊球来发送用于第三芯片裸片和存储控制器的操作的所有信号和所有电源电压。
9.根据权利要求8所述的层叠封装件，其中，每个第二堆叠连接焊球处于电气浮置状态。
10.根据权利要求7所述的层叠封装件，其中，通过第一堆叠连接焊球发送用于第三芯片裸片和存储控制器的操作的所有信号与用于第三芯片裸片和存储控制器中的至少一个的操作的第一电源电压的一部分，通过第二堆叠连接焊球发送用于第三芯片裸片和存储控制器中的至少一个的操作的第一电源电压的剩余部分。
11.根据权利要求10所述的层叠封装件，其中，通过附着到第一印刷电路板的底表面的各个焊球输入的第一电源电压的所述剩余部分通过第一印刷电路板发送到底部封装件和第二堆叠连接焊球。
12.根据权利要求1所述的层叠封装件，其中，第一芯片裸片和第二芯片裸片仅通过形成在第一印刷电路板中的信号线来相互发送信号或相互接收信号。
13.一种移动计算装置，所述移动计算装置包括：
系统板；
第一封装件，附着到系统板；
电源管理集成电路，附着到系统板并被配置成通过系统板将第一电源电压供应到第一封装件；
其中，第一封装件包括：
第一印刷电路板；
底部封装件，包括附着到第一印刷电路板的第一芯片裸片和第二芯片裸片；
顶部封装件，包括第二印刷电路板和附着到第二印刷电路板的第三芯片裸片，并且覆盖在底部封装件之上；以及
第一堆叠连接焊球和第二堆叠连接焊球，电连接在第一印刷电路板和第二印刷电路板之间，并且仅形成在底部封装件的侧面之中的相互面对的两个侧面周围。
14.根据权利要求13所述的移动计算装置，其中，第一芯片裸片包括调制解调器芯片裸片，
其中，第二芯片裸片包括动态随机存取存储器芯片裸片或伪静态随机存取存储器芯片裸片，
其中，底部封装件包括系统级封装。
15.根据权利要求13所述的移动计算装置，其中，顶部封装件还包括附着到第二印刷电路板的存储控制器，
其中，存储控制器被配置成控制第三芯片裸片的操作，
其中，第三芯片裸片包括基于闪存的存储芯片裸片。
16.根据权利要求15所述的移动计算装置，其中，仅通过第一堆叠连接焊球发送用于第三芯片裸片和存储控制器的操作的所有信号以及用于第三芯片裸片和存储控制器的操作的所有第一电源电压。
17.根据权利要求13所述的移动计算装置，其中，移动计算装置还包括附着到系统板的第二封装件并包括应用处理器芯片裸片，
其中，电源管理集成电路被配置成通过系统板将第二电源电压供应到应用处理器芯片裸片，
其中，系统板包括信号线，信号线被配置成发送在应用处理器芯片裸片和第一封装件之间发送或接收的信号，
其中，信号线通过第一印刷电路板连接到第一堆叠连接焊球之中的对应的连接焊球。
18.根据权利要求13所述的移动计算装置，其中，系统板包括接地线，
其中，第一电源电压包括操作电压和接地电压，
其中，来自第一堆叠连接焊球之中的与接地电压有关的连接焊球通过第一印刷电路板连接到接地线，
其中，通过第一印刷电路板将操作电压供应到第一堆叠连接焊球之中对应的连接焊球。
19.根据权利要求15所述的移动计算装置，其中，仅通过第一堆叠连接焊球来发送用于第三芯片裸片和存储控制器的操作的所有信号以及来自第一电源电压之中的用于第三芯片裸片和存储控制器中的至少一个的操作的第二电源电压，
其中，仅通过来自第二堆叠连接焊球之中的各个连接焊球来发送来自第一电源电压之中的用于第三芯片裸片和存储控制器中的至少一个的操作的第三电源电压，
其中，通过附着到第一印刷电路板的底表面的焊球输入的第三电源电压通过第一印刷电路板被发送到所述各个连接焊球和底部封装件。
20.根据权利要求19所述的移动计算装置，其中，移动计算装置还包括附着到系统板的第二封装件并且包括应用处理器芯片裸片，
其中，电源管理集成电路被配置成通过系统板将第四电源电压供应到应用处理器芯片裸片，
其中，系统板包括信号线，信号线发送在应用处理器芯片裸片和第一封装件之间发送或接收的信号，
其中，信号线通过第一印刷电路板连接到第一堆叠连接焊球之中的对应的连接焊球。
21.一种电子装置，所述电子装置包括：
第一印刷电路板；
第一芯片裸片，在第一印刷电路板上；
第二芯片裸片，在第一印刷电路板上；
第二印刷电路板，在第一芯片裸片和第二芯片裸片上；
至少一个第三芯片裸片，在第二印刷电路板上；以及
第一堆叠连接焊球和第二堆叠连接焊球，电连接在第一印刷电路板和第二印刷电路板之间；
其中，第一堆叠连接焊球在第一芯片裸片和第二芯片裸片的与第二堆叠连接焊球相对的侧面上。
22.根据权利要求21所述的电子装置，其中，第二芯片裸片在第一芯片裸片上。
23.根据权利要求21所述的电子装置，其中，第一芯片裸片包括调制解调器芯片裸片，
其中，第二芯片裸片包括动态随机存取存储器芯片裸片或伪静态随机存取存储器芯片裸片。
24.根据权利要求21所述的电子装置，其中，第一芯片裸片通过第一凸点以倒装芯片结构附着到第一印刷电路板，
其中，第二芯片裸片通过第二凸点以倒装芯片结构附着到第一印刷电路板。
25.根据权利要求21所述的电子装置，其中，第一芯片裸片通过第一凸点以倒装芯片结构附着到第一印刷电路板，
其中，第二芯片裸片通过第二凸点以倒装芯片结构附着到第一印刷电路板，
其中，用毛细底部填充材料填充第一芯片裸片和第一印刷电路板之间的空的空间以及第二芯片裸片和第一印刷电路板之间的空的空间。
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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108063095A (zh) * 2017-12-15 2018-05-22 路军 一种智能融合传感器芯片的封装方法
CN109390313A (zh) * 2017-08-04 2019-02-26 三星电机株式会社 半导体封装件的连接系统
CN109472099A (zh) * 2018-11-19 2019-03-15 郑州云海信息技术有限公司 一种服务器的印刷电路板及制作方法
CN109817610A (zh) * 2017-11-21 2019-05-28 环旭电子股份有限公司 半导体封装装置
CN111199934A (zh) * 2018-11-16 2020-05-26 瑞昱半导体股份有限公司 电路装置与电路设计及组装方法
CN111539180A (zh) * 2019-01-21 2020-08-14 三星电子株式会社 印刷电路板模拟的计算机实现方法、系统和存储介质
CN114258588A (zh) * 2019-08-28 2022-03-29 美光科技公司 包含线接合和直接芯片附接的堆叠裸片封装以及相关方法、装置和设备

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20190067839A (ko) 2016-10-04 2019-06-17 스카이워크스 솔루션즈, 인코포레이티드 오버몰드 구조를 갖는 양면 라디오-주파수 패키지
WO2018125163A1 (en) * 2016-12-29 2018-07-05 Intel Corporation Multi-point stacked die wirebonding for improved power delivery
US10447274B2 (en) * 2017-07-11 2019-10-15 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
KR101942736B1 (ko) * 2017-08-04 2019-04-17 삼성전기 주식회사 반도체 패키지 연결 시스템
US10332899B2 (en) * 2017-09-29 2019-06-25 Intel Corporation 3D package having edge-aligned die stack with direct inter-die wire connections
TWI750467B (zh) 2018-05-15 2021-12-21 南韓商三星電子股份有限公司 半導體封裝
TWI700798B (zh) 2018-07-12 2020-08-01 南韓商三星電子股份有限公司 半導體封裝
KR20200011820A (ko) * 2018-07-25 2020-02-04 삼성전자주식회사 반도체 패키지
US20210398906A1 (en) * 2020-06-23 2021-12-23 Intel Corporation Scalable and interoperable phyless die-to-die io solution
US11923331B2 (en) * 2021-02-25 2024-03-05 Taiwan Semiconductor Manufacturing Co., Ltd. Die attached leveling control by metal stopper bumps

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050248010A1 (en) * 2004-03-16 2005-11-10 Elpida Memory, Inc Semiconductor package and system module
CN1846311A (zh) * 2003-09-05 2006-10-11 新美亚通讯设备有限公司 可堆叠的电子组件
US20130175702A1 (en) * 2012-01-11 2013-07-11 Samsung Electronics Co., Ltd. Semiconductor package
CN104733448A (zh) * 2013-12-19 2015-06-24 爱思开海力士有限公司 封装体叠层模块

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6414391B1 (en) * 1998-06-30 2002-07-02 Micron Technology, Inc. Module assembly for stacked BGA packages with a common bus bar in the assembly
JP4512545B2 (ja) * 2005-10-27 2010-07-28 パナソニック株式会社 積層型半導体モジュール
KR101479509B1 (ko) * 2008-08-29 2015-01-08 삼성전자주식회사 반도체 패키지
KR20100071522A (ko) * 2008-12-19 2010-06-29 삼성전자주식회사 패키지 온 패키지 타입의 고용량 다기능 멀티 칩 패키지 구조
TWI499024B (zh) * 2009-01-07 2015-09-01 Advanced Semiconductor Eng 堆疊式多封裝構造裝置、半導體封裝構造及其製造方法
KR20110006482A (ko) 2009-07-14 2011-01-20 삼성전자주식회사 메모리 링크 아키텍쳐를 갖는 멀티 프로세서 시스템에 적합한 멀티 칩 패키지 구조
US8264091B2 (en) * 2009-09-21 2012-09-11 Stats Chippac Ltd. Integrated circuit packaging system with encapsulated via and method of manufacture thereof
KR101855294B1 (ko) * 2010-06-10 2018-05-08 삼성전자주식회사 반도체 패키지
KR20110139983A (ko) * 2010-06-24 2011-12-30 삼성전자주식회사 반도체 패키지
US9437512B2 (en) 2011-10-07 2016-09-06 Mediatek Inc. Integrated circuit package structure
KR101901324B1 (ko) 2011-10-25 2018-09-27 삼성전자주식회사 네 개의 채널들을 가진 반도체 패키지
KR101797079B1 (ko) 2011-12-30 2017-11-14 삼성전자 주식회사 Ｐｏｐ 구조의 반도체 패키지
KR101874803B1 (ko) 2012-01-20 2018-08-03 삼성전자주식회사 패키지 온 패키지 구조체
KR101923535B1 (ko) 2012-06-28 2018-12-03 삼성전자주식회사 패키지 온 패키지 장치 및 이의 제조 방법
KR101909202B1 (ko) 2012-10-08 2018-10-17 삼성전자 주식회사 패키지-온-패키지 타입의 패키지
KR102008014B1 (ko) 2012-10-15 2019-08-06 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9136159B2 (en) 2012-11-15 2015-09-15 Amkor Technology, Inc. Method and system for a semiconductor for device package with a die-to-packaging substrate first bond
KR102043369B1 (ko) 2012-11-21 2019-11-11 삼성전자주식회사 반도체 메모리 칩 및 이를 포함하는 적층형 반도체 패키지
KR102107147B1 (ko) 2013-02-01 2020-05-26 삼성전자주식회사 패키지 온 패키지 장치

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1846311A (zh) * 2003-09-05 2006-10-11 新美亚通讯设备有限公司 可堆叠的电子组件
US20050248010A1 (en) * 2004-03-16 2005-11-10 Elpida Memory, Inc Semiconductor package and system module
US20130175702A1 (en) * 2012-01-11 2013-07-11 Samsung Electronics Co., Ltd. Semiconductor package
CN104733448A (zh) * 2013-12-19 2015-06-24 爱思开海力士有限公司 封装体叠层模块

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109390313A (zh) * 2017-08-04 2019-02-26 三星电机株式会社 半导体封装件的连接系统
CN109817610A (zh) * 2017-11-21 2019-05-28 环旭电子股份有限公司 半导体封装装置
CN108063095A (zh) * 2017-12-15 2018-05-22 路军 一种智能融合传感器芯片的封装方法
CN111199934A (zh) * 2018-11-16 2020-05-26 瑞昱半导体股份有限公司 电路装置与电路设计及组装方法
CN111199934B (zh) * 2018-11-16 2022-07-19 瑞昱半导体股份有限公司 电路装置与电路设计及组装方法
CN109472099A (zh) * 2018-11-19 2019-03-15 郑州云海信息技术有限公司 一种服务器的印刷电路板及制作方法
CN111539180A (zh) * 2019-01-21 2020-08-14 三星电子株式会社 印刷电路板模拟的计算机实现方法、系统和存储介质
CN111539180B (zh) * 2019-01-21 2023-11-24 三星电子株式会社 印刷电路板模拟的计算机实现方法、系统和存储介质
CN114258588A (zh) * 2019-08-28 2022-03-29 美光科技公司 包含线接合和直接芯片附接的堆叠裸片封装以及相关方法、装置和设备
US11705432B2 (en) 2019-08-28 2023-07-18 Micron Technology, Inc. Stacked die package including a first die coupled to a substrate through direct chip attachment and a second die coupled to the substrate through wire bonding, and related methods and devices

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