CN105633035A - 封装基板及其半导体封装 - Google Patents
封装基板及其半导体封装 Download PDFInfo
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- CN105633035A CN105633035A CN201510777400.8A CN201510777400A CN105633035A CN 105633035 A CN105633035 A CN 105633035A CN 201510777400 A CN201510777400 A CN 201510777400A CN 105633035 A CN105633035 A CN 105633035A
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- packaging
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- interlayer connector
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- connection pad
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Abstract
本发明实施例公开了一种封装基板及其半导体封装。其中封装基板包括:核心层,具有第一面以及相对于该第一面的第二面,并且该核心层具有中央区域和围绕该中央区域的周边区域;接地接垫群组,设置在该中央区域内的该第二面上;第一电源接垫群组,设置在该中央区域内的该第二面上;第一块状介层插塞,嵌入在该核心层中,并且位于该中央区域内,其中该接地接垫群组共同电连接于该第一块状介层插塞;以及第二块状介层插塞,嵌入在该核心层中,并且位于该中央区域内,其中该第一电源接垫群组共同电连接于该第二块状介层插塞。本发明实施例的封装基板及其半导体封装,具有较佳的散热性,因此能够提高封装结构的效能。
Description
技术领域
本发明涉及半导体封装技术领域,尤其涉及一种具有块状介层插塞的封装基板及其半导体封装,该封装基板具有较佳的散热能力,能有效的对操作中的集成电路芯片或芯片封装进行散热。
背景技术
近年来,移动通讯市场持续推动先进半导体封装产业的发展。这主要是由于制造商尽可能的满足终端用户对手机功能、性能和小型化的需求所得的结果。
从最初的芯片尺寸封装(ChipScalePackaging,CSP)的采用,及紧随其后的对于多芯片封装和封装上封装(Package-on-Package,PoP)结构在制造上的需求,可窥见移动通讯市场的影响。这种趋势在智能手机方面最为显著,其中,越来越多的应用组件、基频及多媒体处理器采用倒装芯片封装,以满足尺寸、性能,以及在某些情况下,对成本的要求。
采用倒装芯片封装的封装上封装(PoP)结构虽可以有效地解决信号完整性(signalintegrity)和电源完整性(powerintegrity)。然而,较大的功耗所造成的散热问题已经成为本技术领域的一个主要挑战。正如本领域已知的,集成电路(IC)操作时,IC芯片会产生热,从而加热包含该IC芯片的整个电子封装构件。由于IC芯片的性能会随着其温度的增加而衰退,且高的热应力会降低电子封装构件的结构完整性,故必须使该热量散失。
通常,倒装芯片芯片尺寸封装(FlipChipCSP,FCCSP)利用金属盖进行散热,芯片产生的热经由热传导接口从芯片传递到金属盖,再将热通过对流传递到周围环境。然而,这样的FCCSP结构需要额外的金属盖,因此较为昂贵。
发明内容
有鉴于此,本发明实施例提供了一种封装基板及其半导体封装,能够突破先进半导体封装的散热瓶颈,藉此提高效能。
本发明提供了一种封装基板,包含有:
核心层,具有第一面以及相对于该第一面的第二面,并且该核心层具有中央区域和围绕该中央区域的周边区域;
接地接垫群组,设置在该中央区域内的该第二面上;
第一电源接垫群组,设置在该中央区域内的该第二面上;
第一块状介层插塞,嵌入在该核心层中,并且位于该中央区域内,其中该接地接垫群组共同电连接于该第一块状介层插塞;以及
第二块状介层插塞,嵌入在该核心层中,并且位于该中央区域内,其中该第一电源接垫群组共同电连接于该第二块状介层插塞。
其中,该第一块状介层插塞及该第二块状介层插塞由整块金属所构成,且该整块金属贯穿该核心层的整个厚度。
其中,该接地接垫群组仅通过该第一块状介层插塞与该第一面相连通。
其中,该第一电源接垫群组仅通过该第二块状介层插塞与该第一面相连通。
其中,另包含:
第二电源接垫群组,设置在该中央区域内的该第二面上;以及
第三块状介层插塞,嵌入在该核心层中,并且位于该中央区域内,其中该第二电源接垫群组共同电连接于该第三块状介层插塞。
其中,该第一电源接垫群组用于输送第一电源域电源信号,该第二电源接垫群组用于输送第二电源域电源信号,该第一电源域电源信号不同于该第二电源域电源信号。
其中,该第一块状介层插塞及该第二块状介层插塞包含铜。
其中,该第一块状介层插塞环绕该第二块状介层插塞。
本发明还提供了一种半导体封装,该半导体封装为球栅阵列式封装,包含有:
如上所述的封装基板;以及
芯片,组装到该封装基板的该第一面上。
其中,该芯片以其主动面朝下的方式组装到该封装基板的该第一面上,和/或,还包含:芯片封装,组装到该封装基板的该第一面上。
本发明实施例的有益效果是:
本发明实施例的封装基板及其半导体封装,利用块状介层插塞进行散热,因此具有较佳的散热性,从而能够突破先进半导体封装的散热瓶颈,并藉此提高封装结构的效能。
附图说明
图1为根据本发明实施例所绘示的剖面示意图,示例为封装基板。
图2为从封装基板的PCB(印刷电路板)侧俯视导电接垫及块状介层插塞的布局示意图。
图3为根据本发明另一实施例所绘示的倒装芯片芯片尺寸封装(FCCSP)的剖面示意图。
图4为依据本发明另一实施例所绘示的封装上封装(PoP)的剖面示意图。
具体实施方式
为了使本发明所解决的技术问题、技术方案及有益效果更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。
以下的说明中,不同实施例中可能会有重复的附图标记和/或文字。这样的重复只是为了简化并能清楚地说明本发明,并非为了指出各种实施例和/或所讨论的各种配置之间的关系。
另外,以下的说明中,若牵涉到第一结构特征位于第二结构特征上方或上面,包括在不同实施例中,所指的是,该第一结构特征及该第二结构特征可以是彼此直接接触,或者不直接接触。
本文中所用的术语,其目的仅在于描述具体实施例,并非意在限制本发明。如本文所用,单数形式“一”、“一个”和“该”也可包括多个形式,除非上下文另外明确指出。应进一步理解,开放式术语“包括”和/或“包含”,在本说明书中使用时,特指所陈述的结构特征、整数、步骤、操作、组件和/或部件的存在,但亦不排除其它额外结构特征、整数、步骤、操作、组件、部件,和/或其组合的存在。
请参考图1,图1为根据本发明实施例所绘示的剖面示意图,示例为封装基板100。虽然在本实施例中示例的是2层布线的封装基板,但应该理解,在其它实施例中,封装基板也可以具有更多层金属布线层,例如四层或六层,但不限于此。
如图1所示,封装基板100包含:核心层200,具有第一面200a以及相对于第一面200a的第二面200b。在第一面200a上,设置有防焊层520和多个导电接垫310、320、330、340。这些导电接垫310、320、330、340提供了与集成电路芯片或裸芯片(在该图中未示出)的电连接路径。因此,第一面200a可以称为封装基板100的“芯片侧”或“祼芯片侧”。应当理解,这些导电接垫310、320、330、340皆为形成在第一面200a上阻焊层520内的线路图案层的一部分。
根据本发明实施例,导电接垫310、320、330设置在中央区域101内,导电接垫340设置在环绕中央区域101的周边区域102内。根据本发明实施例,导电接垫310可以是接地接垫,被配置用来传送接地信号(G)。根据本发明实施例,导电接垫320可以是电源接垫,被配置用来传送第一电源域(P1)的电源信号。根据本发明实施例,导电接垫330可以是电源接垫,被配置用来传送第二电源域(P2)的电源信号。根据本发明实施例,导电接垫340可以是信号接垫,被配置用来传送输入/输出(I/O)信号。
在封装基板100的第二面200b上,同样地,设置有防焊层510和多个导电接垫210、220、230、240。这些导电接垫210、220、230、240提供了封装基板100与印刷电路板(PCB)或主板(在该图中未示出)的电连接路径。因此,第二面200b也可以称为封装基板100的“PCB侧”。应当理解的是,导电接垫210、220、230、240皆为形成在第二面200b上阻焊层510内的线路图案层的一部分。
根据本发明实施例,导电接垫210、220、230设置在中央区域101内,导电接垫240设置在环绕中央区域101的周边区域102内。根据本发明实施例,导电接垫210可以是接地接垫,被配置用来传送所述接地信号(G)。根据本发明实施例,导电接垫220可以是电源接垫,被配置用来传送所述第一电源域(P1)的电源信号,例如VCC。根据本发明实施例,导电接垫230可以是电源接垫,被配置用来传送所述第二电源域(P2)的电源信号,例如VDD。根据本发明实施例,导电接垫240可以是信号接垫,被配置用来传送输入/输出(I/O)信号。
根据本发明实施例,核心层200可包括预浸材料(prepreg)或玻璃纤维环氧树脂,但并不限于此。导电接垫310~340和210~240可以包括导电材料,例如铜,并在一些情况下,还可包含表面处理层(surfacefinishlayer)或保护层。防焊层510、520可以包括任何合适的阻焊树脂。
在周边区域102内,相应的导电接垫240、340可以是通过导孔(conductivevia)或电镀通孔(platedthroughhole,PTH)440电连接在一起。所述导孔或电镀通孔440贯穿核心层200的整个厚度。所述导孔或电镀通孔440可以利用激光钻孔、机械钻孔或微影工艺等方式形成。
根据本发明实施例,所述多个导电接垫210在第二面200b上被配置成群组,所述多个导电接垫310在第一面200a上被配置成群组。导电接垫210这群组与导电接垫310这群组可以共同经由嵌入在核心层200内的单一块状介层插塞110电连接在一起。所述块状介层插塞110贯穿核心层200的整个厚度。
根据本发明实施例,所述多个导电接垫220被配置成群组,所述多个导电接垫320被配置成群组。导电接垫220这群组与导电接垫320这群组可以共同经由嵌入在核心层200内的单一块状介层插塞120电连接在一起。所述块状介层插塞120贯穿核心层200的整个厚度。
根据本发明实施例,所述多个导电接垫230被配置成群组,所述多个导电垫330被配置成群组。导电接垫230这群组与导电接垫330这群组可以共同经由嵌入在核心层200内的单一块状介层插塞130电连接在一起。所述块状介层插塞130贯穿核心层200的整个厚度。
根据本发明实施例,各个所述块状介层插塞110、120、130可以由整块(或一体成型的)金属,例如铜,或其他合适的散热材料所构成。根据本发明实施例,例如,各个所述块状介层插塞110、120、130的宽度可以是所述导孔或电镀通孔440的直径的100倍。因此,散热性能及电源完整性可以同时显著获得改善。
图2示例了从封装基板的PCB侧俯视导电接垫及块状介层插塞的布局示意图。其中,相同的组件、区域或层仍沿用相同符号来表示。应该理解的是,图2中所示例的从封装基板的PCB侧俯视导电接垫及块状介层插塞的布局或布线图案仅为例示说明。在其它实施例中,也可以采用不同布局及布线图案。
如图2所示,在中央区域101内,所述块状介层插塞110、120、130以虚线表示。根据本发明实施例,所述块状介层插塞110可以围绕所述块状介层插塞120、130。在图2中,一组用于输送接地信号的导电接垫210共同电连接到单一块状介层插塞110,一组用于在第一电源域(P1)输送电源信号的导电接垫220共同电连接到单一块状介层插塞120,以及一组用于在第二电源域(P2)传送电源信号的导电接垫230共同电连接到单一块状介层插塞130。
图3为依据本发明另一实施例所绘示的倒装芯片芯片尺寸封装(FCCSP)的剖面示意图。如图3所示,倒装芯片芯片尺寸封装1包含如上所述的封装基板100,以及翻面的半导体祼芯片(或芯片)10,其主动面朝下组装到封装基板100的芯片侧。例如,封装基板100可以是2层基板,仅具有两层金属布线层,分别设置在封装基板100的两个相对侧。但是应当理解的是,在其它实施例中,半导体祼芯片10也可用晶圆级封装来取代,例如,散出型晶圆级封装(fan-outwaferlevelpackage),但并不限于此。
根据本发明实施例,半导体祼芯片10还具有多个接合焊垫11、12、13、14,布置在其主动面上,其中该主动面直接面向封装基板100的芯片侧。在所述半导体祼芯片10与所述封装基板100之间设置有多个导电组件20分别将接合焊垫11、12、13、14电连接至导电接垫310、320、330、340。根据本发明实施例,导电组件20可以包括铜柱或焊锡凸块,但不限于此。
在半导体祼芯片10与封装基板100之间,可以设置底胶(underfill)30以包覆导电组件20。已知,底胶30可控制焊点的应力,该应力是由半导体祼芯片10与封装基板100之间的热膨胀系数差异所引起。底胶30经过固化后,可以吸收应力,降低对焊锡凸块的应变,大大增加了封装成品的寿命。应理解的是,在某些情况下,底胶30可以省略,或以其他材料代替,例如,成型模料(moldingcompound)。此外,可提供成型模盖40包覆住半导体祼芯片10以及封装基板100的部分表面。
如上所述,根据本发明实施例,中央区域101内的接地接垫被配置在同一群组,并经由单一块状介层插塞110电连接在一起,中央区域101内的第一电源域(P1)的电源接垫被配置在同一群组,并经由单一块状介层插塞120电连接在一起,以及中央区域101内的第二功率域(P2)的电源接垫被配置在同一群组,并经由单一块状介层插塞130电连接在一起。在半导体祼芯片10的操作过程中产生的热,能够有效地通过所述块状介层插塞110、120、130进行散热。另外,在第二面200b上,设置有多个锡球50,提供后续的连接使用。经由块状介层插塞110、120、130导出的热,可以再经由锡球50传导至外部,例如,电路板。
图4为依据本发明另一实施例所绘示的封装上封装(PoP)的剖面示意图。如图4所示,封装上封装2包含如上所述的封装基板100,以及翻面的半导体祼芯片(或芯片)10,其主动面朝下组装到封装基板100的芯片侧。例如,封装基板100可以是2层基板,仅具有两层金属布线层,分别设置在封装基板100的两个相对侧。但是应当理解的是,在其它实施例中,半导体祼芯片10也可用晶圆级封装来取代,例如,散出型晶圆级封装,但并不限于此。
同样的,在所述半导体祼芯片10与所述封装基板100之间设置有多个导电组件20分别电连接接合焊垫11、12、13、14及导电接垫310、320、330、340。根据本发明实施例,导电组件20可以包括铜柱或焊锡凸块,但不限于此。在半导体祼芯片10与封装基板100之间,可以设置底胶30,包覆导电组件20。应理解的是,在某些情况下,底胶30可以省略,或以其他材料代替,例如,成型模料。
如上所述,根据本发明实施例,中央区域101内的接地接垫被配置在同一群组,并经由单一块状介层插塞110电连接在一起,中央区域101内的第一电源域(P1)的电源接垫被配置在同一群组,并经由单一块状介层插塞120电连接在一起,以及中央区域101内的第二功率域(P2)的电源接垫被配置在同一群组,并经由单一块状介层插塞130电连接在一起。
在封装基板100的芯片侧上组装有芯片封装60,并通过导电组件80,例如,焊锡凸块或铜柱,电连接到封装基板100上的相应接垫350。例如,芯片封装60可以是动态随机存取存储器(DynamicRandomAccessMemory,DRAM)芯片封装,但并不限于此。另外,在第二面200b上,设置有多个锡球50,提供后续的连接使用。经由块状介层插塞110、120、130导出的热,可以再经由锡球50传导至外部,例如,电路板。
在本发明的前述范例中,主要以二层结构的封装基板为例进行说明,但是可以理解的是,本发明的封装基板也可以为多层结构,例如三层或四层等。
以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明的保护范围之内。
Claims (10)
1.一种封装基板,其特征在于,包含有:
核心层,具有第一面以及相对于该第一面的第二面,并且该核心层具有中央区域和围绕该中央区域的周边区域;
接地接垫群组,设置在该中央区域内的该第二面上;
第一电源接垫群组,设置在该中央区域内的该第二面上;
第一块状介层插塞,嵌入在该核心层中,并且位于该中央区域内,其中该接地接垫群组共同电连接于该第一块状介层插塞;以及
第二块状介层插塞,嵌入在该核心层中,并且位于该中央区域内,其中该第一电源接垫群组共同电连接于该第二块状介层插塞。
2.如权利要求1所述的封装基板,其特征在于,该第一块状介层插塞及该第二块状介层插塞由整块金属所构成,且该整块金属贯穿该核心层的整个厚度。
3.如权利要求1所述的封装基板,其特征在于,该接地接垫群组仅通过该第一块状介层插塞与该第一面相连通。
4.如权利要求1所述的封装基板,其特征在于,该第一电源接垫群组仅通过该第二块状介层插塞与该第一面相连通。
5.如权利要求1所述的封装基板,其特征在于,另包含:
第二电源接垫群组,设置在该中央区域内的该第二面上;以及
第三块状介层插塞,嵌入在该核心层中,并且位于该中央区域内,其中该第二电源接垫群组共同电连接于该第三块状介层插塞。
6.如权利要求5所述的封装基板,其特征在于,该第一电源接垫群组用于输送第一电源域电源信号,该第二电源接垫群组用于输送第二电源域电源信号,该第一电源域电源信号不同于该第二电源域电源信号。
7.如权利要求1所述的封装基板,其特征在于,该第一块状介层插塞及该第二块状介层插塞包含铜。
8.如权利要求1所述的封装基板,其特征在于,该第一块状介层插塞环绕该第二块状介层插塞。
9.一种半导体封装,该半导体封装为球栅阵列式封装,其特征在于,包含有:
如权利要求1~8中任一项所述的封装基板;以及
芯片,组装到该封装基板的该第一面上。
10.如权利要求9所述的半导体封装,其特征在于,该芯片以其主动面朝下的方式组装到该封装基板的该第一面上,和/或,还包含:芯片封装,组装到该封装基板的该第一面上。
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US10580715B2 (en) * | 2018-06-14 | 2020-03-03 | Texas Instruments Incorporated | Stress buffer layer in embedded package |
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