TW201620054A - 具塊狀介層插塞的封裝基板及其半導體封裝 - Google Patents

具塊狀介層插塞的封裝基板及其半導體封裝 Download PDF

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TW201620054A
TW201620054A TW104138235A TW104138235A TW201620054A TW 201620054 A TW201620054 A TW 201620054A TW 104138235 A TW104138235 A TW 104138235A TW 104138235 A TW104138235 A TW 104138235A TW 201620054 A TW201620054 A TW 201620054A
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package substrate
package
bulk layer
power
plug
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TW104138235A
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TWI593032B (zh
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許文松
陳泰宇
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聯發科技股份有限公司
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Abstract

一種封裝基板，包含有一核心層，具有第一面以及相對於該第一面的一第二面；一中央區域，位於該第二面；一週邊區域，環繞該中央區域；一接地接墊群組，設置在該第二面的該中央區域內；一第一電源接墊群組，設置在該第二面的該中央區域內；一第一塊狀介層插塞，嵌入在該核心層中，位於該中央區域內，其中該接地接墊群組係共同電連接於該第一塊狀介層插塞；以及一第二塊狀介層插塞，嵌入在該核心層中，位於該中央區域內，其中該第一電源接墊群組係共同電連接於該第二塊狀介層插塞。

Description

具塊狀介層插塞的封裝基板及其半導體封裝
本發明係有關半導體封裝技術領域，特別是有關於一種封裝基板，具有較佳的散熱能力，能有效的對操作中的積體電路晶片或晶片封裝進行散熱。
近年來，行動通訊市場持續推動先進半導體封裝產業的發展。這主要是由於製造商盡可能的滿足終端用戶的對手機功能、性能和小型化的需求所得結果。
從最初的晶片尺寸封裝（Chip Scale Packaging；CSP）的採用，及緊隨其後對於多晶片封裝和封裝上封裝（Package-on-Package；PoP）結構在製造上的需求，可窺見行動通訊市場的影響。這種趨勢在智慧手機方面最為顯著，其中，越來越多的應用元件、基頻及多媒體處理器採用覆晶封裝，以滿足尺寸、性能，以及，在某些情況下，對成本的要求。
採用覆晶封裝的封裝上封裝（PoP）結構雖可以有效地解決訊號完整性（signal integrity）和電源完整性（power integrity）。然而，較大的功耗所造成的散熱問題已經成為本技術領域一個主要挑戰。正如本領域已知的，積體電路（IC）操作時，IC晶片會產生熱，從而加熱包含該IC晶片的整個電子封裝構件。由於IC晶片的性能會隨著其溫度的增加而衰退，且高的熱應力會降低電子封裝構件的結構完整性，故必須使該熱量散失。
通常，覆晶晶片尺寸封裝（Flip Chip CSP；FCCSP）利用一金屬蓋進行散熱，晶片產生的熱經由熱傳導介面從晶片傳遞到金屬蓋，再將熱透過對流傳遞到周圍環境。然而，這樣的FCCSP結構需要額外的金屬蓋，因此較為昂貴。
本發明的主要目的在提供一種改良的封裝基板及其半導體封裝，能夠突破先進半導體封裝的散熱瓶頸，藉此提高效能。
本發明的另一個目的是提供一種改進的封裝基板及其半導體封裝，能夠突破先進半導體封裝的散熱瓶頸，並且無需採用較昂貴的散熱片或金屬蓋。
為達成上述目的，本發明實施例提供一種封裝基板，包含有一核心層，具有第一面以及相對於該第一面的一第二面；該核心層具有一中央區域以及環繞該中央區域之一週邊區域；一接地接墊群組，設置在該第二面的該中央區域內；一第一電源接墊群組，設置在該第二面的該中央區域內；一第一塊狀介層插塞，嵌入在該核心層中，位於該中央區域內，其中該接地接墊群組係共同電連接於該第一塊狀介層插塞；以及一第二塊狀介層插塞，嵌入在該核心層中，位於該中央區域內，其中該第一電源接墊群組係共同電連接於該第二塊狀介層插塞。
本發明實施例提供一種半導體封裝，該半導體封裝為球柵陣列式封裝，包含有：所述的封裝基板；以及一晶片，組裝到該封裝基板的該第一面上。
上述的封裝基板及其半導體封裝，利用塊狀介層插塞進行散熱，因此能夠突破先進半導體封裝的散熱瓶頸，藉此提高效能。
無庸置疑的，該領域的技術人士讀完接下來本發明較佳實施例的詳細描述與圖式後，均可了解本發明的目的。
接下來的詳細敘述請參照相關圖式所示內容，用來說明可依據本發明具體實行的實施例。這些實施例提供足夠的細節，可使此領域中的技術人員充分了解並具體實行本發明。在不悖離本發明的範圍內，可做結構上的修改，並應用在其他實施例上。
此外，以下的說明中，不同實例中可能會有重複附圖標記和/或文字。這樣的重複只是為了簡化並能清楚說明本發明，並非為了指出各種實施例和/或所討論的各種配置之間的關係。
另外，以下的說明中，若牽涉到一第一結構特徵位於一第二結構特徵上方或上面，包括在不同實施例中，所指的是，該第一結構特徵及該第二結構特徵可以是彼此直接接觸，或者不直接接觸。
本文中所用的術語，其目的僅於描述具體實施例，並非意在限制本發明。如本文所用，單數形式“一”、“一個”和“該”也可包括複數形式，除非上下文另外明確指出。應進一步理解，開放式術語“包括”和/或“包含”，在本說明書中使用時，特定所陳述的結構特徵、整數、步驟、操作、元件和/或部件的存在，但亦不排除其它額外結構特徵、整數、步驟、操作、元件、部件，和/或其組合的存在。
請參考第1圖。第1圖為根據本發明一實施例所繪示的剖面示意圖，例示一封裝基板100。雖然在本實施例中例示的是2層佈線的封裝基板，但應該理解，在其它實施例中，封裝基板也可以具有更多層金屬佈線層，例如四層或六層，但不限於此。
如第1圖所示，封裝基板100包含一核心層200，具有一第一面200a以及相對於第一面200a的一第二面200b。在第一面200a上，設置有防焊層520和複數個導電接墊310、320、330、340。這些導電接墊310、320、330、340提供了與積體電路晶片或裸晶（在該圖中未示出）的電連接路徑。因此，第一面200a可以稱為封裝基板100的“晶片側”或 “裸晶側”。應當理解，這些導電接墊310、320、330、340皆為形成在第一面200a上阻焊層520內的一線路圖案層的一部分。
根據本發明實施例，導電接墊310、320、330設置在一中央區域101內，導電接墊340設置在環繞中央區域101的一週邊區域102內。根據本發明實施例，導電接墊310可以是接地接墊，被配置用來傳送一接地訊號（G）。根據本發明實施例，導電接墊320可以是電源接墊，被配置用來傳送一第一電源域（P1）的電源訊號。根據本發明實施例，導電接墊330可以是電源接墊，被配置用來傳送一第二電源域（P2）的電源訊號。根據本發明實施例，導電接墊340可以是訊號接墊，被配置用來傳送輸入/輸出（I/O）訊號。
在封裝基板100的第二面200b上，同樣地，設置有防焊層510和複數個導電接墊210、220、230、240。這些導電接墊210、220、230、240提供了封裝基板100與一印刷電路板（PCB）或主機板（在該圖中未示出）的電連接路徑。因此，第二面200b也可以稱為封裝基板100的一“PCB側”。應當理解的是，導電接墊210、220、230、240皆為形成在第二面200b上阻焊層510內的一線路圖案層的一部分。
根據本發明實施例，導電接墊210、220、230設置在中央區域101內，導電接墊240設置在環繞中央區域101的週邊區域102內。根據本發明實施例，導電接墊210可以是接地接墊，被配置用來傳送所述接地訊號（G）。根據本發明實施例，導電接墊220可以是電源接墊，被配置用來傳送所述第一電源域（P1）的電源訊號，例如VCC 。根據本發明實施例，導電接墊230可以是電源接墊，被配置用來傳送所述第二電源域（P2）的電源訊號，例如VDD 。根據本發明實施例，導電接墊240可以是訊號接墊，被配置用來傳送輸入/輸出（I/O）訊號。
根據本發明實施例，核心層200可包括預浸材料（prepreg）或玻璃纖維環氧樹脂，但並不限於此。導電接墊310〜340和210〜240可以包括導電材料，例如銅，並在一些情況下，還可包含一表面處理層（surface finish layer）或一保護層。防焊層510、520可以包括任何合適的阻焊樹脂。
在所述週邊區域102內，相應的導電接墊240、340可以是透過一導孔（conductive via）或電鍍通孔（plated through hole，PTH）440電連接在一起。所述導孔或電鍍通孔440貫穿核心層200的整個厚度。所述導孔或電鍍通孔440可以利用雷射鑽孔、機械鑽孔或微影製程等方式形成。
根據本發明實施例，所述複數個導電接墊210在第二面200b上被配置成一群組，所述複數個導電接墊310在第一面200a上被配置成一群組。導電接墊210這群組與導電接墊310這群組可以共同經由一嵌入在核心層200內的單一塊狀介層插塞110電連接在一起。所述塊狀介層插塞110貫穿核心層200的整個厚度。
根據本發明實施例，所述複數個導電接墊220被配置成一群組，所述複數個導電接墊320被配置成一群組。導電接墊220這群組與導電接墊320這群組可以共同經由一嵌入在核心層200內的單一塊狀介層插塞120電連接在一起。所述塊狀介層插塞120貫穿核心層200的整個厚度。
根據本發明實施例，所述複數個導電接墊230被配置成一群組，所述複數個導電墊330被配置成一群組。導電接墊230這群組與導電接墊330這群組可以共同經由一嵌入在核心層200內的單一塊狀介層插塞130電連接在一起。所述塊狀介層插塞130貫穿核心層200的整個厚度。
根據本發明實施例，各個所述塊狀介層插塞110、120、130可以由整塊（或一體成型的）金屬，例如銅，或其他合適的散熱材料所構成。根據本發明實施例，例如，各個所述塊狀介層插塞110、120、130的寬度可以是所述導孔或電鍍通孔440的直徑的100倍。因此，散熱性能及電源完整性可以同時顯著獲得改善。
第2圖例示從封裝基板的PCB側俯視導電接墊及塊狀介層插塞的佈局示意圖，其中，相同的元件、區域或層仍沿用相同符號來表示。應該理解的是，第2圖中所例示的從封裝基板的PCB側俯視導電接墊及塊狀介層插塞的佈局或佈線圖案僅為例示說明。在其它實施例中，也可以採用不同佈局及佈線圖案。
如第2圖所示，在中央區域101內，所述塊狀介層插塞110、120、130以虛線表示。根據本發明實施例，所述塊狀介層插塞110可以圍繞所述塊狀介層插塞120、130。在第2圖中，一組用於輸送接地訊號的導電接墊210共同電連接到一單一塊狀介層插塞110，一組用於在第一電源域（P1）輸送電源訊號的導電接墊220共同電連接到一單一塊狀介層插塞120，以及一組用於在第二電源域（P2）傳送電源訊號的導電接墊230共同電連接到一單一塊狀介層插塞130。
第3圖為依據本發明另一實施例所繪示的覆晶晶片尺寸封裝（FCCSP）的剖面示意圖。如第3圖所示，覆晶晶片尺寸封裝1包含一如上所述的封裝基板100，以及一翻面的半導體裸晶（或晶片）10，其主動面朝下組裝到封裝基板100的晶片側。例如，封裝基板100可以是2層基板，僅具有兩層金屬佈線層，分別設置在封裝基板100的兩個相對側。但是應當理解的是，在其它實施例中，半導體裸晶10也可用晶圓級封裝來取代，例如，散出型晶圓級封裝（fan-out wafer level package），但並不限於此。
根據本發明實施例，半導體裸晶10還具有複數個接合焊墊11、12、13、14，佈置在其主動面上，其中該主動面直接面向封裝基板100的晶片側。在所述半導體裸晶10與所述封裝基板100之間設置有複數個導電元件20分別將接合焊墊11、12、13、14電連接至導電接墊310、320、330、340。根據本發明實施例，導電元件20可以包括銅柱或焊錫凸塊，但不限於此。
在半導體裸晶10與封裝基板100之間，可以設置一底膠（underfill）30以包覆導電元件20。已知，底膠30可控制焊點的應力，該應力係由半導體裸晶10與封裝基板100之間的熱膨脹係數差異所引起。底膠30經過固化後，可以吸收應力，降低對焊錫凸塊的應變，大大增加了封裝成品的壽命。應理解的是，在某些情況下，底膠30可以省略，或以其他材料代替，例如，成型模料（molding compound）。此外，可提供一成型模蓋40包覆住半導體裸晶10以及封裝基板100的部分表面。
如上所述，根據本發明實施例，中央區域101內的接地接墊被配置在同一群組，並經由一單一塊狀介層插塞110電連接在一起，中央區域101內的第一電源域（P1）的電源接墊被配置在同一群組，並經由一單一塊狀介層插塞120電連接在一起，以及中央區域101內的第二功率域（P2）的電源接墊被配置在同一群組，並經由一單一塊狀介層插塞130電連接在一起。在半導體裸晶10的操作過程中產生的熱，能夠有效地通過所述塊狀介層插塞110、120、130進行散熱。另外，在第二面200b上，設置有複數個錫球50，提供後續的連結使用。經由塊狀介層插塞110、120、130導出的熱，可以再經由錫球50傳導至外部，例如，電路板。
第4圖為依據本發明另一實施例所繪示的封裝上封裝（PoP）的剖面示意圖。如第4圖所示，封裝上封裝2包含一如上所述的封裝基板100，以及一翻面的半導體裸晶（或晶片）10，其主動面朝下組裝到封裝基板100的晶片側。例如，封裝基板100可以是2層基板，僅具有兩層金屬佈線層，分別設置在封裝基板100的兩個相對側。但是應當理解的是，在其它實施例中，半導體裸晶10也可用晶圓級封裝來取代，例如，散出型晶圓級封裝，但並不限於此。
同樣的，在所述半導體裸晶10與所述封裝基板100之間設置有複數個導電元件20分別電連接接合焊墊11、12、13、14及導電接墊310、320、330、340。根據本發明實施例，導電元件20可以包括銅柱或焊錫凸塊，但不限於此。在半導體裸晶10與封裝基板100之間，可以設置一底膠30，包覆導電元件20。應理解的是，在某些情況下，底膠30可以省略，或以其他材料代替，例如，成型模料。
如上所述，根據本發明實施例，中央區域101內的接地接墊被配置在同一群組，並經由一單一塊狀介層插塞110電連接在一起，中央區域101內的第一電源域（P1）的電源接墊被配置在同一群組，並經由一單一塊狀介層插塞120電連接在一起，以及中央區域101內的第二功率域（P2）的電源接墊被配置在同一群組，並經由一單一塊狀介層插塞130電連接在一起。
在封裝基板100的晶片側上組裝有一晶片封裝60，並通過導電元件80，例如，焊錫凸塊或銅柱，電連接到封裝基板100上的相應接墊350。例如，晶片封裝60可以是動態隨機存取記憶體（Dynamic Random Access Memory； DRAM）晶片封裝，但並不限於此。另外，在第二面200b上，設置有複數個錫球50，提供後續的連結使用。經由塊狀介層插塞110、120、130導出的熱，可以再經由錫球50傳導至外部，例如，電路板。
在本發明的前述範例中，主要以二層結構的封裝基板為例進行說明，但是可以理解的是，本發明的封裝基板也可以為多層結構，例如三層或四層等。   以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1‧‧‧覆晶晶片尺寸封裝
2‧‧‧封裝上封裝
10‧‧‧半導體裸晶
11、12、13、14‧‧‧接合焊墊
20‧‧‧導電元件
30‧‧‧底膠
40‧‧‧成型模蓋
50‧‧‧錫球
60‧‧‧晶片封裝
80‧‧‧導電元件
100‧‧‧封裝基板
101‧‧‧中央區域
102‧‧‧週邊區域
110、120、130‧‧‧塊狀介層插塞
200‧‧‧核心層
200a‧‧‧第一面
200b‧‧‧第二面
210、220、230、240‧‧‧導電接墊
310、320、330、340‧‧‧導電接墊
350‧‧‧接墊
440‧‧‧導孔或電鍍通孔
510、520‧‧‧防焊層
G‧‧‧接地訊號
P1‧‧‧第一電源域
P2‧‧‧第二電源域
所附圖式提供對於此實施例更深入的了解，並納入此說明書成為其中一部分。這些圖式與描述，用來說明一些實施例的原理。   第1圖為根據本發明一實施例所繪示的剖面示意圖，例示一封裝基板。   第2圖例示從封裝基板的PCB側俯視導電接墊及塊狀介層插塞的佈局示意圖。   第3圖為依據本發明另一實施例所繪示的覆晶晶片尺寸封裝（FCCSP）的剖面示意圖。   第4圖為依據本發明另一實施例所繪示的封裝上封裝（PoP）的剖面示意圖。
100‧‧‧封裝基板
101‧‧‧中央區域
102‧‧‧週邊區域
110、120、130‧‧‧塊狀介層插塞
200‧‧‧核心層
200a‧‧‧第一面
200b‧‧‧第二面
210、220、230、240‧‧‧導電接墊
310、320、330、340‧‧‧導電接墊
440‧‧‧導孔或電鍍通孔
510、520‧‧‧防焊層
G‧‧‧接地訊號
P1‧‧‧第一電源域
P2‧‧‧第二電源域

Claims (10)

  1. 一種封裝基板，包含有：        一核心層，具有一第一面以及相對於該第一面的一第二面，並且該核心層具有一中央區域和圍繞該中央區域的一周邊區域；        一接地接墊群組，設置在該中央區域內的該第二面上；        一第一電源接墊群組，設置在該中央區域內的該第二面上；        一第一塊狀介層插塞，嵌入在該核心層中，並且位於該中央區域內，其中該接地接墊群組係共同電連接於該第一塊狀介層插塞；以及        一第二塊狀介層插塞，嵌入在該核心層中，並且位於該中央區域內，其中該第一電源接墊群組係共同電連接於該第二塊狀介層插塞。
  2. 如申請專利範圍第1項所述的封裝基板，其中該第一塊狀介層插塞及該第二塊狀介層插塞係由一整塊金屬所構成，且該整塊金屬貫穿該核心層的整個厚度。
  3. 如申請專利範圍第1項所述的封裝基板，其中該接地接墊群組僅透過該第一塊狀介層插塞與該第一面相連通。
  4. 如申請專利範圍第1項所述的封裝基板，其中該第一電源接墊群組僅透過該第二塊狀介層插塞與該第一面相連通。
  5. 如申請專利範圍第1項所述的封裝基板，其中另包含： 一第二電源接墊群組，設置在該中央區域內的該第二面上；以及 一第三塊狀介層插塞，嵌入在該核心層中，並且位於該中央區域內，其中該第二電源接墊群組係共同電連接於該第三塊狀介層插塞。
  6. 如申請專利範圍第5項所述的封裝基板，其中該第一電源接墊群組係用於輸送一第一電源域電源訊號，該第二電源接墊群組係用於輸送一第二電源域電源訊號，該第一電源域電源訊號不同於該第二電源域電源訊號。
  7. 如申請專利範圍第1項所述的封裝基板，其中該第一塊狀介層插塞及該第二塊狀介層插塞包含銅。
  8. 如申請專利範圍第1項所述的封裝基板，其中該第一塊狀介層插塞環繞該第二塊狀介層插塞。
  9. 一種半導體封裝，該半導體封裝為球柵陣列式封裝，包含有：        如請求項1~8中任一項所述的封裝基板；以及     晶片，組裝到該封裝基板的該第一面上。
  10. 如申請專利範圍第9項之半導體封裝，其中該晶片以其主動面朝下之方式組裝到該封裝基板的該第一面上；    和/或，還包含：一晶片封裝，組裝到該封裝基板的該第一面上。
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