TWI381512B - 多晶片堆疊結構 - Google Patents

多晶片堆疊結構 Download PDF

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TWI381512B
TWI381512B TW098138383A TW98138383A TWI381512B TW I381512 B TWI381512 B TW I381512B TW 098138383 A TW098138383 A TW 098138383A TW 98138383 A TW98138383 A TW 98138383A TW I381512 B TWI381512 B TW I381512B
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substrate
interposer
stack structure
disposed
wafer stack
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TW201117347A (en
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Ji Cheng Lin
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Powertech Technology Inc
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    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
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    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Description

多晶片堆疊結構
本發明係有關一種多晶片堆疊結構。
鑒於半導體科技隨著電腦與網路通訊等產品功能急速提昇，因此必需具備多元化、可攜性與輕薄微小化之需求，使晶片封裝製程業脫離傳統技術而朝高功率、高密度、輕、薄與微小化等高精密度製程發展。
且隨著微小化以及高運作速度需求的增加，多晶片封裝構裝在許多電子裝置越來越常見。多晶片構造可藉由將兩個或兩個以上之晶片組合在單一封裝結構中，來使系統運作速度之限制最小化。
立體式封裝目前大致有兩種方式，分別是封裝上封裝(Package on Package，PoP)以及封裝內封裝(Package in Package，PiP)。PoP是一種很典型的3D封裝，係將兩個獨立的封裝體經封裝與測試後再以表面黏著方式疊合，可減少製程風險，進而提高產品良率。然而，由於PoP是將兩個獨立的封裝體加以堆疊，因此堆疊後的封裝厚度已不符合現今產品輕薄短小之趨勢。
一種將多顆晶片進行三維空間垂直整合之技術已被提出，以達到尺寸精簡的最佳效益。與現有平面的晶片整合有所不同，三維空間垂直整合之技術採取上下導通的架構，因此晶片間的連接長度及延遲時間均較傳統二維電路明顯縮短，同時提升晶片效能並降低晶片功耗。惟，不同類型的晶片之間，因輸入輸出佈線設計大不相同，故整合時的製程有相當的難度。
為了解決上述問題，本發明目的之一係提供一種多晶片堆疊結構，利用在記憶體晶片與邏輯晶片中間設置中介基板來簡化製程複雜度並節省基板成本。
本發明目的之一係提供一種多晶片堆疊結構包括：一基板；複數記憶體晶片設置於基板上並與基板上表面電性連接；一中介基板設置於記憶體晶片上方，其中複數第一接點與複數第二接點設置於中介基板一上表面，且第二接點係位於中介基板之週緣；及複數第一凸塊設置於中介基板一下表面，且第一凸塊係與記憶體晶片電性連接；一邏輯晶片設置於中介基板之上表面並與第一接點電性連接；以及，複數金線係用以電性連接中介基板的第二接點與基板上表面。
以下藉由具體實施例配合所附的圖式詳加說明，當更容易瞭解本發明之目的、技術內容、特點及其所達成之功效。
其詳細說明如下，所述較佳實施例僅做一說明非用以限定本發明。
請參考圖1，圖1為本發明一實施例之一種多晶片堆疊結構之示意圖。如圖所示，多晶片封裝結構包括：一基板10、複數記憶體晶片20、一中介基板30、一邏輯晶片40與複數條金線50。如圖所示，記憶體晶片20係堆疊設置於基板10上並與基板10的上表面11電性連接。中介基板30，例如矽材質所構成，設置於記憶體晶片20上方，其中中介基板30含有複數第一接點32與複數第二接點34設置於其一上表面31，且第二接點34係位於中介基板30之適緣。以及複數第一凸塊36設置於中介基板30之一下表面35，且第一凸塊36係與設置於其下之記憶體晶片20電性連接。邏輯晶片40設置於中介基板30之上表面31並與第一接點32電性連接。以及複數金線50用以電性連接中介基板30的第二接點34與基板10上表面11。其中中介基板30的使用可改善因為記憶體晶片20與邏輯晶片40的輸入/輸出佈線設計(I/O layout)與功能的不同所產生的複雜製程。
接續上述，請參考圖2，於此實施例中，邏輯晶片40設置於多晶片堆疊結構最上方有利於散熱管理，故本發明一實施例中更包括一散熱片60設置於邏輯晶片40上以加強散熱，更者，將邏輯晶片40設置於多晶片堆疊結構最上方亦可降低下方基板10設計的複雜度，進而降低基板成本。接續參考圖2，此結構中更包括複數銲球70設置於基板10的下表面13以構裝於外界裝置上。
繼續參考圖1，於一實施例中，記憶體晶片20係利用複數矽通孔結構22相互電性連接。且如圖1所示，更可包括複數第二凸塊26設置於矽通孔結構22下，使得位於上方的記憶體晶片20藉由第二凸塊26與位於下方之記憶體晶片20的矽通孔結構22電性連接。此外，中介基板30的第一凸塊36與設置於其下之記憶體晶片20也是利用矽通孔結構22電性連接。利用矽通孔結構作為電性連接的橋樑可減少打線堆疊的空間以縮小多晶片堆疊結構的尺寸。於一實施例中，如圖1所示，複數銲球42設置於邏輯晶片40下方，用以電性連接邏輯晶片40與中介基板30上的第一接點32。邏輯晶片40利用銲球42的方式、結構與中介基板30電性連接，可改善因熱膨脹係數不同而可能產生的翹曲問題。
於又一實施例中，如圖3A所示，多晶片封裝結構更包括一封裝膠體80包覆基板10的上表面11、記憶體晶片20、中介基板30、邏輯晶片40與金線50。於再一實施例中，如圖3B所示，其中封裝膠體80曝露部分邏輯晶片40，例如邏輯晶片40的上表面41，且一散熱片62設置於封裝膠體80上並貼附曝露出的部份邏輯晶片40，如邏輯晶片40的上表面41，以加強散熱功能。於另一實施例中，如圖3C所示，多晶片堆疊封裝更包括一底膠90填充於基板10與記憶體晶片20之間、記憶體晶片20與記憶體晶片20之間、與中介基板30與記憶體晶片20之間。於又一實施例中，請參考圖3D，在堆疊各記憶體晶片20時，亦可直接利用矽通孔結構22作為電性連接的橋樑，不需設置凸塊。
依據上述，本發明特徵之一係將邏輯晶片設置於多晶片堆疊結構的最上方以加強散熱功能。此外，邏輯晶片利用複數銲球與中介基板上的第一接點電性連接，可改善中介基板與邏輯晶片因熱膨脹係數不同而可能產生的翹曲、電性接合不良的問題。更者，將邏輯晶片設置於中介基板上，可在中介基板上針對不同的邏輯晶片的輸入輸出佈線設計重新佈線，製程上相當彈性。再來，中介基板與複數堆疊的記憶體晶片皆可使用矽通孔結構相互電性連接，亦可有效改善多晶片堆疊封裝後的厚度。
綜合上述，本發明利用在記憶體晶片與邏輯晶片中間設置中介基板來簡化製程複雜度並節省基板成本。
以上所述之實施例僅係為說明本發明之技術思想及特點，其目的在使熟習此項技藝之人士能夠瞭解本發明之內容並據以實施，當不能以之限定本發明之專利範圍，即大凡依本發明所揭示之精神所作之均等變化或修飾，仍應涵蓋在本發明之專利範圍內。
10．．．基板
11,31,41．．．上表面
13,35．．．下表面
20．．．記憶體晶片
22．．．矽通孔結構
26,36．．．凸塊
30．．．中介基板
32．．．第一接點
34．．．第二接點
40．．．邏輯晶片
42,70．．．銲球
50．．．金線
60,62．．．散熱片
80．．．封裝膠體
90．．．底膠
圖1為本發明一實施例之多晶片堆疊結構之剖視圖。
圖2為本發明又一實施例之多晶片堆疊結構之剖視圖。
圖3A、圖B、圖3C、圖3D為本發明不同實施例多晶片堆疊結構之剖視圖。
10‧‧‧基板
11,31‧‧‧上表面
13,35‧‧‧下表面
20‧‧‧記憶體晶片
22‧‧‧矽通孔結構
26,36‧‧‧凸塊
30‧‧‧中介基板
32‧‧‧第一接點
34‧‧‧第二接點
40‧‧‧邏輯晶片
42‧‧‧銲球
50‧‧‧金線

Claims (10)

  1. 一種多晶片堆疊結構，包含：一基板；複數記憶體晶片，堆疊設置於該基板上並與該基板上表面電性連接；一中介基板，設置於該些記憶體晶片上方，其中複數第一接點與複數第二接點，設置於該中介基板一上表面，且該些第二接點係位於該中介基板之週緣；及複數第一凸塊，設置於該中介基板一下表面，且該些第一凸塊係與該些記憶體晶片電性連接；一邏輯晶片，設置於該中介基板之該上表面並與該些第一接點電性連接；以及複數金線，係用以電性連接該中介基板的該些第二接點與該基板上表面。
  2. 如請求項1所述之多晶片堆疊結構，其中該些記憶體晶片係利用複數矽通孔結構相互電性連接。
  3. 如請求項2所述之多晶片堆疊結構，更包含複數第二凸塊設置於該些矽通孔結構下，使得位於上方的該記憶體晶片藉由該些第二凸塊與位於下方之該記憶體晶片的該些矽通孔結構電性連接。
  4. 如請求項2所述之多晶片堆疊結構，其中該中介基板上的該些第一凸塊係與設置於其下之該記憶體晶片的該些矽通孔結構電性連接。
  5. 如請求項1所述之多晶片堆疊結構，其中複數銲球設置於該邏輯晶片下方，用以電性連接該邏輯晶片與該中介基板之該些第一接點。
  6. 如請求項1所述之多晶片堆疊結構，更包含複數銲球設置於該基板下表面。
  7. 如請求項1所述之多晶片堆疊結構，更包含一散熱片設置於該邏輯晶片上。
  8. 如請求項1所述之多晶片堆疊結構，更包含一封裝膠體包覆該基板上表面、該些記憶體晶片、該中介基板與該邏輯晶片。
  9. 如請求項7所述之多晶片堆疊結構，其中該封裝膠體曝露部分該邏輯晶片，且一散熱片設置於該封裝膠體上並貼附曝露出的部份該邏輯晶片。
  10. 如請求項1所述之多晶片堆疊結構，更包含一底膠填充於該基板與該些記憶體晶片之間、該些記憶體晶片之間、與該中介基板與該記憶體晶片之間。
TW098138383A 2009-11-12 2009-11-12 多晶片堆疊結構 TWI381512B (zh)

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US20020085334A1 (en) * 2000-12-29 2002-07-04 Intel Corporation Multiple tier array capacitor and methods of fabrication therefor
US20030153122A1 (en) * 2002-02-13 2003-08-14 Michael Brooks Methods and apparatus for a stacked-die interposer
US7098528B2 (en) * 2003-12-22 2006-08-29 Lsi Logic Corporation Embedded redistribution interposer for footprint compatible chip package conversion
US20080067659A1 (en) * 2006-09-20 2008-03-20 Samsung Electronics Co., Ltd. Stacked semiconductor package, method of fabrication, and method of wire-bond monitoring
KR20090080701A (ko) * 2008-01-22 2009-07-27 주식회사 하이닉스반도체 반도체 패키지 및 이를 이용한 적층 패키지

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