TW201633500A - 堆疊式封裝及具有其的可攜式電腦裝置 - Google Patents

堆疊式封裝及具有其的可攜式電腦裝置 Download PDF

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Publication number
TW201633500A
TW201633500A TW104137977A TW104137977A TW201633500A TW 201633500 A TW201633500 A TW 201633500A TW 104137977 A TW104137977 A TW 104137977A TW 104137977 A TW104137977 A TW 104137977A TW 201633500 A TW201633500 A TW 201633500A
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Taiwan
Prior art keywords
die
printed circuit
circuit board
package
wafer
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TW104137977A
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English (en)
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TWI703704B (zh
Inventor
權興奎
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三星電子股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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Abstract

一種堆疊式封裝可包括：第一印刷電路板；底部封裝，包括附著至所述第一印刷電路板的第一晶片晶粒及第二晶片晶粒；頂部封裝，包括第二印刷電路板及附著至所述第二印刷電路板的第三晶片晶粒，且上覆於所述底部封裝上；及/或第一堆疊連接焊球及第二堆疊連接焊球，電性連接於所述第一印刷電路板與所述第二印刷電路板之間，且僅圍繞所述底部封裝的各個側中相互面對的兩個側形成。

Description

堆疊式封裝及具有其的可攜式電腦裝置
本發明概念的某些示例性實施例可大體是有關於堆疊式封裝。本發明概念的某些示例性實施例可大體是有關於僅圍繞保護性材料的各個側中相互面對的兩個側安置用於堆疊底部封裝及頂部封裝的堆疊連接球的堆疊式封裝，所述保護性材料包括附著至底部封裝的印刷電路板的晶片晶粒。本發明概念的某些示例性實施例可大體是有關於具有堆疊式封裝的行動電腦裝置。
半導體晶片的封裝（packaging）可指代用於將晶片晶粒連接至外部系統的中間步驟製程。隨著例如智慧型電話及平板個人電腦（personal computer，PC）等可攜式裝置的使用的增長，製造商可嘗試開發更輕及更小的可攜式裝置。在可攜式裝置中可能會使用相當多的積體電路（integrated circuit），且可將積體電路中的每一者封裝成半導體封裝。
堆疊式封裝（package on package，PoP）可節約系統板的空間，且為減小可攜式電子裝置的大小，可能是在智慧型電話及平板個人電腦的製造中所必需的。具體而言，記憶體封裝（例如，頂部封裝）可堆疊於邏輯封裝（例如，底部封裝）上方以減小印刷電路板（printed circuit board，PCB）的表面積。為減小包括多個堆疊式封裝的可攜式電子裝置的大小，可能需要減小所述多個堆疊式封裝中的每一者的大小及高度。
本發明概念的某些示例性實施例可提供堆疊式封裝。
本發明概念的某些示例性實施例可提供僅圍繞保護性材料的各個側中相互面對的兩個側安置用於堆疊底部封裝及頂部封裝的堆疊連接球的堆疊式封裝，所述保護性材料包括附著至底部封裝的印刷電路板的晶片晶粒。
本發明概念的某些示例性實施例可提供具有堆疊式封裝的行動電腦裝置。
在某些示例性實施例中，一種堆疊式封裝可包括：第一印刷電路板（PCB）；底部封裝，包括附著至所述第一印刷電路板的第一晶片晶粒及第二晶片晶粒；頂部封裝，包括第二印刷電路板以及附著至所述第二印刷電路板的第三晶片晶粒，且上覆於所述底部封裝上；及/或第一堆疊連接焊球及第二堆疊連接焊球，電性連接於所述第一印刷電路板與所述第二印刷電路板之間，且僅圍繞所述底部封裝的各個側中相互面對的兩個側形成。
在某些示例性實施例中，所述第一晶片晶粒可包括數據機（modem）晶片晶粒。所述第二晶片晶粒可包括動態隨機存取記憶體（dynamic random-access memory，DRAM）晶片晶粒或偽靜態隨機存取記憶體（static random-access memory，SRAM）晶片晶粒。所述底部封裝可包括系統級封裝（SiP）。
在某些示例性實施例中，所述第一晶片晶粒可經由第一凸塊以倒裝晶片結構（flip-chip structure）附著至所述第一印刷電路板。所述第二晶片晶粒經由第二凸塊以所述倒裝晶片結構附著至所述第一印刷電路板。
在某些示例性實施例中，所述第一晶片晶粒可經由第一凸塊以倒裝晶片結構附著至所述第一印刷電路板。所述第二晶片晶粒可經由第二凸塊以所述倒裝晶片結構附著至所述第一印刷電路板。所述第一晶片晶粒與所述第一印刷電路板之間的中空空間及所述第二晶片晶粒與所述第一印刷電路板之間的中空空間可被填充以毛細管底部填充（capillary underfill，CUF）材料。
在某些示例性實施例中，所述第一晶片晶粒可經由第一凸塊以倒裝晶片結構附著至所述第一印刷電路板。所述第二晶片晶粒可經由第二凸塊以所述倒裝晶片結構附著至所述第一印刷電路板。所述第一晶片晶粒與所述第一印刷電路板之間的中空空間及所述第二晶片晶粒與所述第一印刷電路板之間的中空空間、所述第一晶片晶粒、及所述第二晶片晶粒可使用模製底部填充（molded underfill，MUF）材料進行囊封。
在某些示例性實施例中，所述第一晶片晶粒可經由凸塊以倒裝晶片結構附著至所述第一印刷電路板。所述第二晶片晶粒可經由打線接合附著至所述第一印刷電路板。所述第一晶片晶粒與所述第一印刷電路板之間的中空空間、所述第一晶片晶粒、及所述第二晶片晶粒可使用模製底部填充（MUF）材料進行囊封。
在某些示例性實施例中，其中所述頂部封裝可更包括附著至所述第二印刷電路板的記憶體控制器。所述記憶體控制器可用以控制所述第三晶片晶粒的運作。所述第三晶片晶粒可包括快閃型記憶體晶片晶粒。
在某些示例性實施例中，用於所述第三晶片晶粒及所述記憶體控制器的運作的所有訊號及所有供電電壓可僅經由所述第一堆疊連接焊球進行傳送。
在某些示例性實施例中，所述第二堆疊連接焊球中的每一者可均處於電性浮動狀態。
在某些示例性實施例中，用於所述第三晶片晶粒及所述記憶體控制器的運作的所有訊號、及用於所述第三晶片晶粒及所述記憶體控制器中的至少一者的運作的第一供電電壓的一部分可經由所述第一堆疊連接焊球進行傳送。用於所述第三晶片晶粒及所述記憶體控制器中的至少一者的運作的第二供電電壓的其餘部分可經由所述第二堆疊連接焊球進行傳送。
在某些示例性實施例中，經由附著至所述第一印刷電路板的底面的相應焊球而輸入的所述第二供電電壓可被經由所述第一印刷電路板傳送至所述底部封裝及所述第二堆疊連接焊球。
在某些示例性實施例中，所述第一晶片晶粒及所述第二晶片晶粒可僅經由形成於所述第一印刷電路板中的訊號線而向彼此傳送訊號或自彼此接收訊號。
在某些示例性實施例中，一種行動電腦裝置可包括：系統板；第一封裝，附著至所述系統板；及/或電力管理積體電路（power management integrated circuit，PMIC），附著至所述系統板且用以經由所述系統板供應第一供電電壓至所述第一封裝。所述第一封裝可包括：第一印刷電路板（PCB）；底部封裝，包括附著至所述第一印刷電路板的第一晶片晶粒及第二晶片晶粒；頂部封裝，包括第二印刷電路板及附著至所述第二印刷電路板的第三晶片晶粒，且上覆於所述底部封裝上；及/或第一堆疊連接焊球及第二堆疊連接焊球，電性連接於所述第一印刷電路板與所述第二印刷電路板之間，且僅圍繞所述底部封裝的各個側中相互面對的兩個側形成。
在某些示例性實施例中，所述第一晶片晶粒可包括數據機晶片晶粒。所述第二晶片晶粒可包括動態隨機存取記憶體（DRAM）晶片晶粒或偽靜態隨機存取記憶體（SRAM）晶片晶粒。所述底部封裝可包括系統級封裝（SiP）。
在某些示例性實施例中，所述頂部封裝可更包括附著至所述第二印刷電路板的記憶體控制器。所述記憶體控制器可用以控制所述第三晶片晶粒的運作。所述第三晶片晶粒可包括快閃型記憶體晶片晶粒。
在某些示例性實施例中，用於所述第三晶片晶粒及所述記憶體控制器的運作的所有訊號、及用於所述第三晶片晶粒及所述記憶體控制器的運作的所有所述第一供電電壓可僅經由所述第一堆疊連接焊球進行傳送。
在某些示例性實施例中，所述行動電腦裝置可更包括附著至所述系統板的第二封裝且包括應用處理器晶片晶粒。所述電力管理積體電路可用以經由所述系統板供應第二供電電壓至所述應用處理器晶片晶粒。所述系統板可包括用以傳送在所述應用處理器晶片晶粒與所述第一封裝之間傳送或接收的訊號的訊號線。所述訊號線可經由所述第一印刷電路板連接至所述第一堆疊連接焊球中的對應堆疊連接焊球。
在某些示例性實施例中，所述系統板可包括接地線。所述第一供電電壓可包括工作電壓及接地電壓。所述第一堆疊連接焊球中與所述接地電壓相關的連接焊球可經由所述第一印刷電路板連接至所述接地線。所述工作電壓可經由所述第一印刷電路板被供應至所述第一堆疊連接焊球中的對應堆疊連接焊球。
在某些示例性實施例中，用於所述第三晶片晶粒及所述記憶體控制器的運作的所有訊號、及所述第一供電電壓中用於所述第三晶片晶粒及所述記憶體控制器中的至少一者的運作的第二供電電壓可僅經由所述第一堆疊連接焊球進行傳送。所述第一供電電壓中用於所述第三晶片晶粒及所述記憶體控制器中的至少一者的運作的第三供電電壓可僅經由所述第二堆疊連接焊球中的相應連接焊球進行傳送。經由附著至所述第一印刷電路板的底面的焊球而輸入的所述第三供電電壓可經由所述第一印刷電路板傳送至所述相應連接焊球及所述底部封裝。
在某些示例性實施例中，所述行動電腦裝置可更包括附著至所述系統板的第二封裝且包括應用處理器晶片晶粒。所述電力管理積體電路可用以經由所述系統板供應第四供電電壓至所述應用處理器晶片晶粒。所述系統板可包括用於傳送在所述應用處理器晶片晶粒與所述第一封裝之間傳送或接收的訊號的訊號線。所述訊號線可經由所述第一印刷電路板連接至所述第一堆疊連接焊球中的對應堆疊連接焊球。
在某些示例性實施例中，一種電子裝置可包括：第一印刷電路板（PCB）；第一晶片晶粒，位於所述第一印刷電路板上；第二晶片晶粒，位於所述第一印刷電路板上；第二印刷電路板，位於所述第一晶片晶粒及所述第二晶片晶粒上；至少一個第三晶片晶粒，位於所述第二印刷電路板上；及/或第一堆疊連接焊球及第二堆疊連接焊球，電性連接於所述第一印刷電路板與所述第二印刷電路板之間。所述第一堆疊連接焊球可位於所述第一晶片晶粒及所述第二晶片晶粒的與所述第二堆疊連接焊球相對的側上。
在某些示例性實施例中，所述第二晶片晶粒可位於所述第一晶片晶粒上。
在某些示例性實施例中，所述第一晶片晶粒可包括數據機晶片晶粒。所述第二晶片晶粒可包括動態隨機存取記憶體（DRAM）晶片晶粒或偽靜態隨機存取記憶體（SRAM）晶片晶粒。
在某些示例性實施例中，所述第一晶片晶粒可經由第一凸塊以倒裝晶片結構附著至所述第一印刷電路板。所述第二晶片晶粒可經由第二凸塊以所述倒裝晶片結構附著至所述第一印刷電路板。
在某些示例性實施例中，所述第一晶片晶粒可經由第一凸塊以倒裝晶片結構附著至所述第一印刷電路板。所述第二晶片晶粒可經由第二凸塊以所述倒裝晶片結構附著至所述第一印刷電路板。所述第一晶片晶粒與所述第一印刷電路板之間的中空空間及所述第二晶片晶粒與所述第一印刷電路板之間的中空空間可被填充以毛細管底部填充（CUF）材料。
在某些示例性實施例中，所述第一晶片晶粒可經由第一凸塊以倒裝晶片結構附著至所述第一印刷電路板。所述第二晶片晶粒可經由第二凸塊以倒裝晶片結構附著至所述第一印刷電路板。所述第一晶片晶粒與所述第一印刷電路板之間的中空空間、及所述第二晶片晶粒與所述第一印刷電路板之間的中空空間、所述第一晶片晶粒、及所述第二晶片晶粒可使用模製底部填充（MUF）材料進行囊封。
在某些示例性實施例中，所述第一晶片晶粒可經由凸塊以倒裝晶片結構附著至所述第一印刷電路板。所述第二晶片晶粒可經由打線接合附著至所述第一印刷電路板。所述第一晶片晶粒與所述第一印刷電路板之間的中空空間、所述第一晶片晶粒、及所述第二晶片晶粒可使用模製底部填充（MUF）材料進行囊封。
在某些示例性實施例中，所述電子裝置可更包括：記憶體控制器，位於所述第二印刷電路板上。所述記憶體控制器可用以控制至少一個第三晶片晶粒的運作。
現在將參照附圖來更充分地闡述示例性實施例。然而，實施例可實施為諸多不同形式，而不應被視為僅限於本文所說明的實施例。更確切而言，提供該些示例性實施例是為了使本揭露內容將透徹及完整，並將向熟習此項技術者充分傳達本揭露內容的範圍。在圖式中，為清晰起見，可誇大層及區的厚度。
應理解，當稱一個元件位於另一組件「上（on）」，或「連接至（connected to）」、「電性連接至（electrically connected to）」、或「耦合至（coupled to）」另一組件時，所述元件可直接位於所述另一組件上，或直接連接至、電性連接至、或耦合至所述另一組件，抑或可存在中間組件。相反，當稱一個組件「直接（directly）」位於另一組件「上（on）」，或「直接連接至（directly connected to）」、「直接電性連接至（directly electrically connected to）」、或「直接耦合至（directly coupled to）」至另一組件時，則不存在中間組件。本文中所用用語「及/或（and/or）」包含相關列出項其中一或多個項的任意及所有組合。
應理解，儘管本文中可能使用第一（first）、第二（second）、第三（third）等用語來闡述各種元件、組件、區、層、及/或區段，但該些元件、組件、區、層、及/或區段不應受該些用語限制。該些用語僅用於區分各個元件、組件、區、層、及/或區段。舉例而言，第一元件、組件、區、層、及/或區段可被稱為第二元件、組件、區、層、及/或區段，此並不背離示例性實施例的教示內容。
為便於說明，本文中可使用例如「在…之下（beneath）」、「在…下面（below）」、「下方的（lower）」、「在…之上（above）」、「上方的（upper）」等空間相對關係用語來闡述圖式所示一個組件及/或特徵與另一組件及/或特徵、或其他組件及/或特徵的關係。應理解，空間相對關係用語旨在除圖中所繪示的定向外亦涵蓋裝置在使用或操作中的不同定向。
本文中所使用術語僅是為了闡述特定示例性實施例而並非旨在限制示例性實施例。除非上下文清楚地另外指明，否則本文中所使用的單數形式「一（a、an）」及「所述（the）」旨在亦包括複數形式。更應理解，當在本說明書中使用用語「包括（comprises/comprising）」、「包含（includes及/或including）」時，是指明所陳述特徵、整數、步驟、操作、元件、及/或組件的存在，但不排除一或多個其他特徵、整數、步驟、操作、元件、組件、及/或其群組的存在或添加。
在本文中可參照剖視圖來闡述示例性實施例，其中剖視圖是對理想化示例性實施例（及中間結構）的示意性說明。因此，預期存在由例如製造技術及/或容差所造成的與圖示形狀的偏差。因此，示例性實施例不應被視作僅限於本文中所示區的特定形狀，而是欲包括由例如製造所導致的形狀偏差。舉例而言，被示出為矩形的植入區將通常具有圓形特徵或曲線特徵及/或在其邊緣處具有植入濃度的梯度，而非自植入區至非植入區為二元變化。相同地，藉由植入而形成的隱埋區可在隱埋區與在進行植入時所經過的表面之間的區中造成某些植入。因此，圖中所示的區為示意性的，其形狀並非旨在說明裝置的區的實際形狀，且其形狀並非旨在限制示例性實施例的範圍。
除非另有定義，否則本文中所用的全部用語（包括技術用語及科學用語）的意義皆與示例性實施例所屬技術領域中的通常知識者所通常理解的意義相同。更應理解，用語（例如在常用辭典中所定義的用語）應被解釋為具有與其在相關技術的上下文中的意義一致的意義，且除非在本文中進行明確定義，否則不應將其解釋為具有理想化或過於正式的意義。
現在將參照附圖中所示的示例性實施例，其中通篇中相同的參考編號可指代相同的組件。
圖1至圖14是根據本發明概念的某些示例性實施例的底部封裝的剖視圖。
參照圖1，底部封裝100A可包括第一印刷電路板（PCB）110、分別附著至或安裝於第一印刷電路板110的頂面上的第一晶片晶粒130及第二晶片晶粒140。焊球112可附著至第一印刷電路板110的底面上。焊球131可附著至第一印刷電路板110的頂面。焊球112或焊球131可為凸塊、焊料凸塊、或銅凸塊。焊球112包括焊球11至焊球14。
本說明書中所闡述的焊球、凸塊、焊料凸塊、或銅凸塊是互連件（interconnection）的某些示例性實施例。焊球112可經由焊墊（pad）附著至第一印刷電路板110的底面。具有導電性的焊墊可為接腳（pin）或焊盤（land pad）。
晶片晶粒可為晶片或晶粒。根據某些示例性實施例，圖1至圖14中所示的底部封裝100A至底部封裝100J、底部封裝100A-1、100B-1、100C-1、及100D-1可實施於系統級封裝（SiP）中；然而，示例性實施例並非僅限於此。
第一晶片晶粒130可以倒裝晶片結構附著至第一印刷電路板110。根據某些示例性實施例，第一晶片晶粒130可經由焊球131附著至第一印刷電路板110。根據某些示例性實施例，第一晶片晶粒130可實施於數據機晶片晶粒或支援寬頻分碼多重存取（wideband code division multiple access，WCDMA）通訊方法的數據機晶片晶粒中；然而，示例性實施例並非僅限於此。
由於第一晶片晶粒130經由焊球131附著至第一印刷電路板110，故第一印刷電路板110的頂部與第一晶片晶粒130之間的中空空間可被填充以底部填充材料133。舉例而言，底部填充材料133可藉由毛細管底部填充（CUF）製程填充所述空間。因此，藉由毛細管底部填充製程填充中空空間的底部填充材料被稱為毛細管底部填充材料。
第二晶片晶粒140可經由晶粒附著（die attach）材料141附著至第一印刷電路板110。根據某些示例性實施例，晶粒附著材料141可為膜（film）或液體環氧黏合劑（liquid epoxy adhesive）；然而，示例性實施例並非僅限於此。根據某些示例性實施例，第二晶片晶粒140可實施於動態隨機存取記憶體（DRAM）晶片晶粒或偽靜態隨機存取記憶體（SRAM）晶片晶粒中；然而，示例性實施例並非僅限於此。所述偽靜態隨機存取記憶體可包括具有靜態隨機存取記憶體介面的動態隨機存取記憶體微芯（micro core）。
第二晶片晶粒140可使用打線接合接觸第一印刷電路板110。此外，第二晶片晶粒140可使用導線（wire）143向第一印刷電路板110傳送訊號或自第一印刷電路板110接收訊號。第一晶片晶粒130及第二晶片晶粒140可並排附著至第一印刷電路板110。
圖1示出其中第一晶片晶粒130以倒裝晶片結構附著至第一印刷電路板110、且第二晶片晶粒140經由晶粒附著材料141附著至第一印刷電路板110的示例性實施例；然而，示例性實施例並非僅限於此。第一晶片晶粒130及第二晶片晶粒140可經由實施於第一印刷電路板110中的訊號線SL而彼此電性連接。因此，第一晶片晶粒130及第二晶片晶粒140可經由訊號線SL向彼此傳送訊號或自彼此接收訊號。
供電電壓可包括工作電壓及接地電壓。供電電壓可提供電力。第一工作電壓VDD1可經由焊球11及第一印刷電路板110被供應至第一晶片晶粒130，且接地電壓VSS可經由焊球13及第一印刷電路板110被供應至第一晶片晶粒130。第二工作電壓VDD2可經由焊球12及第一印刷電路板110被供應至第二晶片晶粒140，且接地電壓VSS可經由焊球14及第一印刷電路板110被供應至第二晶片晶粒140。
即，與第一晶片晶粒130的第一工作電壓VDD1及接地電壓VSS（例如，供電電壓）相關的觸點或接腳可經由焊球11及焊球13引出，且與第二晶片晶粒140的第二工作電壓VDD2及接地電壓VSS（例如，供電電壓）相關的觸點或接腳可經由焊球12及焊球14引出。
參照圖2，底部封裝100B包括附著至第一印刷電路板110的第一晶片晶粒130及第二晶片晶粒140。參照圖1及圖2，附著至第一印刷電路板110的第一晶片晶粒130及第二晶片晶粒140可經由焊球16及第一印刷電路板110而被提供以工作電壓VDD，並可經由焊球17及第一印刷電路板110而被提供以接地電壓VSS。即，與第一晶片晶粒130及第二晶片晶粒140中的每一者的工作電壓VDD及接地電壓VSS（例如，供電電壓）相關的觸點或接腳可經由焊球16及焊球17引出。
參照圖3，底部封裝100C可包括堆疊於第一晶片晶粒130上或上方的第二晶片晶粒140。第二晶片晶粒140可經由晶粒附著材料141堆疊於第一晶片晶粒130的頂面上方。第二晶片晶粒140可經由導線及焊墊連接至第一印刷電路板110。即，第二晶片晶粒140可經由打線接合連接至第一印刷電路板110。
第一晶片晶粒130及第二晶片晶粒140可經由實施於第一印刷電路板110中的訊號線SL彼此連接。因此，第一晶片晶粒130及第二晶片晶粒140可經由實施於第一印刷電路板110中的訊號線SL向彼此傳送訊號或自彼此接收訊號。
第一工作電壓VDD1可經由焊球21被供應至第一晶片晶粒130，且接地電壓VSS可經由焊球23被供應至第一晶片晶粒130。第二工作電壓VDD2可經由焊球22被供應至第二晶片晶粒140，且接地電壓VSS可經由焊球24被供應至第二晶片晶粒140。
參照圖3及圖4，底部封裝100D包括堆疊於第一晶片晶粒130上或上方的第二晶片晶粒140。附著至第一印刷電路板110的第一晶片晶粒130及第二晶片晶粒140經由焊球26而被提供以工作電壓VDD，並經由焊球27而被提供以接地電壓VSS。
參照圖5，底部封裝100E包括附著至第一印刷電路板110的第一晶片晶粒130及第二晶片晶粒140。第一晶片晶粒130及第二晶片晶粒140中的每一者可以倒裝晶片結構附著至第一印刷電路板110。
第二晶片晶粒140可經由焊球131a附著至第一印刷電路板110。第一印刷電路板110的頂部與第二晶片晶粒140之間的中空空間可被填充以底部填充材料133a。底部填充材料133a可為毛細管底部填充材料。第一晶片晶粒130及第二晶片晶粒140可經由實施於第一印刷電路板110中的訊號線SL向彼此傳送訊號或自彼此接收訊號。
第一工作電壓VDD1經由焊球31被供應至第一晶片晶粒130，且接地電壓VSS經由焊球33被供應至第一晶片晶粒130。第二工作電壓VDD2經由焊球32被供應至第二晶片晶粒140，且接地電壓VSS經由焊球34被供應至第二晶片晶粒140。
參照圖6，底部封裝100F包括附著至第一印刷電路板110的第一晶片晶粒130及第二晶片晶粒140。附著至第一印刷電路板110的第一晶片晶粒130及第二晶片晶粒140經由焊球36而被提供以工作電壓VDD，並經由焊球37而被提供以接地電壓VSS。
參照圖7，底部封裝100G包括附著至第一印刷電路板110的第一晶片晶粒130及第二晶片晶粒140。第一晶片晶粒130及第二晶片晶粒140中的每一者以倒裝晶片結構附著至第一印刷電路板110。
第一晶片晶粒130及第二晶片晶粒140可藉由模製底部填充（MUF）製程而使用模製底部填充材料MOLD進行模製。此時，第一晶片晶粒130及第二晶片晶粒140中的每一者與第一印刷電路板110之間的中空空間可被填充以模製底部填充材料MOLD。舉例而言，模製底部填充材料MOLD可為環氧模製化合物（epoxy molding compound，EMC）；然而，示例性實施例並非僅限於此。
第一工作電壓VDD1經由焊球41被供應至第一晶片晶粒130，且接地電壓VSS經由焊球43被供應至第一晶片晶粒130。第二工作電壓VDD2經由焊球42被供應至第二晶片晶粒140，且接地電壓VSS經由焊球44被供應至第二晶片晶粒140。
參照圖8，底部封裝100H包括附著至第一印刷電路板110的第一晶片晶粒130及第二晶片晶粒140。第一晶片晶粒130及第二晶片晶粒140中的每一者以倒裝晶片結構附著至第一印刷電路板110。
第一晶片晶粒130及第二晶片晶粒140可使用模製底部填充材料MOLD進行模製。此時，第一晶片晶粒130及第二晶片晶粒140中的每一者與第一印刷電路板110之間的中空空間可被填充以模製底部填充材料MOLD。附著至第一印刷電路板110的第一晶片晶粒130及第二晶片晶粒140經由焊球46而被提供以工作電壓VDD，並經由焊球47而被提供以接地電壓VSS。
參照圖9，底部封裝100I包括附著至第一印刷電路板110的第一晶片晶粒130及第二晶片晶粒140。第一晶片晶粒130及第二晶片晶粒140中的每一者以倒裝晶片結構附著至第一印刷電路板110。
第一晶片晶粒130與第一印刷電路板110之間的中空空間可經由毛細管底部填充製程而被填充以底部填充材料133，且第二晶片晶粒140與第一印刷電路板110之間的中空空間可經由毛細管底部填充製程而被填充以底部填充材料133a。第一晶片晶粒130的周邊及第二晶片晶粒140的周邊可藉由模製底部填充製程而使用模製底部填充材料MOLD進行囊封。
第一工作電壓VDD1可經由焊球51被供應至第一晶片晶粒130，且接地電壓VSS可經由焊球53被供應至第一晶片晶粒130。第二工作電壓VDD2可經由焊球52被供應至第二晶片晶粒140，且接地電壓VSS可經由焊球54被供應至第二晶片晶粒140。
參照圖10，底部封裝100J包括附著至第一印刷電路板110的第一晶片晶粒130及第二晶片晶粒140。第一晶片晶粒130及第二晶片晶粒140中的每一者以倒裝晶片結構附著至第一印刷電路板110。
第一晶片晶粒130及第二晶片晶粒140可藉由毛細管底部填充製程及模製底部填充製程進行囊封。附著至第一印刷電路板110的第一晶片晶粒130及第二晶片晶粒140經由焊球56而被提供以工作電壓VDD，並經由焊球57而被提供以接地電壓VSS。
參照圖1及圖11，底部封裝100A-1包括以倒裝晶片結構附著至第一印刷電路板110的第一晶片晶粒130及經由打線接合連接至第一印刷電路板110的第二晶片晶粒140。
第一晶片晶粒130及第二晶片晶粒140可由藉由模製底部填充製程形成的保護性材料150環繞。舉例而言，保護性材料150可為環氧模製化合物（EMC）；然而，示例性實施例並非僅限於此。
參照圖2及圖12，底部封裝100B-1包括以倒裝晶片結構附著至第一印刷電路板110的第一晶片晶粒130以及經由打線接合連接至第一印刷電路板110的第二晶片晶粒140。第一晶片晶粒130及第二晶片晶粒140可由藉由模製底部填充製程形成的保護性材料150環繞。舉例而言，保護性材料150可為環氧模製化合物；然而，示例性實施例並非僅限於此。
參照圖3及圖13，底部封裝100C-1包括堆疊於第一晶片晶粒130上或上方的第二晶片晶粒140。第一晶片晶粒130及第二晶片晶粒140可由藉由模製底部填充製程形成的保護性材料150環繞。舉例而言，保護性材料150可為環氧模製化合物；然而，示例性實施例並非僅限於此。
參照圖4及圖14，底部封裝100D-1包括堆疊於第一晶片晶粒130上或上方的第二晶片晶粒140。第一晶片晶粒130及第二晶片晶粒140可由藉由模製底部填充製程形成的保護性材料150環繞。舉例而言，保護性材料150可為環氧模製化合物；然而，示例性實施例並非僅限於此。
圖15至圖18是根據本發明概念的某些示例性實施例的包括底部封裝及頂部封裝的堆疊式封裝的剖視圖。參照圖11及圖15，頂部封裝TPG的第二印刷電路板170可經由互連件160（例如，堆疊連接焊球160）電性連接至第一印刷電路板110。如圖17所示，堆疊連接焊球160可包括第一堆疊連接焊球SJB1及第二堆疊連接焊球SJB2。如上所述，堆疊連接焊球可連接於形成於第一印刷電路板110的頂面上的焊墊與形成於第二印刷電路板170的底面上的焊墊之間。頂部封裝TPG可堆疊於底部封裝100A-1上方。
頂部封裝TPG可包括附著至第二印刷電路板170的至少一個第三晶片晶粒。在圖15至圖18中，為便於說明，示出四個第三晶片晶粒173、177、181、及185以及四個晶粒附著材料171、175、179、及183；然而，示例性實施例並非僅限於此。因此，包括於頂部封裝TPG中的第三晶片晶粒的數目及晶粒附著材料的數目可根據某些示例性實施例進行各種改變。
所述四個第三晶片晶粒173、177、181、及185中的每一者可為快閃型記憶體晶片晶粒（flash-based memory chip die）（例如，邏輯反及型（NOT AND，NAND）快閃晶片晶粒或邏輯反或型（NOT OR，NOR）快閃晶片晶粒）；然而，示例性實施例並非僅限於此。所述四個第三晶片晶粒173、177、181、及185中的每一者可經由導線187連接至彼此。此外，所述四個第三晶片晶粒173、177、181、及185中的每一者可經由導線187向第二印刷電路板170傳送訊號或自第二印刷電路板170接收訊號。
所述晶粒附著材料171、175、179、及183中的每一者可為膜或液體環氧黏合劑；然而，示例性實施例並非僅限於此。
頂部封裝TPG可更包括使用晶粒附著材料189-1附著至第二印刷電路板170的記憶體控制器189-2。當所述四個第三晶片晶粒173、177、181、及185中的每一者為反及型快閃晶片晶粒時，記憶體控制器189-2可為反及型快閃控制器。記憶體控制器189-2可經由導線189-3向第二印刷電路板170傳送訊號或自第二印刷電路板170接收訊號。
所述四個第三晶片晶粒173、177、181、及185、記憶體控制器189-2、以及導線187及導線189-3可使用保護性材料190進行模製。保護性材料190可藉由模製底部填充製程形成；然而，示例性實施例並非僅限於此。舉例而言，保護性材料190可為環氧模製化合物；然而，示例性實施例並非僅限於此。
圖17是當在A方向上觀察包括底部封裝100A-1及頂部封裝TPG的堆疊式封裝時的剖視圖。即，圖17是堆疊式封裝的正面剖視圖，且圖19是堆疊式封裝的側剖視圖。
圖21是示出圍繞底部封裝的相互面對的兩個側安置的第一堆疊連接焊球SJB1及第二堆疊連接焊球SJB2的實施例實例的平面圖。參照圖17及圖21，第一堆疊連接焊球SJB1及第二堆疊連接焊球SJB2可僅圍繞包括第一晶片晶粒130及第二晶片晶粒140的保護性材料150的四個側中相互面對的兩個側形成。即，第一堆疊連接焊球SJB1及第二堆疊連接焊球SJB2可形成為蝶形結構（butterfly structure）。
參照圖17，用於傳送供電電壓（例如，第三工作電壓VDD3及接地電壓VSS）以及對於包括於頂部封裝TPG中的第三晶片晶粒173、177、181、及185中的至少一者的運作及記憶體控制器189-2的運作而言所必需的訊號SIG的焊墊可經由第一堆疊連接焊球SJB1及第一印刷電路板110、藉由焊球112中的至少兩個焊球引出。
此外，只有用於傳送對於第三晶片晶粒173、177、181、及185中的至少一者的運作而言所必需的供電電壓（例如，工作電壓及接地電壓）的焊墊可經由第二堆疊連接焊球SJB2中的至少兩個連接焊球連接至第一印刷電路板110中的金屬線。工作電壓VDD、VDD1、或VDD2、以及接地電壓VSS可被供應至第一晶片晶粒130、第二晶片晶粒140、及第三晶片晶粒173、177、181、及185中的至少一者。
參照圖18，連接於底部封裝100A-1’與頂部封裝TPG之間的第二堆疊連接焊球SJB2可不傳送任何工作電壓或任何訊號。此時，第二堆疊連接焊球SJB2可被稱為處於電性浮動狀態。工作電壓VDD、VDD1、或VDD2、以及接地電壓VSS可經由對應焊球而僅被供應至第一晶片晶粒130及第二晶片晶粒140。
本說明書中的工作電壓VDD、VDD1、VDD2、及VDD3中的每一者籠統地指代一或多個工作電壓，且傳送工作電壓VDD、VDD1、VDD2、及VDD3中的每一者的焊球籠統地指代一或多個焊球。此外，傳送訊號SIG的焊球指代用於傳送多個訊號的焊球。
圖19及圖20是根據本發明概念的某些示例性實施例的包括底部封裝及頂部封裝的堆疊式封裝的剖視圖。
堆疊式封裝可包括參照圖1至圖14所述的包括第一晶片晶粒130及第二晶片晶粒140的底部封裝（100A至100J、100A-1、100B-1、100C-1、或100D-1，統稱「100」）、以及參照圖15所述的底部封裝TPG。根據某些示例性實施例，欲包括於堆疊式封裝中的底部封裝的結構可根據堆疊式封裝的設計規格進行各種改變。
參照圖19，只有用於傳送對於第三晶片晶粒173、177、181、及185中的至少一者的運作而言所必需的供電電壓（例如，工作電壓及接地電壓）的焊墊可藉由第二堆疊連接焊球SJB2中的至少兩個連接焊球連接至第一印刷電路板110中的金屬線。
第二堆疊連接焊球SJB2中的至少兩個連接焊球並不藉由第一印刷電路板110的焊球而獨立地引出。因此，工作電壓VDD、VDD1、或VDD2、以及接地電壓VSS可同時被供應至包括第一晶片晶粒130及第二晶片晶粒140的底部封裝100與頂部封裝TPG二者。
參照圖20，連接於底部封裝100與頂部封裝TPG之間的第二堆疊連接焊球SJB2可不傳送任何工作電壓及任何訊號。參照圖17至圖20，用於傳送對於包括於頂部封裝TPG中的第三晶片晶粒173、177、181、及185、以及記憶體控制器189-2的運作而言所必需的訊號SIG的所有第一焊墊可僅連接至第一堆疊連接焊球SJB1。
如圖17及圖19所示，用於傳送對於包括於頂部封裝TPG中的第三晶片晶粒173、177、181、及185、及/或記憶體控制器189-2的運作而言所必需的第三工作電壓VDD3及接地電壓VSS（例如，供電電壓）的第二焊墊可連接至第一堆疊連接焊球SJB1，且用於傳送對於包括於頂部封裝TPG中的第三晶片晶粒173、177、181、及185、及/或記憶體控制器189-2的運作而言所必需的供電電壓（VDD、VDD1、及VDD2、以及接地電壓VSS中的至少一者）的第三焊墊可連接至第二堆疊連接焊球SJB2。此時，第二焊墊的數目可多於第三焊墊的數目。
如圖18及圖20所示，用於傳送對於包括於頂部封裝TPG中的第三晶片晶粒173、177、181、及185、以及記憶體控制器189-2的運作而言所必需的第三工作電壓VDD3及接地電壓VSS（例如，供電電壓）的第二焊墊可僅連接至第一堆疊連接焊球SJB1，且第二堆疊連接焊球SJB2可維持電性浮動狀態。如圖21所示，第一堆疊連接焊球SJB1及第二堆疊連接焊球SJB2僅圍繞相互面對的兩個側安置。傳送至頂部封裝TPG的訊號SIG或傳送自頂部封裝TPG的訊號SIG可僅經由第一堆疊連接焊球SJB1進行傳送。
圖22及圖23是包括使用雷射鑽製技術暴露出的第一堆疊連接焊球及第二堆疊連接焊球的底部封裝的剖視圖。
在圖22中，對於底部封裝100-1而言，第一晶片晶粒130接收經由對應第一焊球輸入的供電電壓，且第二晶片晶粒140接收經由對應第二焊球輸入的供電電壓。在圖23中，對於底部封裝100-2而言，第一晶片晶粒130接收經由對應共用焊球輸入的供電電壓，且第二晶片晶粒140接收經由共用焊球輸入的供電電壓。
如圖22及圖23所示，在使用保護性材料150對底部封裝100-1及底部封裝100-2中的每一者中所包括的第一晶片晶粒130、第二晶片晶粒140、焊球131、及導線143進行模製之後，可使用雷射鑽製通路（laser drill via）技術而暴露出能夠連接至第一堆疊連接焊球SJB1及第二堆疊連接焊球SJB2的焊球145。因此，藉由雷射鑽製的通路而暴露出的焊球145可藉由紅外（infrared，IR）回流而電性連接至第一堆疊連接焊球SJB1及第二堆疊連接焊球SJB2。焊球145可形成於第一印刷電路板110的頂面上。
圖24是包括於根據本發明概念的某些示例性實施例的行動電腦裝置中的封裝總成的剖視圖。參照圖1至圖24，包括於行動電腦裝置中的封裝總成200可包括系統板210、包括底部封裝100及頂部封裝TPG的堆疊式封裝（或第一封裝）、電力管理積體電路（PMIC）205、及第二封裝230。舉例而言，系統板210可執行印刷電路板的功能。
本說明書中所闡述的行動電腦裝置可實施於行動電話、智慧型電話、平板個人電腦、行動網際網路裝置（mobile internet device，MID）、可穿戴式（wearable）裝置或可穿戴式電腦、膝上型電腦、物聯網（internet of things，IoT）裝置、或萬聯網（internet of everything，IoE）裝置中。
第一封裝可經由焊球112附著至系統板210。電力管理積體電路205可經由對應焊球附著至系統板210。第二封裝230可經由焊球231附著至系統板210。
自電力管理積體電路205輸出的第一供電電壓PW1可經由嵌置於系統板210中的第一電壓線、焊球112中的對應焊球、及第一印刷電路板110被供應至第一堆疊連接焊球SJB1中的至少一者。
自電力管理積體電路205輸出的第二供電電壓PW2可經由嵌置於系統板210中的第二電壓線及焊球231中的至少一者被供應至第二封裝230。自電力管理積體電路205輸出的第三供電電壓PW3可經由嵌置於系統板210中的第三電壓線及對應焊球被供應至無線晶片晶粒250中。
經由第一堆疊連接焊球SJB1中的對應連接焊球輸出的訊號可經由嵌置於系統板210中的訊號線SL1傳送至第二封裝230，且自第二封裝230輸出的訊號可經由嵌置於系統板210中的訊號線SL1傳送至第一堆疊連接焊球SJB1中的對應連接焊球。包括於第一封裝中的第一晶片晶粒130可經由嵌置於系統板210中的訊號線SL2向無線晶片晶粒250傳送訊號或自無線晶片晶粒250接收訊號。
第一封裝、電力管理積體電路205、第二封裝230、及無線晶片晶粒250中的每一者的接地線可連接至嵌置於系統板210中的接地線GND。第一封裝的接地線可連接至第一晶片晶粒130的接地線、第二晶片晶粒140的接地線、以及第三晶片晶粒173、177、181、及185中的每一者的接地線。
第二封裝230可包括經由焊球231連接至系統板210的第三印刷電路板233、經由互連件連接至第三印刷電路板233的第四晶片晶粒235、用於保護第四晶片晶粒235的保護性材料237、及連接第三印刷電路板233與第四印刷電路板241的互連件239。
互連件239可指代堆疊連接焊球。根據某些示例性實施例，第四晶片晶粒235可以倒裝晶片結構附著至第三印刷電路板233。根據某些示例性實施例，第四晶片晶粒235可使用晶粒附著材料附著至第三印刷電路板233。此時，第四晶片晶粒235可經由導線向第三印刷電路板233傳送訊號或自第三印刷電路板233接收訊號。根據某些示例性實施例，第四晶片晶粒235可指代應用處理器（application processor，AP）晶片晶粒或系統晶片（system on chip，SoC）；然而，示例性實施例並非僅限於此。
第二封裝230可更包括第五晶片晶粒243，且第五晶片晶粒243可附著於第四印刷電路板241上。根據某些示例性實施例，第五晶片晶粒243可指代揮發性記憶體（volatile memory）晶片晶粒或非揮發性記憶體（non-volatile memory）晶片晶粒。舉例而言，第五晶片晶粒243可實施於動態隨機存取記憶體晶片晶粒中。
根據某些示例性實施例，第五晶片晶粒243可以倒裝晶片結構附著至第四印刷電路板241。根據某些示例性實施例，第五晶片晶粒243可使用晶粒附著材料附著至第四印刷電路板241。此時，第五晶片晶粒243可經由導線向第四印刷電路板241傳送訊號或自第四印刷電路板241接收訊號。第二封裝230可更包括用於保護第五晶片晶粒243的保護性材料245。根據某些示例性實施例，第二封裝230可實施於堆疊式封裝中。
保護性材料237及保護性材料245中的每一者可實施於環氧模製化合物中。第三印刷電路板233與第四晶片晶粒235之間的空間可藉由毛細管底部填充（CUF）製程而被填充以底部填充材料。
圖25是包括圖24所示封裝總成的行動電腦裝置的方塊圖。參照圖24及圖25，行動電腦裝置300可包括底部封裝100、頂部封裝TPG、電力管理積體電路205、第四晶片晶粒235（例如，應用處理器235）、第五晶片晶粒243（例如，動態隨機存取記憶體（DRAM）243）、無線晶片晶粒250（例如，射頻積體電路（radio frequency integrated circuit，RFIC）250）、及顯示器310。電力管理積體電路205可供應對應供電電壓至底部封裝100、頂部封裝TPG、第四晶片晶粒235（例如，應用處理器235）、第五晶片晶粒243（例如，動態隨機存取記憶體243）、無線晶片晶粒250（例如，射頻積體電路250）、及顯示器310中的每一者。
底部封裝100的結構及頂部封裝TPG的結構如參照圖1至圖24所述。第四晶片晶粒235（例如，應用處理器235）可控制第五晶片晶粒243（例如，動態隨機存取記憶體243）的寫入操作及讀取操作。第四晶片晶粒235（例如，應用處理器235）可將欲在顯示器310中顯示的顯示資料傳送至顯示器310。
第四晶片晶粒235（例如，應用處理器235）可控制包括於底部封裝100中的第一晶片晶粒130及/或第二晶片晶粒140的運作。第四晶片晶粒235（例如，應用處理器235）可控制包括於頂部封裝TPG中的記憶體控制器189-2及/或第三晶片晶粒173、177、181、及185的運作。第四晶片晶粒235（例如，應用處理器235）可控制無線晶片晶粒250（例如，射頻積體電路250）的運作。
根據本發明概念的某些示例性實施例的堆疊式封裝可僅圍繞保護性材料的各個側中相互面對的兩個側安置用於堆疊底部封裝及頂部封裝的堆疊連接球，所述保護性材料包括附著至底部封裝的印刷電路板的晶片晶粒。根據本發明概念的某些示例性實施例的堆疊式封裝可將對於包括於頂部封裝中的至少一個晶片晶粒的運作而言所必需的所有焊墊僅連接至堆疊連接球中的第一堆疊連接球，藉此減小根據本發明概念的某些示例性實施例的堆疊式封裝的大小及高度。
儘管已參照本發明概念的某些示例性實施例具體示出並闡述了本發明概念的某些示例性實施例，然而此項技術中具有通常知識者應理解，在不背離由以下申請專利範圍界定的本發明概念的精神及範圍的條件下，可對其作出形式及細節上的各種改變。
應理解，本文所述示例性實施例應被視為僅具有闡述性意義而非用於限制目的。對示例性實施例內的特徵或態樣的闡述應通常被視作可供用於其他示例性實施例中的其他相似特徵或態樣。
11、12、13、14、16、17、21、22、23、24、26、27、31、32、33、34、36、37、41、42、43、44、46、47、51、52、53、54、56、57、112、131、131a、145、231‧‧‧焊球 100、100-1、100-2、100A、100B、100C、100D、100E、100F、100G、100H、100I、100J、100A-1、100A-1’、100B-1、100C-1、100D-1‧‧‧底部封裝 110‧‧‧第一印刷電路板 130‧‧‧第一晶片晶粒 133、133a‧‧‧底部填充材料 140‧‧‧第二晶片晶粒 141、171、175、179、183、189-1‧‧‧晶粒附著材料 143、187、189-3‧‧‧導線 150、190、237、245‧‧‧保護性材料 160、239‧‧‧互連件/堆疊連接焊球 170‧‧‧第二印刷電路板 173、177、181、185‧‧‧第三晶片晶粒 189-2‧‧‧記憶體控制器 200‧‧‧封裝總成 205‧‧‧電力管理積體電路（PMIC） 210‧‧‧系統板 230‧‧‧第二封裝 233‧‧‧第三印刷電路板 235‧‧‧第四晶片晶粒/應用處理器 241‧‧‧第四印刷電路板 243‧‧‧第五晶片晶粒/動態隨機存取記憶體（DRAM） 250‧‧‧無線晶片晶粒/射頻積體電路（RFIC） 300‧‧‧行動電腦裝置 310‧‧‧顯示器 A‧‧‧方向 GND‧‧‧接地線 MOLD‧‧‧模製底部填充材料 PW1‧‧‧第一供電電壓 PW2‧‧‧第二供電電壓 PW3‧‧‧第三供電電壓 SL、SL1、SL2‧‧‧訊號線 SIG‧‧‧訊號 SJB1‧‧‧第一堆疊連接焊球 SJB2‧‧‧第二堆疊連接焊球 TPG‧‧‧頂部封裝 VDD‧‧‧工作電壓 VDD1‧‧‧第一工作電壓 VDD2‧‧‧第二工作電壓 VDD3‧‧‧第三工作電壓 VSS‧‧‧接地電壓
結合附圖閱讀以下示例性實施例的詳細說明，以上及/或其他態樣及優點將變得更顯而易見且更易於理解，其中：
圖1至圖14是根據本發明概念的某些示例性實施例的底部封裝的剖視圖。
圖15至圖18是根據本發明概念的某些示例性實施例的包括底部封裝及頂部封裝的堆疊式封裝的剖視圖。
圖19至圖20是根據本發明概念的某些示例性實施例的包括底部封裝及頂部封裝的堆疊式封裝的剖視圖。
圖21是示出根據本發明概念的某些示例性實施例的圍繞底部封裝的相互面對的兩個側安置的第一堆疊連接焊球及第二堆疊連接焊球的實施例實例的平面圖。
圖22及圖23是包括使用雷射鑽製技術暴露出的第一堆疊連接焊球及第二堆疊連接焊球的底部封裝的剖視圖。
圖24是包括於根據本發明概念的某些示例性實施例的行動電腦裝置中的封裝總成（package assembly）的剖視圖。
圖25是包括圖24所示的封裝總成的行動電腦裝置的方塊圖。
100‧‧‧底部封裝
110‧‧‧第一印刷電路板
112‧‧‧焊球
190‧‧‧保護性材料
200‧‧‧封裝總成
205‧‧‧電力管理積體電路(PMIC)
210‧‧‧系統板
230‧‧‧第二封裝
231‧‧‧焊球
233‧‧‧第三印刷電路板
235‧‧‧第四晶片晶粒/應用處理器
237‧‧‧保護性材料
239‧‧‧互連件
241‧‧‧第四印刷電路板
243‧‧‧第五晶片晶粒/動態隨機存取記憶體(DRAM)
245‧‧‧保護性材料
250‧‧‧無線晶片晶粒/射頻積體電路(RFIC)
GND‧‧‧接地線
PW1‧‧‧第一供電電壓
PW2‧‧‧第二供電電壓
PW3‧‧‧第三供電電壓
SL1、SL2‧‧‧訊號線
SJB1‧‧‧第一堆疊連接焊球
SJB2‧‧‧第二堆疊連接焊球
TPG‧‧‧頂部封裝

Claims (25)

  1. 一種堆疊式封裝，包括： 第一印刷電路板； 底部封裝，包括附著至所述第一印刷電路板的第一晶片晶粒及第二晶片晶粒； 頂部封裝，包括第二印刷電路板及附著至所述第二印刷電路板的第三晶片晶粒，且上覆於所述底部封裝上；以及 第一堆疊連接焊球及第二堆疊連接焊球，電性連接於所述第一印刷電路板與所述第二印刷電路板之間，且僅圍繞所述底部封裝的各個側中相互面對的兩個側形成。
  2. 如申請專利範圍第1項所述的堆疊式封裝，其中所述第一晶片晶粒包括數據機晶片晶粒， 其中所述第二晶片晶粒包括動態隨機存取記憶體晶片晶粒或偽靜態隨機存取記憶體晶片晶粒，且 其中所述底部封裝包括系統級封裝。
  3. 如申請專利範圍第1項所述的堆疊式封裝，其中所述第一晶片晶粒經由第一凸塊以倒裝晶片結構附著至所述第一印刷電路板，且 其中所述第二晶片晶粒經由第二凸塊以所述倒裝晶片結構附著至所述第一印刷電路板。
  4. 如申請專利範圍第1項所述的堆疊式封裝，其中所述第一晶片晶粒經由第一凸塊以倒裝晶片結構附著至所述第一印刷電路板， 其中所述第二晶片晶粒經由第二凸塊以所述倒裝晶片結構附著至所述第一印刷電路板，且 其中所述第一晶片晶粒與所述第一印刷電路板之間的中空空間及所述第二晶片晶粒與所述第一印刷電路板之間的中空空間被填充以毛細管底部填充材料。
  5. 如申請專利範圍第1項所述的堆疊式封裝，其中所述第一晶片晶粒經由第一凸塊以倒裝晶片結構附著至所述第一印刷電路板， 其中所述第二晶片晶粒經由第二凸塊以所述倒裝晶片結構附著至所述第一印刷電路板，且 其中所述第一晶片晶粒與所述第一印刷電路板之間的中空空間及所述第二晶片晶粒與所述第一印刷電路板之間的中空空間、所述第一晶片晶粒、及所述第二晶片晶粒是使用模製底部填充材料進行囊封。
  6. 如申請專利範圍第1項所述的堆疊式封裝，其中所述第一晶片晶粒經由凸塊以倒裝晶片結構附著至所述第一印刷電路板， 其中所述第二晶片晶粒經由打線接合附著至所述第一印刷電路板，且 其中所述第一晶片晶粒與所述第一印刷電路板之間的中空空間、所述第一晶片晶粒、及所述第二晶片晶粒是使用模製底部填充材料進行囊封。
  7. 如申請專利範圍第1項所述的堆疊式封裝，其中所述頂部封裝更包括附著至所述第二印刷電路板的記憶體控制器， 其中所述記憶體控制器用以控制所述第三晶片晶粒的運作，且 其中所述第三晶片晶粒包括快閃型記憶體晶片晶粒。
  8. 如申請專利範圍第7項所述的堆疊式封裝，其中用於所述第三晶片晶粒及所述記憶體控制器的運作的所有訊號及所有供電電壓僅經由所述第一堆疊連接焊球進行傳送。
  9. 如申請專利範圍第8項所述的堆疊式封裝，其中所述第二堆疊連接焊球中的每一者均處於電性浮動狀態。
  10. 如申請專利範圍第7項所述的堆疊式封裝，其中用於所述第三晶片晶粒及所述記憶體控制器的運作的所有訊號、及用於所述第三晶片晶粒及所述記憶體控制器中的至少一者的運作的第一供電電壓的一部分經由所述第一堆疊連接焊球進行傳送，而用於所述第三晶片晶粒及所述記憶體控制器中的至少一者的運作的第二供電電壓的其餘部分則經由所述第二堆疊連接焊球進行傳送。
  11. 如申請專利範圍第10項所述的堆疊式封裝，其中經由附著至所述第一印刷電路板的底面的相應焊球而輸入的所述第二供電電壓經由所述第一印刷電路板而被傳送至所述底部封裝及所述第二堆疊連接焊球。
  12. 如申請專利範圍第1項所述的堆疊式封裝，其中所述第一晶片晶粒及所述第二晶片晶粒僅經由形成於所述第一印刷電路板中的訊號線而向彼此傳送訊號或自彼此接收訊號。
  13. 一種行動電腦裝置，包括： 系統板； 第一封裝，附著至所述系統板；以及 電力管理積體電路，附著至所述系統板且用以經由所述系統板供應第一供電電壓至所述第一封裝； 其中所述第一封裝包括： 第一印刷電路板； 底部封裝，包括附著至所述第一印刷電路板的第一晶片晶粒及第二晶片晶粒； 頂部封裝，包括第二印刷電路板及附著至所述第二印刷電路板的第三晶片晶粒，且上覆於所述底部封裝上；以及 第一堆疊連接焊球及第二堆疊連接焊球，電性連接於所述第一印刷電路板與所述第二印刷電路板之間，且僅圍繞所述底部封裝的各個側中相互面對的兩個側形成。
  14. 如申請專利範圍第13項所述的行動電腦裝置，其中所述第一晶片晶粒包括數據機晶片晶粒， 其中所述第二晶片晶粒包括動態隨機存取記憶體晶片晶粒或偽靜態隨機存取記憶體晶片晶粒，且 其中所述底部封裝包括系統級封裝。
  15. 如申請專利範圍第13項所述的行動電腦裝置，其中所述頂部封裝更包括附著至所述第二印刷電路板的記憶體控制器， 其中所述記憶體控制器用以控制所述第三晶片晶粒的運作，且 其中所述第三晶片晶粒包括快閃型記憶體晶片晶粒。
  16. 如申請專利範圍第15項所述的行動電腦裝置，其中用於所述第三晶片晶粒及所述記憶體控制器的運作的所有訊號、及用於所述第三晶片晶粒及所述記憶體控制器的運作的所有所述第一供電電壓僅經由所述第一堆疊連接焊球進行傳送。
  17. 如申請專利範圍第13項所述的行動電腦裝置，其中所述行動電腦裝置更包括附著至所述系統板的第二封裝且包括應用處理器晶片晶粒， 其中所述電力管理積體電路用以經由所述系統板供應第二供電電壓至所述應用處理器晶片晶粒， 其中所述系統板包括用以傳送在所述應用處理器晶片晶粒與所述第一封裝之間傳送或接收的訊號的訊號線，且 其中所述訊號線經由所述第一印刷電路板連接至所述第一堆疊連接焊球中的對應堆疊連接焊球。
  18. 如申請專利範圍第13項所述的行動電腦裝置，其中所述系統板包括接地線， 其中所述第一供電電壓包括工作電壓及接地電壓， 其中所述第一堆疊連接焊球中與所述接地電壓相關的連接焊球經由所述第一印刷電路板連接至所述接地線，且 其中所述工作電壓經由所述第一印刷電路板被供應至所述第一堆疊連接焊球中的對應堆疊連接焊球。
  19. 如申請專利範圍第15項所述的行動電腦裝置，其中用於所述第三晶片晶粒及所述記憶體控制器的運作的所有訊號、及所述第一供電電壓中用於所述第三晶片晶粒及所述記憶體控制器中的至少一者的運作的第二供電電壓僅經由所述第一堆疊連接焊球進行傳送， 其中所述第一供電電壓中用於所述第三晶片晶粒及所述記憶體控制器中的至少一者的運作的第三供電電壓僅經由所述第二堆疊連接焊球中的相應連接焊球進行傳送，且 其中經由附著至所述第一印刷電路板的底面的焊球而輸入的所述第三供電電壓經由所述第一印刷電路板傳送至所述相應連接焊球及所述底部封裝。
  20. 如申請專利範圍第19項所述的行動電腦裝置，其中所述行動電腦裝置更包括附著至所述系統板的第二封裝且包括應用處理器晶片晶粒， 其中所述電力管理積體電路用以經由所述系統板供應第四供電電壓至所述應用處理器晶片晶粒， 其中所述系統板包括用於傳送在所述應用處理器晶片晶粒與所述第一封裝之間傳送或接收的訊號的訊號線，且 其中所述訊號線經由所述第一印刷電路板連接至所述第一堆疊連接焊球中的對應堆疊連接焊球。
  21. 一種電子裝置，包括： 第一印刷電路板； 第一晶片晶粒，位於所述第一印刷電路板上； 第二晶片晶粒，位於所述第一印刷電路板上； 第二印刷電路板，位於所述第一晶片晶粒及所述第二晶片晶粒上； 至少一個第三晶片晶粒，位於所述第二印刷電路板上；以及 第一堆疊連接焊球及第二堆疊連接焊球，電性連接於所述第一印刷電路板與所述第二印刷電路板之間； 其中所述第一堆疊連接焊球位於所述第一晶片晶粒及所述第二晶片晶粒的與所述第二堆疊連接焊球相對的側上。
  22. 如申請專利範圍第21項所述的電子裝置，其中所述第二晶片晶粒位於所述第一晶片晶粒上。
  23. 如申請專利範圍第21項所述的電子裝置，其中所述第一晶片晶粒包括數據機晶片晶粒，且 其中所述第二晶片晶粒包括動態隨機存取記憶體晶片晶粒或偽靜態隨機存取記憶體晶片晶粒。
  24. 如申請專利範圍第21項所述的電子裝置，其中所述第一晶片晶粒經由第一凸塊以倒裝晶片結構附著至所述第一印刷電路板，且 其中所述第二晶片晶粒經由第二凸塊以所述倒裝晶片結構附著至所述第一印刷電路板。
  25. 如申請專利範圍第21項所述的電子裝置，其中所述第一晶片晶粒經由第一凸塊以倒裝晶片結構附著至所述第一印刷電路板， 其中所述第二晶片晶粒經由第二凸塊以所述倒裝晶片結構附著至所述第一印刷電路板，且 其中所述第一晶片晶粒與所述第一印刷電路板之間的中空空間及所述第二晶片晶粒與所述第一印刷電路板之間的中空空間被填充以毛細管底部填充材料。
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