TW202123411A - 用於積體電路封裝體之複合式橋接晶粒至晶粒互連件 - Google Patents
用於積體電路封裝體之複合式橋接晶粒至晶粒互連件 Download PDFInfo
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- TW202123411A TW202123411A TW109132609A TW109132609A TW202123411A TW 202123411 A TW202123411 A TW 202123411A TW 109132609 A TW109132609 A TW 109132609A TW 109132609 A TW109132609 A TW 109132609A TW 202123411 A TW202123411 A TW 202123411A
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Abstract
所揭示的實施例包括複合橋接晶粒至晶粒互連件,其位於一積體電路封裝體基體之晶粒側上,且接觸兩個IC晶粒、及於一模製材料中之一被動裝置,其中該模製材料亦接觸該兩個IC晶粒。
Description
本揭示內容係關於用於積體電路裝置封裝體的電力輸送。
多個積體電路晶片在封裝體內之整合,例如具有晶片之間的高互連密度之多晶片封裝體(MCP)積體電路裝置,具有電力輸送問題,諸如非所欲的電感迴路及阻抗峰值廓形。
於本發明的一個態樣中,揭示一種積體電路設備,其包含:一第一積體電路(IC)晶粒;一後續IC晶粒;在該第一IC晶粒及該後續IC晶粒之每一者上之封裝體-連接件接合墊;一複合橋接晶粒至晶粒互連件,其接觸在該第一IC晶粒及該後續IC晶粒上之複合橋接接合墊;一被動裝置,其位於該第一IC晶粒與該後續IC晶粒之間,且接觸該複合橋接晶粒至晶粒互連件;以及一模製材料,其接觸該第一IC晶粒及該後續IC晶粒、該被動裝置及該複合橋接晶粒至晶粒互連件。
所揭露的實施例包括組裝至積體電路(IC)封裝體基體的晶粒側之複合橋接晶粒至晶粒互連件,其中被動裝置係位於晶粒側安裝積體電路(IC)晶粒之間的模製層中。電力輸送網路(PDN)在諸如解耦電容器之被動裝置位於具有IC晶粒之模製層中且組裝至複合橋接晶粒至晶粒互連件的情況下,係被促進。此類被動裝置互連件藉由被動裝置之鄰近位置,有助於更快速的解耦電力輸送問題。在一實施例中,該電容器為一多層陶瓷電容器。在一實施例中,該電容器為一矽電容器。
球柵格陣列密度係針對輸入輸出(I/O)密度改變而被促進,其中處理了禁入區問題。被動裝置的位置,更靠近積體電路晶粒,係減輕積體電路封裝體基體佔地問題,以增加互連密度。
電氣效能之電源完整性藉由降低的封裝體電感迴路化達到。解耦電容器係直接耦接至供電(Vcc)軌及接地參考電壓(Vss),其降低電力輸送網路阻抗(ZPDN
)及顫動行為。
圖1A係根據若干實施例,一複合橋接晶粒至晶粒互連件於組裝期間的一橫截面正視圖101,其成為一積體電路封裝體的部分。相較於進一步所揭示之複合橋接晶粒至晶粒互連件之施用,反轉垂直定向。(參見例如圖1)。
根據一實施例,一第一積體電路(IC)晶粒10及一後續IC晶粒20係與一被動裝置112一起座置於一載體110上。該第一IC晶粒10包括一主動層及金屬化結構9,其包括以半導體材料製造之電晶體及其他主動裝置。類似地,該後續IC晶粒20包括一主動層及金屬化結構19。
圖1B為根據一實施例,圖1A中所描繪之總成101在進一步組裝之後的一橫截面正視圖102。一遮罩114,諸如一乾膜阻劑(DFR)114,已於第一及後續IC晶粒10及20的部分上被圖案化,且該DFR覆蓋更大的封裝體-連接件接合墊116及116'、並留下曝露的複合橋接接合墊118及118',以供進一步連接至該複合橋接晶粒至晶粒互連件132(見圖1H)。
圖1C為根據一實施例,圖1B中所描繪之總成102在進一步加工之後的一橫截面正視圖103。一模製層120填充至第一與後續IC晶粒10與20之間的空間內,使得被動裝置112位於該第一與後續IC晶粒10與20之間的模製層中。於打開接觸通道及形成互連通孔之製備中,模製層120亦覆蓋該等複合橋接接合墊118及118'。複合橋接接合墊118及118'係產生一較緊密的凸塊間距幾何結構,其由複合橋接晶粒至晶粒互連件實施例所促進。
圖1D為根據一實施例,圖1C中所描繪之總成103在進一步加工之後的一橫截面正視圖104。模製層120的圖案化已完成,以打開對複合橋接接合墊118及118'之接觸通道122。在諸如一解耦電容器120之電容器被動裝置120的狀況下,亦已完成模製層120之圖案化,以打開對各別的陽極及陰極接點之接觸通道124。在一實施例中,進行雷射鑽孔技術以打開接觸通道122及124。在一實施例中,進行光微影技術以打開接觸通道122及124,諸如透過一遮罩圖案化蝕刻。在一實施例中,使用雷射鑽孔以及光微影加工。
圖1E為根據一實施例,圖1D中所描繪之總成104在進一步加工之後的一橫截面正視圖105。複合橋接接觸件126及126',充填接觸通道122(見圖1D),諸如藉由一電鍍技術,接著藉由一指向蝕刻以自模製層120之上表面移除材料。類似地,被動裝置接觸件128係同時填充至接觸通道124中以接觸被動裝置112的電極。
在一實施例中,側向互連件130和130'(第一130和後續130')將該被動裝置112耦接至複合橋接接觸件126和126'。模製層120的圖案化已完成,以打開對複合橋接接合墊118及118'之接觸通道122。在一電容器被動裝置112的狀況下,亦完成模製層120的圖案化,以將該被動裝置112耦接至複合橋接接合墊118及118'。在一實施例中,跡線130及130'係同時形成具接點126及128,其藉由鍍敷該等接觸件及跡線,接著在模製材料120的上表面處遮罩一指向蝕刻,接著移除遮罩以現露出跡線130及130'。
圖1F為根據一實施例,圖1E中所描繪的結構在進一步加工之後的一積體電路設備106中之一複合橋接晶粒至晶粒互連件132的一橫截面正視圖。複合橋接晶粒至晶粒互連件132包括接觸件126及126'、被動裝置接觸件128及側向互連件130及130',以及繞過被動裝置112之傳導跡線134(晶粒至晶粒跡線134)。這些結構將被動裝置112耦接至複合橋接晶粒至晶粒互連件132,且以非限制性範例之形式,存在層間介電質136及138,其支撐例如傳導跡線134。
圖1G為根據一實施例,圖1F中所描繪的積體電路設備106中之複合橋接晶粒至晶粒互連件132於進一步結構加工後的一橫截面正視圖。IC設備107具有組裝至該複合橋接晶粒至晶粒互連件132之進一步結構。這些包括層間介電質層(ILD),諸如第一ILD 136及一後續ILD 138。進一步結構包括一傳導屏蔽140,其將座置於一積體電路封裝體基體的一晶粒側上。如所例示,該傳導屏蔽140伸出一佔用面積至該複合橋接接合墊118及118'上,且伸出至該被動裝置112上。傳導屏蔽140提供保護使免於在若干傳導跡線例如130、130'及134與一積體電路封裝體基體中任何接近的傳導跡線及通孔(參見例如圖1H中之IC封裝體基體142)之間有電磁耦接。
圖1H為根據一實施例,作為圖1G中所描繪的積體電路設備107之部分的複合橋接晶粒至晶粒互連件132於進一步結構加工後的一橫截面正視圖。
根據一具體例,一積體電路封裝體108包括IC晶粒10及20、耦接IC晶粒10及20的複合橋接晶粒至晶粒互連件132,以及該總成已倒置且為座置在一晶粒側143上的IC封裝體基體142上。複合橋接晶粒至晶粒互連件132曝露第一及後續IC晶粒10及20中之每一者上的封裝體-連接體接合墊116及116',且該複合橋接晶粒至晶粒互連件132接觸該等複合橋接接合墊118及118'。
較大的接合墊116及116'係分別基準連接至晶粒側電氣凸塊117及117',其可在IC封裝體晶粒側143上開始,抑或可在載體110的移除之後(見圖1G)、且在IC晶粒10及20以及複合橋接晶粒至晶粒互連件132的反轉之後,預先附接至各別較大的接合墊116及116'。在任何情況下,由晶粒側電氣凸塊117及117'生成的支座在晶粒側143回焊後,容納該複合橋接晶粒至晶粒互連件132的支座。
在一實施例中,為了剛性,IC封裝體基體142包括一核心層144。在該核心層144之上及之下,堆積層146包括有機層,其容納諸如封裝體通孔148及跡線150之互連件,以促進積體電路(IC)晶粒10及20與複合橋接晶粒至晶粒互連件132之互連,以及IC封裝體基體142的焊盤側(land side)141上之接腳引出連接至一電氣凸塊陣列152。在一實施例中,有機層146由環氧聚合物樹脂及矽石(silica)顆粒材料之複合物製造。在一實施例中,跡線150之寬度是在5 µm至40 µm之範圍。在一實施例中,該IC封裝體基體142為了封裝體z-高度(或厚度)縮減可排除核心層144。在任何情況下,複合橋接晶粒至晶粒互連件132消弭了對於一矽橋中介件的需要,其需要增加Z高度。此外,複合橋接晶粒至晶粒互連件132亦消除了對諸如一嵌入式多晶粒互連橋接件(EMIB)之矽橋接件的需要,其在IC晶粒10及20下方將佔據有用的晶粒下方佔地。
圖1為根據若干實施例,諸如包括圖1H中描繪的複合橋接晶粒至晶粒互連件132之IC封裝體的一積體電路封裝體設備100的一橫截面正視圖。包括第一及後續IC晶粒10及20、複合橋接晶粒至晶粒互連件132及被動裝置112的設備100,係座置於IC封裝體基體142之晶粒側143上。一底部填充物154已被流動至在IC晶粒10及20下方的晶粒側143上且亦接觸該複合橋接晶粒至晶粒互連件132。
在被動裝置112為一解耦電容器112的情況,藉由電容器112與其服務中之IC晶粒之間的縮短迴路電感而能夠有改良之電源完整性,其有助於未中斷之電流,對於直流(DC)負載線路效能及所得IC晶粒及包含其之任何運算系統的運算效能而言係為有用的。
在被動裝置112為一解耦電容器112的情況,其係耦接至電源(Vcc)及耦接至複合橋接晶粒至晶粒互連件132內之若干傳導跡線的接地(Vss)部分。複合橋接晶粒至晶粒互連件132內的其他傳導跡線及通孔被使用作為信號連接,諸如資料傳送連接。
如在一實施例中所例示,攜載IC晶粒10及20以及複合橋接晶粒至晶粒互連件132之IC封裝體基體142係被帶向一諸如主機板156或印刷佈線板156之板156。電氣接點係由一電氣凸塊陣列所製,其中一凸塊由參考數字152表示。在一實施例中,該板156具有一外部殼體157,其為該板156上之組件提供實體及電絕緣保護中之至少一者。舉例而言,外部殼體157係為該板156之整體部分,其為諸如通訊裝置之一手持式運算系統的部分。在一實施例中,外部殼體157係為該板156的一整體部分,其係諸如無人機之一行動運算平台之外部的一部分。
圖1K為根據若干實施例,圖1中所描繪之含有複合橋接晶粒至晶粒互連件之積體電路封裝體設備100的一頂部平面圖109。可自圖1K中之截面線A-A'取得描繪於圖1中之橫截面正視圖。項目1I及1J省略,且板156未被表示。晶粒側143支撐第一及後續IC晶粒10及20、以及有若干被動裝置於IC晶粒10與20間之模製材料中的複合橋接晶粒至晶粒互連件132。
在一實施例中,被動裝置112係為一第一電容器112,且一後續被動裝置158係為一耦接至複合橋接晶粒至晶粒互連件132中之後續電容器158。根據若干實施例,被動裝置112為模製材料120中的第一被動裝置的情況,進一步被動裝置包括後續被動裝置158、第三被動裝置160、第四被動裝置162及第五被動裝置164。該等若干被動裝置係在模製材料120中,且它們為複合橋接晶粒至晶粒互連件132的整體部分,使得該等若干被動裝置支撐IC晶粒10及20,而不需要嵌入IC封裝體基體142中。
在一實施例中,被動裝置為解耦電容器112、158、160、162及164。在一實施例中,電容器之子集合係獨立地耦接至不同的潛在供電軌,諸如用於第一電容器112及158之1.0伏特供電軌,以及用於電容器160、162及164之1.5 V供電軌。在一實施例中,該等電容器具有在20 µm至500 µm之範圍內的厚度。在一實施例中,所例示之至少一被動裝置為一電阻器。在一實施例中,所例示之至少一被動裝置為一電感器。
在一實施例中,一第一積體電路晶粒10係一中央處理單元,諸如由美國加州聖克拉拉的Intel公司所製造之一處理器。在一實施例中,該後續IC晶粒20是一圖形處理器20。在一實施例中,第一IC晶粒10以凸塊陣列117及117'(參見圖1)凸佈於晶粒側143上,其具有於一70微米(µm)至150 µm之範圍的凸塊間距幾何圖形。
圖1M係一複合橋接晶粒至晶粒互連件之與一積體電路封裝體及積體電路晶粒介接的一詳細區段部分。項目1L省略。該詳細區段可例如從描繪於圖1中的積體電路封裝體設備100取出。主動裝置及金屬化結構9及19進一步在各自的IC晶粒10及20處例示為各自的主動裝置8及18。
圖2為根據一實施例之帶有一複合橋接晶粒至晶粒互連件232之積體電路封裝體設備200的一橫截面正視圖。IC封裝體200係包括一第一及一後續IC晶粒10及20、該複合橋接晶粒至晶粒互連件232及位於IC晶粒10與20之間的一模製層220中的一被動裝置212,而IC晶粒10及20和該複合橋接晶粒至晶粒互連件232則座置於一IC封裝體基體242的一晶粒側243上。一底部填充物254已被流動至在IC晶粒10及20下方的晶粒側243上且亦接觸該複合橋接晶粒至晶粒互連件232。
在一實施例中,一焊盤側被動裝置266係「負鼠」形態安裝於IC封裝體基體242之焊盤側241上。該焊盤側被動裝置266係藉由實質上與焊盤側241垂直的垂直封裝體互連件(VPI)耦接至晶粒側243,並且進入複合橋接晶粒至晶粒互連件232。根據一實施例,與電容器212協同,焊盤側電容器266提供增強的電源供應雜訊抑制。在一實施例中,被動裝置212係一電阻器。
電氣凸塊217及217'協助將IC晶粒10及20耦接至IC封裝體基體242。電氣凸塊217及217'在晶粒側243上回焊之後產生支座,供有用地將複合橋接晶粒至晶粒互連件232座置於晶粒側243上。
在一實施例中,為了剛性,IC封裝體基體242包括一核心層244。在該核心層244之上及之下,堆積層246包括有機層,其容納諸如封裝體通孔248及跡線250之互連件,以促進積體電路(IC)晶粒10及20與複合橋接晶粒至晶粒互連件232之互連,以及IC封裝體基體242的焊盤側241上之接腳引出連接至一電氣凸塊陣列252。在一實施例中,有機層246由環氧聚合物樹脂及矽石顆粒材料之複合物製造。在一實施例中,跡線250之寬度是在5 µm至40 µm之範圍。在一實施例中,該IC封裝體基體242為了封裝體z-高度(或厚度)縮減可排除核心層244。
如在一實施例中所例示,攜載IC晶粒10及20以及複合橋接晶粒至晶粒互連件232之IC封裝體基體242係被帶向一諸如主機板256或印刷佈線板256之板256,且焊盤側被動裝置266具有從焊盤側241至晶粒側243並進入複合橋接晶粒至晶粒互連件232的一貫穿路徑。
在一實施例中,該板256具有一外部殼體257,其為該板256上之組件提供實體及電絕緣保護中之至少一者。
圖3為根據一實施例之帶有一複合橋接晶粒至晶粒互連件332之積體電路封裝體300的一橫截面正視圖。IC封裝體300係包括分別的一第一及一後續IC晶粒10及20、該複合橋接晶粒至晶粒互連件332及位於IC晶粒10與20之間的模製層320中的一上部被動裝置312,而IC晶粒10及20和該複合橋接晶粒至晶粒互連件332係座置於一IC封裝體基體342的一晶粒側343上。一底部填充物354已被流動至在IC晶粒10及20下方的晶粒側343上且亦接觸該複合橋接晶粒至晶粒互連件332。
在一實施例中,一內部被動裝置368係以致使第一、上部被動裝置312「跨坐」內部被動裝置368上、而被動裝置312及368的各者係與複合橋接晶粒至晶粒互連件332接觸的一方式被安裝。在任何情況下,藉由模製材料320,堆疊的被動組件312及368彼此隔離。
在一實施例中,第一IC晶粒10有與一主動層及金屬化結構29、諸如一記憶體晶粒的第一背側晶粒小晶片11連通的穿矽通孔(TSV)370。類似地,第一IC晶粒,後續背側晶粒小晶片12亦在第一IC晶粒10上,且通過一TSV耦接。在一實施例中,後續IC晶粒20有與一主動層及金屬化結構39、諸如一記憶體晶粒的第一背側晶粒小晶片21連通的穿矽通孔(TSV)372。類似地,一後續IC晶粒,後續背側晶粒小晶片22亦在後續IC晶粒20上,且通過一TSV耦接。
第一及後續電氣凸塊317及317'協助將各別的第一及後續IC晶粒10及20耦接至IC封裝體基體342。電氣凸塊317及317'在晶粒側343上回焊之後產生支座,供有用地將複合橋接晶粒至晶粒互連件332座置於晶粒側343上。
在一實施例中,為了剛性,IC封裝體基體342包括一核心層344。在該核心層344之上及之下,堆積層346包括有機層,其容納諸如封裝體通孔348及跡線350之互連件,以促進積體電路(IC)晶粒10及20與複合橋接晶粒至晶粒互連件332之互連,以及IC封裝體基體342焊盤側341上之接腳引出連接至一電氣凸塊陣列352。在一實施例中,有機層346由環氧聚合物樹脂及矽石顆粒材料之複合物製造。在一實施例中,跡線350之寬度是在5 µm至40 µm之範圍。在一實施例中,該IC封裝體基體342為了封裝體z-高度(或厚度)縮減可排除核心層344。
如一實施例中所例示,攜載IC晶粒10及20以及複合橋接晶粒至晶粒互連件332之IC封裝體基體342係被帶向諸如主機板356或印刷佈線板356之一板356。
在一實施例中,該板356具有一外部殼體357,其為該板356上之組件提供實體及電絕緣保護中之至少一者。
圖3A為根據若干實施例,為圖3中所描繪之含有複合橋接晶粒至晶粒互連件之積體電路封裝體設備300的一頂部平面圖301。可自圖3A中之截面線A-A'取得描繪於圖3中之橫截面正視圖。該板356未被表示。晶粒側343支撐第一及後續IC晶粒10及20、以及有若干被動裝置於IC晶粒10與20間之模製層320中的複合橋接晶粒至晶粒互連件332。
在該平面圖中,第一IC晶粒10攜載若干小晶片11、11'、12及12',且後續IC晶粒20攜載若干小晶片21、21'、22及22'。
在該平面圖中,內部被動裝置368(參見圖3)被第一、上部被動裝置312所遮。在一實施例中,被動裝置312係為一第一電容器312,且一後續被動裝置358係為一耦接至複合橋接晶粒至晶粒互連件332中之後續電容器358。在一實施例中,一後續內部被動裝置部署於該後續被動裝置358下方。根據若干實施例,被動裝置312為模製材料320中的第一被動裝置的情況,進一步被動裝置包括後續被動裝置358、第三被動裝置360、第四被動裝置362及第五被動裝置364。在一實施例中,至少兩個上部被動裝置係跨坐於一內部被動裝置上,諸如第一被動裝置312及後續被動裝置358係各跨坐於第一內部被動裝置368上,如圖3所描繪。在一實施例中,兩個以上的內部被動裝置如所例示係於若干上部被動裝置下方。在一實施例中,三個以上的內部被動裝置如所例示係於若干上部被動裝置下方。在一實施例中,四個以上的內部被動裝置如所例示係於若干上部被動裝置下方。
該等若干上部被動及內部被動裝置實施例係在模製材料320中,且為該複合橋接晶粒至晶粒互連件332的一整體部分,使得該等若干上部被動及內部被動裝置支撐IC晶粒10及20,而不需要嵌入IC封裝體基體342中。
在一實施例中,若干被動裝置為解耦電容器312、358、360、362及364,且若干內部被動裝置實施例亦為解耦電容器。在一實施例中,電容器之子集合係獨立地耦接至不同的潛在供電軌,諸如用於第一及後續電容器312、及358之1.0伏特供電軌,以及用於電容器360、362及364之1.5 V供電軌。在一實施例中,若干內部被動裝置具有相同的供電軌連接且用於一1.0 V供電軌。在一實施例中,若干內部被動裝置之子集合具有相同供電軌連接且用於一1.0 V供電軌,並且若干內部被動裝置之子集合具有用於一高於1.0 V使用或一低於1.0 V使用的一供電軌連接。在一實施例中,該等電容器具有在20 µm至500 µm之範圍內的厚度,且內部電容器具有的一寬度或長度係小於跨坐該內部電容器之電容器的寬度或長度。
在一實施例中,一第一積體電路晶粒10係一中央處理單元,諸如由美國加州聖克拉拉的Intel公司所製造之一處理器。在一實施例中,該後續IC晶粒20是一圖形處理器20。在一實施例中,第一IC晶粒10為支撐一個以上諸如晶粒11及11'之TSV連接記憶體晶粒的處理器晶粒。在一實施例中,後續IC晶粒20為支撐一個以上諸如晶粒21及21'之TSV連接記憶體晶粒的圖形處理器晶粒。
在一實施例中,第一IC晶粒10以凸塊陣列317及317'(參見圖3)凸佈於晶粒側343上,其具有於一70微米(µm)至150 µm之範圍的凸塊間距幾何圖形。
圖3B為根據若干實施例,為一含有複合橋接晶粒至晶粒互連件之積體電路封裝體設備的一頂部平面圖302,諸如圖3中所描繪之含有複合橋接晶粒至晶粒互連件之積體電路封裝體設備300。可自圖3B中之截面線B-B'取得描繪於圖3中之橫截面正視圖。該板356未被表示。在一實施例中,第一被動裝置312騎坐於一第一內部被動裝置368(見圖3)。在一實施例中,第一被動裝置312座置於第一下部被動裝置476頂上,諸如圖4所例示。
晶粒側343支撐第一及後續IC晶粒10及20、以及有若干被動裝置於IC晶粒10與20間之模製層320中的複合橋接晶粒至晶粒互連件332。另外,一第三IC晶粒30及一第四IC晶粒40亦在IC封裝體基體342之晶粒側343上。
在該平面圖中,第一IC晶粒10攜載若干小晶片11及12,且後續IC晶粒20攜載若干小晶片21及22。
在該平面圖中,第一、後續及第三被動裝置312、358及360係在模製材料320中,並且接觸複合橋接晶粒至晶粒互連件332。在一實施例中,一第四被動裝置362係於第一IC晶粒10與第四IC晶粒40之間的模製材料320中。在一實施例中,一第五被動裝置364係於第一IC晶粒10與第四IC晶粒40之間的模製材料320中,且亦相鄰於後續被動裝置358。在一實施例中,一第六被動裝置368係於後續IC晶粒20與第四IC晶粒40之間的模製材料320中,且亦相鄰於後續被動裝置358。在一實施例中,一第七被動裝置374係於後續IC晶粒20與第四IC晶粒40之間的模製材料320中,且亦相鄰於第六被動裝置368。
該等若干被動裝置實施例係在模製材料320中,且為複合橋接晶粒至晶粒互連件332的一整體部分,使得該等若干被動裝置支撐IC晶粒10、20、30及40,而不需要嵌入IC封裝體基體342中。
在一實施例中,被動裝置為解耦電容器312、358、360、362、364、368及374。在一實施例中,電容器之子集合係獨立地耦接至不同的潛在供電軌,諸如用於電容器312及358之1.0伏特供電軌,以及用於電容器360、362及364之1.5 V供電軌。在一實施例中,若干被動裝置具有相同的供電軌連接且用於一1.0 V供電軌。在一實施例中,該等若干被動裝置368及374之一子集合具有相同供電軌連接且用於一1.0 V供電軌,並且該等若干被動裝置368及374之一子集合具有用於一高於1.0 V使用抑或一低於1.0 V使用的一供電軌連接。在一實施例中,該等電容器具有在20 µm至500 µm之範圍的厚度。
在一實施例中,一第一積體電路晶粒10係一中央處理單元,諸如由美國加州聖克拉拉的Intel公司所製造之一處理器。在一實施例中,該後續IC晶粒20是一圖形處理器20。在一實施例中,第三IC晶粒30為一平台控制器集線器30。在一實施例中,第四IC晶粒40為一基頻處理器40。在一具體實施例中,若干晶粒10、20、30及40包括CPU、GPU、記憶體、場可規劃閘陣列(FPGA)及基頻處理器的功能。
在一實施例中,第一IC晶粒10為支撐超過一個諸如晶粒11及12之TSV連接記憶體晶粒的處理器晶粒。在一實施例中,後續IC晶粒20為支撐一個以上諸如晶粒21及22之TSV連接記憶體晶粒的圖形處理器晶粒。
在一實施例中,第一IC晶粒10以凸塊陣列317及317'(參見圖3)凸佈於晶粒側343上,具有於一70微米(µm)至150 µm之範圍的凸塊間距幾何圖形。
如所例示在一實施例中,複合橋接晶粒至晶粒互連件332為一晶粒至晶粒橋接件332,其中若干晶粒的排列係以諸如圖1G所描繪的晶粒至晶粒跡線134直接連接。例如,在非等效實施例中,複合橋接晶粒至晶粒互連件332在任何相鄰IC晶粒之間具有晶粒至晶粒跡線:IC晶粒10及20、IC晶粒10及30、IC晶粒10及40、IC晶粒20及40以及IC晶粒20及30。進一步且類似於圖1G中耦接IC晶粒10及20的晶粒至晶粒跡線134,在複合橋接晶粒至晶粒互連件332中的一晶粒至晶粒跡線耦接第三及第四IC晶粒30及40。
圖4為根據一實施例之帶有一複合橋接晶粒至晶粒互連件432之積體電路封裝體設備400的一橫截面正視圖。IC封裝體400係包括分別的一第一及一後續IC晶粒10及20、該複合橋接晶粒至晶粒互連件432及位於IC晶粒10與20之間的模製層420中的一上部被動裝置412,而IC晶粒10及20和該複合橋接晶粒至晶粒互連件 432係座置於一IC封裝體基體442的一晶粒側443上。一底部填充物454已被流動至在IC晶粒10及20下方的晶粒側443上且亦接觸該複合橋接晶粒至晶粒互連件432。
在一實施例中,一下部被動裝置476係以致使第一、上部被動裝置412係在該下部被動裝置476上方且之上(呈例如直接焊接接觸)、而該下部被動裝置476係接觸複合橋接晶粒至晶粒互連件432的一方式被安裝。
在一實施例中,第一IC晶粒10有與一主動層及金屬化結構49、諸如一記憶體晶粒的第一背側晶粒小晶片11連通的穿矽通孔(TSV)470。類似地,第一IC晶粒,後續背側晶粒小晶片12亦在第一IC晶粒10上,且通過一TSV耦接。在一實施例中,後續IC晶粒20有與一主動層及金屬化結構49、諸如一記憶體晶粒的第一背側晶粒小晶片21連通的穿矽通孔(TSV)472。類似地,一後續IC晶粒,後續背側晶粒小晶片22亦在第一IC晶粒20上,且通過一TSV耦接。
電氣凸塊417及417'協助將IC晶粒10及20耦接至IC封裝體基體442。電氣凸塊417及417'在晶粒側443上回焊之後產生支座,供有用地將複合橋接晶粒至晶粒互連件432座置於晶粒側443上。
在一實施例中,為了剛性,IC封裝體基體442包括一核心層444。在該核心層444之上及之下,堆積層446包括有機層,其容納諸如封裝體通孔448及跡線450之互連件,以促進積體電路(IC)晶粒10及20與複合橋接晶粒至晶粒互連件432之互連,以及IC封裝體基體442焊盤側441上之接腳引出連接至一電氣凸塊陣列452。在一實施例中,有機層446由環氧聚合物樹脂及矽石顆粒材料之複合物製造。在一實施例中,跡線550之寬度是在5 µm至40 µm之範圍。在一實施例中,該IC封裝體基體442為了封裝體z-高度(或厚度)縮減可排除核心層444。
如一實施例中所例示,攜載IC晶粒10及20以及複合橋接晶粒至晶粒互連件432之IC封裝體基體442係被帶向諸如主機板456或印刷佈線板456之一板456。
在一實施例中,該板456具有一外部殼體457,其為該板456上之組件提供實體及電絕緣保護中之至少一者。
現在可理解的是,如圖4所描繪的具複合橋接晶粒至晶粒互連件432之積體電路封裝體400亦可依據圖3A來看,而以上部及下部被動裝置,例如圖4中的412及476,分別取代圖3及3A中的第一上部及內部被動裝置312及368。因此,圖3及圖3A中針對若干電容器所述及的若干不同電壓額定值可映射至圖4中之等效電容器,並限定成若電容器412及476直接接觸則對其等予以串聯額定。
現在可理解的是,如圖4所描繪具複合橋接晶粒至晶粒互連件432之積體電路封裝體400亦可依據圖3B來看,而以上部及下部被動裝置,例如圖4中的412及476,取代圖3B中具堆疊上部及下部電容器之該等若干電容器312、358及360。因此,圖3B中針對若干電容器所述的若干不同的電壓額定值可映射至圖4中之等效電容器,並限定成當電容器412及476直接接觸則對該等電容器予以串聯額定。
圖5係依據若干實施例之用以將一複合橋接晶粒至晶粒互連件組裝至一積體電路封裝體設備之一程序流程圖。
在步驟510,該製程包括將一複合橋接晶粒至晶粒互連件組裝至一第一IC晶粒及一後續IC晶粒上,且組裝至在該第一與後續IC晶粒之間的被動裝置。在一非限制性範例實施例中,圖1G中的第一及後續IC晶粒10及20、以及複合橋接晶粒至晶粒互連件132,已藉由模製層120的使用而與被動裝置112一起組裝。
在步驟520,該程序包括將該複合橋接晶粒至晶粒互連件組裝至一積體電路封裝體基體。在一非限制性範例實施例中,包括IC晶粒10及20之積體電路裝置設備、複合橋接晶粒至晶粒互連件132及被動裝置112係座置於IC封裝體基體142之一晶粒側143上的凸塊117及117'上,如圖1H中所例示。現在可理解的是,圖1、圖2、圖3、圖3A、圖3B及圖4中描繪之具有其等揭示之排列的IC裝置封裝體中之任一者,可組裝至IC封裝體基體於晶粒側處。
在步驟530,該程序包括將該IC封裝體與該複合橋接晶粒至晶粒互連件組裝至一運算系統。在一非限制性範例實施例中,使用圖6所描繪之運算系統600。
圖6被含括以展示用於所揭示實施例之一較高位準裝置應用的一範例。複合橋接晶粒至晶粒互連件實施例可見於一運算系統的若干部份。在一實施例中,該複合橋接晶粒至晶粒互連實施例可為一通訊設備的一部分,諸如一隨附於一蜂巢式通訊塔。在一實施例中,一運算系統600包括但不限於一桌上型電腦。在一實施例中,一運算系統600包括但不限於一膝上型電腦。在一實施例中,一運算系統600包括但不限於一平板。在一實施例中,一運算系統600包括但不限於一筆記型電腦。在一實施例中,一運算系統600包括但不限於一個人數位助理(PDA)。在一實施例中,一運算系統600包括但不限於一伺服器。在一實施例中,一運算系統600包括但不限於一工作站。在一實施例中,運算系統600包括但不限於一蜂巢式電話。在一實施例中,運算系統600包括但不限於一行動運算裝置。在一實施例中,運算系統600包括但不限於一智慧型電話。在一實施例中,系統600包括但不限於一網際網路用具。其他類型的運算裝置係可組配有包括複合橋接晶粒至晶粒互連件實施例之微電子裝置。
在一或多項實施例中,處理器610具有一或多個處理核心612及612N,其中612N代表處理器610內的第N個處理器核心,其中N為一正整數。在一實施例中,電子裝置系統600使用包括610及605之多個處理器的一複合橋接晶粒至晶粒互連件實施例,其中處理器605具有與處理器610類似或相同的邏輯。在一實施例中,處理核心612包括但不限於有用以擷取指令之預取邏輯、用以解碼該等指令之解碼邏輯、用以執行指令之執行邏輯以及類似者。在一實施例中,處理器610具有一快取記憶體616以在系統600中快取用於一積體電路封裝體基體上之複合橋接晶粒至晶粒互連元件的指令及資料中之至少一者。快取記憶體616可組織成包括有快取記憶體之一或多層級的一階層式結構。
一實施例中,處理器610包括一記憶體控制器614,該記憶體控制器可操作以進行使該處理器610能夠存取記憶體630且與之通訊的功能,該記憶體630包括一依電性記憶體632及一非依電性記憶體634中之至少一者。一實施例中,處理器610與記憶體630及晶片組620耦接。一實施例中,晶片組620是例如圖1、2、3、3A、3B及4中所描繪之一複合橋接晶粒至晶粒互連件實施例之部份。
處理器610亦可耦接至一無線天線678以與組配來傳送無線信號及接收無線信號至少一者之任何裝置通訊。在一實施例中,無線天線介面678根據但不限於IEEE 802.11標準及其相關家族、Home Plug AV(HPAV)、超寬頻帶(UWB)、藍牙、WiMax或任何形式之無線通訊協定來操作。
在一實施例中,依電性記憶體632包括,但不限於同步動態隨機存取記憶體(SDRAM)、動態隨機存取記憶體(DRAM)、RAMBUS動態隨機存取記憶體(RDRAM)、及/或任何其他類型的隨機存取記憶體裝置。非依電性記憶體634包括但不限於快閃記憶體、相變記憶體(PCM)、唯讀記憶體(ROM)、電可抹除可規劃唯讀記憶體(EEPROM)或任何其他類型之非依電性記憶體裝置。
記憶體630儲存要由處理器610執行的信息和指令。在一實施例中,記憶體630在處理器610正在執行指令時亦可儲存暫時變數或其他中間資訊。在所例示的實施例中,晶片組620經由點對點(PtP或P-P)介面617及622與處理器610連接。這些PtP實施例之任一者可使用如本揭示內容中所述之複合橋接晶粒至晶粒互連件實施例來達成。在一系統600中,晶片組620使處理器610能夠連接至一複合橋接晶粒至晶粒互連件實施例中之其他元件。在一實施例中,介面617及622根據諸如Intel®快速通道互連(QuickPath Interconnect, QPI)之一PtP通訊協定或類似者來操作。在其他實施例中,可使用不同的互連件。
在一實施例中,晶片組620可操作來與處理器610、605N、顯示器裝置640、及其他裝置672、676、674、660、662、664、666、677等通訊。晶片組620亦可耦接至一無線天線678以與組配來進行傳送無線信號及接收無線信號至少一者之任何裝置通訊。
晶片組620經由介面626連接至顯示器裝置640。顯示器640可為例如液晶顯示器(LCD)、電漿顯示器、陰極射線管(CRT)顯示器、或視覺顯示裝置的任何其他形式。在一實施例中,處理器610及晶片組620於一系統中被合併成一複合橋接晶粒至晶粒互連件實施例。另外,晶片組620連接至將各種元件674、660、662、664及666互連之一或多個匯流排650及655。匯流排650及655可經由諸如至少一複合橋接晶粒至晶粒互連件實施例的一匯流排橋接件672互連在一起。在一具體例中,晶片組620,經由介面624,與非依電性記憶體660、(多個)大容量儲存裝置662、鍵盤/滑鼠664、網路介面666、智慧型TV 676、以及消費者電子裝置677等耦接。
在一實施例中,大容量儲存裝置662包括,但不限於一固態驅動機、一硬碟驅動機、一通用串列匯流排快閃記憶體驅動機、或任何其他形式之電腦資料儲存媒體。在一實施例中,網路介面666乃藉由任何類型之眾所周知的網路介面標準來實施,包括但不限於一乙太網路介面、一通用串列匯流排(USB)介面、一週邊組件互連(PCI)快捷介面、一無線介面及/或任何其他合適類型的介面。在一實施例中,無線介面根據但不限於IEEE 802.11標準及其相關家族、Home Plug AV(HPAV)、超寬頻帶(UWB)、藍牙、WiMax或任何形式之無線通訊協定來操作。
雖然圖6所示模組被描繪為一系統600中之複合橋接晶粒至晶粒互連件實施例內分開的區塊,由此等區塊中之一些所執行的功能可整合於一單一半導體電路內,或者可使用兩個或兩個以上分開的積體電路來實施。舉例來說,雖然快取記憶體616被描繪為處理器610內的一單獨區塊,但快取記憶體616(或616之選定態樣)可併入至處理器核心612中。
為了例示本文中所揭示之複合橋接晶粒至晶粒互連件IC封裝體實施例及方法,本文提供範例之非限制性列表:
範例1為一種積體電路設備,其包含:一第一積體電路(IC)晶粒;一後續IC晶粒;一複合橋接晶粒至晶粒互連件,其接觸該第一及後續IC晶粒之每一者上的複合橋接接合墊,且其中該複合橋接晶粒至晶粒互連件曝露在該第一及後續IC晶粒中之每一者上的封裝體-連接件接合墊;一被動裝置,其於該第一與後續IC晶粒之間,且接觸該複合橋接晶粒至晶粒互連件;以及一模製材料,其接觸該第一及後續IC晶粒、該被動裝置及該複合橋接晶粒至晶粒互連件。
範例2中,範例1之標的任擇地包括在該複合橋接晶粒至晶粒互連件中之一第一側向互連件,其耦接至該第一IC晶粒及該被動裝置;以及在該複合橋接晶粒至晶粒互連件中之一後續側向互連件,其耦接至該後續IC晶粒及該被動裝置。
範例3中,範例1-2中任一或多者之標的任擇地包括一晶粒至晶粒跡線於該複合橋接晶粒至晶粒互連件中,其繞過該被動裝置且耦接第一及後續IC晶粒。
範例4中,範例1-3中任一或多者之標的任擇地包括於該複合橋接晶粒至晶粒互連件中,其中該傳導屏蔽伸出一佔用面積至該複合橋接接合墊上,且伸出至該被動裝置上。
範例5中,範例1-4中任一或多者之標的任擇地包括:在該複合橋接晶粒至晶粒互連件中之一第一側向互連件,其耦接至該第一IC晶粒及該被動裝置;在該複合橋接晶粒至晶粒互連件中之一後續側向互連件,其耦接至該後續IC晶粒及該被動裝置;以及一晶粒至晶粒線於該複合橋接晶粒至晶粒互連件中,其繞過該被動裝置且耦接該第一及後續IC晶粒。
範例6中,範例1-5中任一或多者之標的任擇地包括在該複合橋接晶粒至晶粒互連件中之一第一側向互連件,其耦接至該第一IC晶粒及該被動裝置;在該複合橋接晶粒至晶粒互連件中之一後續側向互連件,其耦接至該後續IC晶粒及該被動裝置;以及一傳導屏蔽於該複合橋接晶粒至晶粒互連件中,其中該傳導屏蔽伸出一佔用面積至該複合橋接接合墊上,且至該被動裝置上。
範例7中,範例1-6中任一或多者之標的任擇地包括在該複合橋接晶粒至晶粒互連件中之一第一側向互連件,其耦接至該第一IC晶粒及該被動裝置;在該複合橋接晶粒至晶粒互連件中之一後續側向互連件,其耦接至該後續IC晶粒及該被動裝置;一晶粒至晶粒線於該複合橋接晶粒至晶粒互連件中,其繞過該被動裝置且耦接該第一及後續IC晶粒;以及一傳導屏蔽於該複合橋接晶粒至晶粒互連件中,其中該傳導屏蔽伸出一佔用面積至該複合橋接接合墊上,且至該被動裝置上。
範例8中,範例1-7中任一或多者之標的任擇地包括一積體電路封裝體基體;以及封裝體連接電氣凸塊,其接觸該等封裝體連接銲墊,其中該等電氣凸塊是在該積體電路封裝體基體上位在一晶粒側。
範例9中,範例1-8中任一或多者之標的任擇地包括一積體電路封裝體基體;封裝體-連接件電氣凸塊,其接觸該等封裝體-連接件接合墊,其中該等電氣凸塊係在該積體電路封裝體基體上、在一晶粒側;以及其中該複合橋接晶粒至晶粒互連件亦在該晶粒側上。
範例10中,範例1-9中任一或多者之標的任擇地包括其中該被動裝置為一嵌入式被動裝置,進一步包括:一積體電路封裝體基體,包括一晶粒側及一焊盤側;封裝體-連接件電氣凸塊,其接觸該等封裝體-連接件接合墊,其中該等電氣凸塊是在該積體電路封裝體基體上、位在該晶粒側;以及在該焊盤側之一底部被動裝置,其中該底部被動裝置係耦接至該第一及後續IC晶粒的至少一者。
範例11為一種積體電路封裝體設備,其包含:一積體電路封裝體基體,包括一晶粒側及一焊盤側;該晶粒側上的一第一積體電路(IC)晶粒;該晶粒側上的一後續IC晶粒;一複合橋接晶粒至晶粒互連件,其接觸在該第一及後續IC晶粒上之每一者上的複合橋接接合墊,且其中該複合橋接晶粒至晶粒互連件曝露在該第一及後續IC晶粒中之每一者上的封裝體-連接件接合墊;封裝體-連接件接合墊,其接觸在該晶粒側的該第一及後續IC晶粒;一被動裝置,位於該第一與後續IC晶粒之間,且耦接至該複合橋接晶粒至晶粒互連件;以及一模製材料,其接觸該第一及後續IC晶粒、該被動裝置及該複合橋接晶粒至晶粒互連件。
範例12中,範例11之標的任擇地包括其中,該被動裝置接觸該複合橋接晶粒至晶粒互連件。
範例13中,範例11-12中任一者或多者之標的任擇地包括:在該第一IC晶粒上的至少一小晶片,且其藉由一穿矽通孔耦接至該第一IC晶粒。
範例14中,範例11-13中任一或多者之標的任擇地包括在該第一IC晶粒上的至少一小晶片,且其藉由一穿矽通孔耦接至該第一IC晶粒;以及在該後續IC晶粒上的至少一小晶片,且其藉由一穿矽通孔耦接至該後續IC晶粒。
範例15中,範例11至14中任一或多者之標的任擇地包括其中該被動裝置為一第一被動裝置,其進一步包括一後續被動裝置,位於該第一與後續IC晶粒之間且於該模製材料中,其中該後續被動裝置接觸該複合橋接晶粒至晶粒互連件。
範例16中,範例11至15中任一或多者之標的任擇地包括其中該被動裝置為一第一被動裝置,其進一步包括一第一內部被動裝置,位於該第一被動裝置下方且於該模製材料中,其中該第一內部被動裝置接觸該複合橋接晶粒至晶粒互連件。
範例17中,範例11-16中任一或多者之標的任擇地包括其中該被動裝置為一第一被動裝置,進一步包括:一第一內部被動裝置,位於該第一被動裝置下方且於該模製材料中,其中該第一內部被動裝置接觸該複合橋接晶粒至晶粒互連件;一後續被動裝置,位於該第一與後續IC晶粒之間且於該模製材料中,其中該後續被動裝置接觸該複合橋接晶粒至晶粒互連件;以及一後續內部被動裝置,位於該後續被動裝置下方且於該模鑄材料中,其中該後續內部被動裝置接觸該複合橋接晶粒至晶粒互連件。
範例18中,範例11-17中任一或多者之標的任擇地包括其中該被動裝置為一第一被動裝置,進一步包括:一後續被動裝置,位於該第一與後續IC晶粒之間且於該模製材料中,其中該後續被動裝置接觸該複合橋接晶粒至晶粒互連件;一第三IC晶粒,位在該晶粒側上、鄰近該第一及後續IC晶粒中之每一者;一第四IC晶粒,位在該晶粒側上、鄰近該第一及後續IC晶粒中之每一者;以及一第三被動裝置,位於該第一與第四IC晶粒之間且於該模製材料中,其中該第三被動裝置接觸該複合橋接晶粒至晶粒互連件。
範例19中,範例11至18中任一或多者之標的任擇地包括其中該被動裝置為一第一上部被動裝置,其進一步包括一第一下部被動裝置,位於該第一上部被動裝置下方並與之接觸、且於該模製材料中,其中該第一下部被動裝置接觸該複合橋接晶粒至晶粒互連件。
範例20中,範例11-19中任一或多者之標的任擇地包括耦接至該焊盤側之一印刷佈線板;以及耦接至該印刷佈線板的一晶片組。
範例21中,範例20之標的任擇地包括其中該印刷佈線板包括一外部殼體,該外部殼體為一介電材料,且其中該外部殼體為擇自於一行動運算系統及一無人機的一裝置的外部之至少部分。
範例22為一種組裝一積體電路設備之方法,其包含:將一複合橋接晶粒至晶粒互連件組裝於一第一積體電路晶粒、一被動裝置及一後續積體電路晶粒上,其中該被動裝置係於該第一與後續積體電路晶粒之間;以及使一模製材料接觸該複合橋接晶粒至晶粒互連件、該第一及後續積體電路晶粒、以及接觸該被動裝置。
範例23中,範例22之標的任擇地包括將該複合橋接晶粒至晶粒互連件組裝至一積體電路封裝體基體、於一晶粒側上,其中該第一及後續積體電路晶粒上之電氣凸塊接觸該晶粒側;以及底部填充該第一及後續積體電路晶粒。
範例24中,範例22-23中任一或多者之標的任擇地包括將該複合橋接晶粒至晶粒互連件組裝至一積體電路封裝體基體、於一晶粒側上,其中該第一及後續積體電路晶粒上之電氣凸塊接觸該晶粒側;底部填充該第一及後續積體電路晶粒;以及將該積體電路封裝體基體在一焊盤側組裝至一印刷佈線板。
上述詳細說明包括提及隨附圖式,其形成詳細說明之一部份。該等圖式藉由說明展示出本發明可以之實現的特定實施例。這些實施例在本文中亦稱為「範例」。此等範例可另包括所示或所述之元件以外的元件。然而,本案發明人亦想到僅有所示或所述之彼等元件被提供的範例。此外,就一特定範例(或其一或多個態樣)、或就本文中所示或所述之其他範例(或其一或多個態樣)而言,本案發明人亦想到使用所示或所述之彼等元件之任何組合或排列(或其一或多個態樣)的範例。
本文件與任何以參考方式併入的文件之間若有使用上不一致的狀況,以本文件中的使用狀況為主。
在此文件中,用語「一」的使用係如專利文件中常見者,用以包括一個或多於一個,獨立於「至少一個」或「一個或多個」之任何其他示例或使用。在此文件中,除非另有指明,否則用語「或」用來指稱一非排除性,或者諸如「A或B」包括「A但非B」、「B但非A」、以及「A及B」。在此文件中,用語「inclusing(包括)」及「in which(其中)」被用為各別用詞「comprising(包含)」及「wherein(其中)」之通俗英語等效詞。而且,下列申請專利範圍中,用語「包括」及「包含」為開放式詞尾,亦即,一系統、裝置、物件、組成物、配方、或製程,其另包括一請求項中此一用語之後所列舉者之外的元件,仍然會被認定是落在申請專利範圍範疇之內。此外,下列申請專利範圍中,「第一」、「第二」、及「第三」等用語僅係作為標示用,而非意欲對其等物品賦加數值要求。
本文所述方法範例係可至少部份地以機器或電腦實行。一些範例可包括以指令編碼的電腦可讀媒體或機器可讀媒體,該等指令可操作來組配一電氣裝置以進行如以上範例中所述之方法。此等方法之實行方案可包括諸如微碼、匯編語言碼(assembly language code)、高階語言碼、或類似者之碼。此等碼可包括用於進行各種方法之電腦可讀指令。碼可形成電腦程式產品之部分。再者,在一範例中,此符碼可諸如在執行期間或於其他時間,以有形方式儲存於一或多個依電性、非暫時性、或非依電性電腦可讀媒體上。這些有形的電腦可讀媒體之範例可包括但不限於硬碟片、可移除式磁碟片、可移除式光碟片(例如,光碟片及數位視訊碟片)、磁性匣帶、記憶體卡或記憶體棒、隨機存取記憶體(RAM)、唯讀記憶體(ROM)及類似者。
以上描述係意圖為說明性,而非限制性。例如,以上所述範例(或其一或多個態樣)可彼此組合而使用。諸如一熟悉該技藝者可在閱覽以上描述之後使用其他實施例。提供「摘要」以符合37 C.F.R. §1.72(b)的要求,容許讀者快速獲知本技術揭露內容的性質。應了解的是,摘要係在其不會被用來詮釋或限制申請專利範圍之範疇或意義的理解之下呈送。此外,在以上詳細說明中,各種特徵可被集合在一起以順應本揭露內容。不應將此情況解釋為意表一未主張之揭示特徵係為任何請求項所必需的。反之,發明主體可呈現為少於特定揭示實施例之全部特徵。因此,以下申請專利範圍藉此係併入本案實施方式乙節作為範例或實施例,各請求項本身代表一各別的實施例,而且列入考量的是,此等實施例可以各種組合或排列彼此組合。所揭示實施例之範疇的判定應參考隨附之申請專利範圍,以及此等申請專利範圍有權主張之等效物的完整範圍。
8,18:主動裝置
9,19,29,39,49:主動層及金屬化結構
10:(第一)積體電路(IC)晶粒
11,21:(第一背側晶粒)小晶片;晶粒
11',12',21',22':小晶片
12,22:(後續背側晶粒)小晶片;晶粒
20:(後續)IC晶粒;圖形處理器
30:第三IC晶粒;平台控制器集線器
40:第四IC晶粒;基頻處理器
100,200,300,400:積體電路(IC)封裝體設備;IC封裝體
101,102,103,104,105:總成的橫截面正視圖;總成
106,107:積體電路(IC)設備
108:積體電路封裝體
109,302:頂部平面圖
110:載體
112:(電容器)被動裝置;(解耦/第一)電容器
114:遮罩;乾膜阻劑(DFR)
116,116':(封裝體-連接件)接合墊
117,117':(晶粒側)電氣凸塊;凸塊陣列;凸塊
118,118':複合橋接接合墊
120,220,320:模製層;模製材料
122,124:接觸通道
126,126':複合橋接接觸件;接點
128:被動裝置接觸件;接點
130,130':側向互連件;(傳導)跡線
132,232,432:複合橋接晶粒至晶粒互連件
134:晶粒至晶粒跡線
136:(第一)層間介電質層(ILD)
138:(後續)ILD
140:傳導屏蔽
141,241,341,441:焊盤側
142,242,342,442:IC封裝體基體
143,243,343,443:晶粒側
144,244,344,444:核心層
146,246,346,446:堆積層;有機層
148,248,348,448:封裝體通孔
150,250,350,450,550:跡線
152,252,352,452:電氣凸塊陣列;凸塊
154,254,354,454:底部填充物
156,256,356,456:主機板;印刷佈線板;板
157,257,357,457:外部殼體
158,358:後續被動裝置;(後續/解耦)電容器
160,360:第三被動裝置;(第三/解耦)電容器
162,362:第四被動裝置;(第四/解耦)電容器
164,364:第五被動裝置;(第五/解耦)電容器
212:被動裝置;電容器
266:焊盤側被動裝置;焊盤側電容器
217,217',417,417':電氣凸塊
312:(第一、上部)被動裝置;(第一/解耦)電容器;被動組件
317:(第一)電氣凸塊;凸塊陣列
317':(後續)電氣凸塊;凸塊陣列
368:(內部/第一內部/第六)被動裝置;被動組件;解耦電容器
370,470,472:穿矽通孔(TSV)
374:(第七)被動裝置;解耦電容器
332:晶粒至晶粒橋接件;(複合橋接)晶粒至晶粒互連件
476:(第一)下部被動裝置;電容器
420:模製層
412:(第一、)上部被動裝置;電容器
510,520,530:步驟
600:(運算)系統
605,610:處理器
612:處理器核心
612N:處理器核心N
614:記憶體控制器
616:快取記憶體
617,622,624,626:介面
620:晶片組
630:記憶體
632:依電性記憶體
634,660:非依電性記憶體
640:顯示器(裝置)
650,655:匯流排
662:大容量儲存裝置;儲存媒體
664:鍵盤/滑鼠
666:網路介面
672:匯流排橋接件
674:I/O裝置
676:智慧型TV
677:消費者電子裝置
678:無線天線
所揭示之實施例係以範例方式、且非以限制性方式在隨附圖式之諸圖中說明,在該等圖式中相似參考數字可指類似元件,其中:
圖1A係根據若干實施例,一複合橋接晶粒至晶粒互連件於組裝期間的一橫截面正視圖101,其成為一積體電路封裝體的部分;
圖1B為根據一實施例,圖1A中所描繪之總成在進一步組裝之後的一橫截面正視圖;
圖1C為根據一實施例,圖1B中所描繪之總成在進一步加工之後的一橫截面正視圖;
圖1D為根據一實施例,圖1C中所描繪之總成在進一步加工之後的一橫截面正視圖;
圖1E為根據一實施例,圖1D中所描繪之總成在進一步加工之後的一橫截面正視圖;
圖1F為根據一實施例,圖1E中所描繪的結構在進一步加工之後的一積體電路設備中之一複合橋接晶粒至晶粒互連件的一橫截面正視圖;
圖1G為根據一實施例,於進一步結構加工後,圖1F中所描繪的積體電路設備中之複合橋接晶粒至晶粒互連件的一橫截面正視圖;
圖1H為根據一實施例,於進一步結構加工後,作為圖1G中所描繪的積體電路設備之部分的複合橋接晶粒至晶粒互連件132之一橫截面正視圖;
圖1為根據若干實施例,諸如包括圖1H中描繪的複合橋接晶粒至晶粒互連件之IC封裝體的一積體電路封裝體設備的一橫截面正視圖;
圖1K為根據若干實施例,為圖1中所描繪之含有複合橋接晶粒至晶粒互連件之積體電路封裝體設備的一頂部平面圖。項目1I及1J省略;
圖1M係一複合橋接晶粒至晶粒互連件之與一積體電路封裝體及積體電路晶粒介接的一詳細區段部分。項目1L省略;
圖2為根據一實施例之帶有一複合橋接晶粒至晶粒互連件之積體電路封裝體設備的一橫截面正視圖;
圖3為根據一實施例之帶有一複合橋接晶粒至晶粒互連件之積體電路封裝體的一橫截面正視圖;
圖3A為根據若干實施例,為圖3中所描繪之含有複合橋接晶粒至晶粒互連件之積體電路封裝體設備的一頂部平面圖。
圖3B為根據若干實施例,為一含有複合橋接晶粒至晶粒互連件之積體電路封裝體設備的一頂部平面圖,諸如圖3中所描繪之含有複合橋接晶粒至晶粒互連件之積體電路封裝體設備。
圖4為根據一實施例之帶有一複合橋接晶粒至晶粒互連件之積體電路封裝體設備的一橫截面正視圖;
圖5係依據若干實施例之用以將一複合橋接晶粒至晶粒互連件組裝至一積體電路封裝體裝置之一方法流程圖;以及
圖6被含括以展示用於所揭示實施例之一較高位準裝置應用的一範例。
8,18:主動裝置
9,19:主動層及金屬化結構
10:(第一)積體電路(IC)晶粒
20:(後續)IC晶粒;圖形處理器
112:(電容器)被動裝置;(解耦/第一)電容器
117,117':(晶粒側)電氣凸塊;凸塊陣列;凸塊
120:模製層;模製材料
126,126':複合橋接接觸件;接點
128:被動裝置接觸件;接點
130,130':側向互連件;(傳導)跡線
134:晶粒至晶粒跡線
140:傳導屏蔽
148:封裝體通孔
150:跡線
Claims (21)
- 一種積體電路設備,其包含: 一第一積體電路(IC)晶粒; 一後續IC晶粒; 在該第一IC晶粒及該後續IC晶粒之每一者上之封裝體-連接件接合墊; 一複合橋接晶粒至晶粒互連件,其接觸在該第一IC晶粒及該後續IC晶粒上之複合橋接接合墊; 一被動裝置,其位於該第一IC晶粒與該後續IC晶粒之間,且接觸該複合橋接晶粒至晶粒互連件;以及 一模製材料,其接觸該第一IC晶粒及該後續IC晶粒、該被動裝置及該複合橋接晶粒至晶粒互連件。
- 如請求項1之積體電路設備,其進一步包括: 在該複合橋接晶粒至晶粒互連件中之一第一側向互連件,其耦接至該第一IC晶粒及耦接至該被動裝置;以及 在該複合橋接晶粒至晶粒互連件中之一後續側向互連件,其耦接至該後續IC晶粒及耦接至該被動裝置。
- 如請求項1至2中任一項之積體電路設備,其進一步包括該複合橋接晶粒至晶粒互連件中的一晶粒至晶粒跡線,其繞過該被動裝置且耦接該第一IC晶粒及該後續IC晶粒。
- 如請求項1至3中任一項之積體電路設備,其進一步包括該複合橋接晶粒至晶粒互連件中的一傳導屏蔽,其中該傳導屏蔽伸出一佔用面積至該複合橋接接合墊上,且至該被動裝置上。
- 如請求項1至4中任一項之積體電路設備,其進一步包括: 一積體電路封裝體基體;以及 封裝體-連接件電氣凸塊,其接觸該等封裝體-連接件接合墊,其中該等電氣凸塊在該積體電路封裝體基體上位在一晶粒側。
- 如請求項1至5中任一項之積體電路設備,其進一步包括: 一積體電路封裝體基體; 封裝體-連接件電氣凸塊,其接觸該等封裝體-連接件接合墊,其中該等電氣凸塊在該積體電路封裝體基體上位在一晶粒側;以及 其中該複合橋接晶粒至晶粒互連件亦在該晶粒側上。
- 如請求項1至6中任一項之積體電路設備,其中該被動裝置為一嵌入式被動裝置,其進一步包括: 一積體電路封裝體基體,其包括一晶粒側及一焊盤側; 封裝體-連接件電氣凸塊,其接觸該等封裝體-連接件接合墊,其中該等電氣凸塊在該積體電路封裝體基體上位在該晶粒側;以及 該晶粒側上之一底部被動裝置,其中該底部被動裝置係耦接至該第一IC晶粒及該後續IC晶粒的至少一者。
- 一種積體電路封裝體設備,其包含: 一積體電路封裝體基體,其包括一晶粒側及一焊盤側; 該晶粒側上的一第一積體電路(IC)晶粒; 該晶粒側上的一後續IC晶粒; 封裝體-連接件接合墊,其接觸在該晶粒側的該第一IC晶粒及該後續IC晶粒; 一複合橋接晶粒至晶粒互連件,其接觸在該第一IC晶粒及該後續IC晶粒上之複合橋接接合墊; 一被動裝置,位於該第一IC晶粒與該後續IC晶粒之間,且耦接至該複合橋接晶粒至晶粒互連件;以及 一模製材料,其接觸該第一IC晶粒及該後續IC晶粒、該被動裝置及該複合橋接晶粒至晶粒互連件。
- 如請求項8之積體電路封裝體設備,其中該被動裝置接觸該複合橋接晶粒至晶粒互連件。
- 如請求項8至9中任一項之積體電路封裝體設備,其進一步包括該第一IC晶粒上的至少一小晶片,且其藉由一穿矽通孔耦接至該第一IC晶粒。
- 如請求項8至10中任一項之積體電路封裝體設備,其進一步包括: 該第一IC晶粒上的至少一小晶片,且其藉由一穿矽通孔耦接至該第一IC晶粒;以及 該後續IC晶粒上的至少一小晶片,且其藉由一穿矽通孔耦接至該後續IC晶粒。
- 如請求項8至11中任一項之積體電路封裝體設備,其中該被動裝置為一第一被動裝置,其進一步包括一後續被動裝置,位於該第一IC晶粒與該後續IC晶粒之間且於該模製材料中,其中該後續被動裝置接觸該複合橋接晶粒至晶粒互連件。
- 如請求項8至12中任一項之積體電路封裝體設備,其中該被動裝置為一第一被動裝置,其進一步包括一第一內部被動裝置,位於該第一被動裝置下方且於該模製材料中,其中該第一內部被動裝置接觸該複合橋接晶粒至晶粒互連件。
- 如請求項8至13中任一項之積體電路封裝體設備,其中該被動裝置為一第一被動裝置,其進一步包括: 一第一內部被動裝置,位於該第一被動裝置下方且於該模製材料中,其中該第一內部被動裝置接觸該複合橋接晶粒至晶粒互連件; 一後續被動裝置,位於該第一IC晶粒與該後續IC晶粒之間且於該模製材料中,其中該後續被動裝置接觸該複合橋接晶粒至晶粒互連件;以及 一後續內部被動裝置,位於該後續被動裝置下方且於該模鑄材料中,其中該後續內部被動裝置接觸該複合橋接晶粒至晶粒互連件。
- 如請求項8至14中任一項之積體電路封裝體設備,其中該被動裝置為一第一被動裝置,其進一步包括: 一後續被動裝置,位於該第一IC晶粒與該後續IC晶粒之間且於該模製材料中,其中該後續被動裝置接觸該複合橋接晶粒至晶粒互連件; 一第三IC晶粒,位在該晶粒側上、鄰近該第一IC晶粒及該後續IC晶粒之每一者; 一第四IC晶粒,位在該晶粒側上、鄰近該第一IC晶粒及該後續IC晶粒之每一者;以及 一第三被動裝置,位於該第一IC晶粒與該第四IC晶粒之間且於該模製材料中,其中該第三被動裝置接觸該複合橋接晶粒至晶粒互連件。
- 如請求項8至15中任一項之積體電路封裝體設備,其中該被動裝置為一第一上部被動裝置,其進一步包括一第一下部被動裝置,位於該第一上部被動裝置下方並與之接觸、且於該模製材料中,其中該第一下部被動裝置接觸該複合橋接晶粒至晶粒互連件。
- 如請求項8至16中任一項之積體電路封裝體設備,其進一步包括: 耦接至該焊盤側之一印刷佈線板;以及 耦接至該印刷佈線板的一晶片組。
- 如請求項17之積體電路封裝體設備,其中該印刷佈線板包括一外部殼體,該外部殼體為一介電材料,且其中該外部殼體為擇自於一行動運算系統及一無人機的一裝置的外部之至少部分。
- 一種組裝一積體電路設備之方法,其包含: 將一複合橋接晶粒至晶粒互連件組裝於一第一積體電路晶粒、一被動裝置及一後續積體電路晶粒上,其中該被動裝置係位於該第一積體電路晶粒與該後續積體電路晶粒之間;以及 使一模製材料接觸到該複合橋接晶粒至晶粒互連件、該第一積體電路晶粒及該後續積體電路晶粒、且接觸到該被動裝置。
- 如請求項19之方法,其進一步包括於一晶粒側上將該複合橋接晶粒至晶粒互連件組裝至一積體電路封裝體基體,其中該第一積體電路晶粒及該後續積體電路晶粒上之電氣凸塊接觸該晶粒側;以及 底部填充該第一積體電路晶粒及該後續積體電路晶粒。
- 如請求項19之方法,其進一步包括於一晶粒側上將該複合橋接晶粒至晶粒互連件組裝至一積體電路封裝體基體,其中該第一積體電路晶粒及該後續積體電路晶粒上之電氣凸塊接觸該晶粒側; 底部填充該第一積體電路晶粒及該後續積體電路晶粒;以及 將該積體電路封裝體基體於一焊盤側處組裝至一印刷佈線板。
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