CN104124223B - 电子系统及其核心模块 - Google Patents

电子系统及其核心模块 Download PDF

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Publication number
CN104124223B
CN104124223B CN201310205713.7A CN201310205713A CN104124223B CN 104124223 B CN104124223 B CN 104124223B CN 201310205713 A CN201310205713 A CN 201310205713A CN 104124223 B CN104124223 B CN 104124223B
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component
packaging
base plate
fastener
assembly
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CN104124223A (zh
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杨之光
张振义
古永延
薛淦浩
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Princo Corp
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Princo Corp
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Abstract

一种核心模块，包括：封装基板，具有多个焊垫；第一组件，通过多个第一接合件与对应第一组件的封装基板的这些焊垫接合，且以第一模封材料模封第一组件；第二组件，通过多个第二接合件与对应第二组件的封装基板的这些焊垫接合；以及一第三组件，通过多个第三接合件与对应第三组件的封装基板的这些焊垫接合，其中第一组件、第二组件及第三组件之间均透过封装基板形成电性连接且以一母模封材料模封第一组件、第二组件及第三组件。

Description

电子系统及其核心模块
技术领域
本发明是关于一种电子系统及其核心模块；特别关于一种多组件子母封装的电子系统及其核心模块。
背景技术
当前多组件电子系统所采用的堆栈封装为已知技术，应高积集度以及电子产品微型化且多功能的封装要求，当前堆栈封装正蓬勃发展出多种技术。如图1所示的堆栈式封装层迭(Package on Package)技术抑或SiP(System in Package)封装技术。此已知技术例如具有第一组件A、第二组件B及第三组件C整合于单一封装模块中。第一组件A首先封装于第一封装基板100且以第一模封材料102进行模封后通过焊锡与基板D连接。并且，为能与设置于上方的第二组件B连接，会于对应位置形成多个第一通孔104，并填入导电性金属材料。第二组件B首先封装于第二封装基板200且以第二模封材料202进行模封后通过焊锡与第一组件A连接。并且，为能与设置于上方的第三组件C连接，会于对应位置形成多个第二通孔204，并填入导电性金属材料。第三组件C首先封装于第三封装基板300且以第三模封材料302进行模封后通过焊锡与第二组件B连接。此一封装模块。此外，图1所示的堆栈式封装层迭虽是采用第一通孔104及第二通孔204来实现组件间的电性连接，但亦有采用打线技术的方式实现电性连接。
然而，此类堆栈式封装层迭PoP技术，存在诸多缺点。由于每一个组件皆需单独先行模封，因此当堆栈时，必然限制了组件间周期距的缩小，因此存在高度无法降低的必然性缺陷，也限制了焊锡与焊垫的大小无法更进一步缩小。再者，由于堆栈式封装层迭后的电性连接复杂，封装后的良率仅能倚赖各组件堆栈前的测试结果，亦有可能因无法再实施堆栈后之后测试以确保可靠度，因此必需承担封装的失败风险。并且，即便如前述以第一通孔104、第二通孔204或者打线技术来实现组件间的电性连接，皆增加了封装电性连接的工艺多种类及因制造过程繁琐而必然导致整体成本增加。
因此，确有发展一种可解决前开封装结构缺点的电子系统及其核心模块为本发明的目的。
发明内容
本发明的目的在于提供一种核心模块，包括：一封装基板，具有多个焊垫；一第一组件，通过多个第一接合件与对应所述第一组件的所述封装基板的这些焊垫接合，且以一第一模封材料模封所述第一组件；一第二组件，通过多个第二接合件与对应所述第二组件的封装基板的这些焊垫接合；以及一第三组件，通过多个第三接合件与对应所述第三组件的所述封装基板的这些焊垫接合，其中所述第一组件、所述第二组件及所述第三组件之间均透过所述封装基板形成电性连接且以一母模封材料模封所述第一组件、所述第二组件及所述第三组件。
本发明的核心模块可进一步包括至少一第四组件，通过多个第四接合件与对应所述至少一第四组件的所述封装基板的这些焊垫接合，透过所述封装基板，与所述第一组件、所述第二组件及所述第三组件之间形成电性连接且所述母模封材料亦模封至少一第四组件。
本发明核心模块的实施例中，所述第一组件可为一存储组件。所述存储组件包括至少一非挥发性内存。所述第二组件可为一逻辑组件。所述第三组件可为一电源管理组件。所述封装基板可为一具有多层内联机的薄膜基板。
本发明的目的在于提供一种电子系统，包括：一封装基板，具有多个焊垫；一第一组件，通过多个第一接合件与对应所述第一组件的所述封装基板的这些焊垫接合，且以一第一模封材料模封所述第一组件；一第二组件，通过多个第二接合件与对应所述第二组件的所述封装基板的这些焊垫接合；一第三组件，通过多个第三接合件与对应所述第三组件的所述封装基板的这些焊垫接合；以及一电路基板，具有多个电路基板焊垫，通过多个电路基板焊锡与所述封装基板接合，其中所述第一组件、所述第二组件及所述第三组件之间均透过所述封装基板形成电性连接且以一母模封材料模封所述第一组件、所述第二组件及所述第三组件。
本发明的电子系统可进一步包括至少一周边组件，所述电路基板通过这些电路基板焊锡与所述至少一周边组件接合。
本发明电子系统的实施例中，所述至少一周边组件是选自GPS模块、WIFI模块、GSM模块、触控模块音源影像模块、显示模块、MEMS磁力计、FM模块、USB host控制器、GPIO接口、直流电源、开关、电池中的至少其中一个。
本发明利用子母封装的概念，能解决前开堆栈式封装层迭PoP技术中各组件皆需先行封装而徒增制造成本及工艺繁琐的缺点，各组件可视其所需，先行封装与否并不再受限制，更提供了组件封装的多样结构，满足不同产品设计的功能需求，也明显地降低了前开堆栈式封装层迭PoP技术于完成单一封装模块后测试的复杂性而无法实施测试的可能。并且，本发明提出的核心模块，将所有组件的电性连接皆透过单一封装基板实现，因此可更进一步简化所有组件的封装技术，例如，依据本发明所有组件、第四组件的封装均可采用表面贴装技术(Surface Mount Technology)，而大幅提高封装工艺的效率。
附图说明
图1是已知技术的多组件堆栈的示意图。
图2是本发明的电子系统及其核心模块的示意图。
图3是本发明的电子系统及其核心模块的功能方块图。
图中标号的对应关是如下：
1 封装基板
2 焊垫
3 电路基板
4 电路基板焊垫
5 电路基板焊锡
10 第一组件
12 第一模封材料
14 第一封装基板
16 第一接合件
20 第二组件
26 第二接合件
30 第三组件
32 第三模封材料
36 第三接合件
40 第四组件
46 第四接合件
50 母模封材料
100 第一封装基板
102 第一模封材料
104 第一通孔
200 第二封装基板
202 第二模封材料
204 第二通孔
300 第三封装基板
302 第三模封材料
A 第一组件
B 第二组件
C 第二组件
D 基板
具体实施方式
请参阅本发明图2。图2是本发明的电子系统及其核心模块的示意图。本发明的核心模块包括一封装基板1、一第一组件10、一第二组件20以及一第三组件30。封装基板1具有多个焊垫2，可为一薄膜基板。并且如图2所示，其可为一多层内联机基板。作为封装基板1的多层内联机基板，其总厚度小于100μm；单一层的厚度小于20μm，且还可小于10μm；最小线宽于30μm，且还可小于15μm；这些焊垫的周期距(pitch)小于80μm，且更可小于50μm。周期距(pitch)的定义是为两相邻焊垫的几何中心点或几何中心线间的距离。其多层内联机是用以提供第一组件10、第二组件20以及第三组件30等间的电性连接功能。在本发明中，是用第一模封材料12预先进行模封第一组件10。第一组件10可先已封装在第一封装基板14上，并且通过多个第一接合件16与对应第一组件10的封装基板1的多个焊垫2接合。如图所示，第二组件20可与第一组件10以堆栈的方式，即第一组件10相对于封装基板1位于第二组件20的上方，通过多个第二接合件26与对应第二组件20的封装基板1的多个焊垫2接合。在本发明的实施例中，第二组件20可为一逻辑组件，例如可为一处理器。第一组件10可为一存储组件。所述存储组件包括至少一非挥发性内存，例如一NAND闪存或一NOR闪存。
在本发明中，是用第三模封材料32预先模封第三组件30。第三组件30通过多个第三接合件36与对应第三组件30的封装基板1的多个焊垫2接合。在本发明的实施例中，第三组件30可为一电源管理组件。并且，本发明的核心模块可进一步包括至少一第四组件40，例如：应用本发明电子产品的电路设计所需的至少一电容或电阻等被动组件，或者为系统设计所需的其它类型组件。同样地，至少一第四组件40亦通过多个第四接合件46与对应至少一第四组件40的封装基板1的多个焊垫2接合。第一接合件16、第二接合件26、第三接合件36及第四接合件46例如可为焊锡、凸块或锡球。透过与封装基板1的接合，实现与第一组件10、第二组件20以及第三组件30间的电性连接。所以，本发明中第一组件10、第二组件20、第三组件30以及至少一第四组件40均透过封装基板1形成电性连接，并且以母模封材料50以单一个工艺，同时模封第一组件10、第二组件20、第三组件30以及至少一第四组件40，形成单一模块化(monolithic)的单一个封装体，以作为一电子产品的核心模块。
如本发明图2所示，第一组件10、第二组件20、第三组件30以及至少一第四组件40各别焊锡与焊垫的接点均透过一高密度载板，即封装基板1互连后，再将各组件封埋于母模封材料50之中。并且，如图2中所示，为设计上不同的应用，在第一组件10的正下方与第一封装基板14间的间隙，或者在已以第一封装基板14封装的第一组件10、第二组件20、第三组件30以及至少一第四组件40的正下方与封装基板1间之间隙中填入保护胶材(图2中的虚线表示)。或者可在第二组件20下方先填入一种保护胶材，再在已以第一封装基板14封装的第一组件10下方再填入相同或他种保护胶材。前述针对各组件保护胶材的选用是可依间隙内的特性以及保护胶材本身的吸水性、热传系数、热膨胀系数、玻璃转化点而可以有不同选择，可使用同一种保护胶材，也可以采用不同保护胶材，甚至也可使用母模封材料50一次灌入所有间隙中亦为本发明可采用的选项。
并且，本发明电子系统及其核心模块的单一模块化(monolithic)于工艺上具有的技术优点，即第一组件10、第二组件20、第三组件30以及至少一第四组件40分别透过第一接合件16、第二接合件26、第三接合件36以及第四接合件46与封装基板1上相对应的焊垫接合，可仅需要一次回焊前述设置于同一平面上的第一接合件16、第二接合件26、第三接合件36以及第四接合件46与封装基板1上对应的焊垫，然已知技术中一般SiP(System inPackage)封装技术中的SiP模块并非单一模块化(monolithic)，亦即个别组件是以个别的回焊工艺将组件与作为载板的晶圆进行接着。因此，进行第二次或之后多次回焊时，晶圆上方已接着的组件即有可能发生脱焊的情形。
现今可行的方法例如：第一次回焊时使用较高温的接着焊料(焊锡)，第二次回焊或之后多次回焊时，焊接点使用较低温的焊料(焊锡)。然此类解决方案存在诸多限制。首先，较高温的接着焊料及其较高温的回焊工艺对组件产生的热冲击大，会导致组件的可靠度降低及使用寿命缩短。并且，若不使用较高温的接着焊料进行第一次或较先的回焊工艺，则进行第二次或之后多次回焊时，已接着的组件即有可能发生脱焊的情形。甚至之后多次回焊时，高温下导致封装基板1及电路基板3发生热翘曲，亦会导致焊锡与焊垫的接点脱焊或空焊。
请参阅本发明图2及图3。图3是本发明的电子系统及其核心模块的功能方块图。如图2及图3所示，本发明的电子系统包括一封装基板1、一第一组件10、一第二组件20、一第三组件30以及一电路基板3。电路基板3具有多个电路基板焊垫4。电路基板3通过多个电路基板焊锡5与封装基板1接合。本发明的电子系统可更进一步包括至少一周边组件。电路基板3亦通过电路基板焊锡5与所述至少一周边组件接合。
本发明中第二组件20可为一逻辑组件，例如：一处理器(Processor)或一可逻辑化组件(Programmable IC)。由于运作功率较大，在本发明实施例中，例如可采裸晶(baredie)封装，使其热阻小。并且如图2所示配置接近封装基板1，第二接合件26可采用微凸块(micro bump，尺寸如小于50μm，较佳为20～50μm；凸块高度如小于50μm，较佳为10～20μm)，例如柱形凸块(stud bump)。则向下热阻可有效地降低，使其发热更有效率地传导至封装基板1，有利于本发明的电子系统及其核心模块整体的系统效能。
第一组件10可为一存储组件。所述存储组件包括至少一非挥发性内存(NANDFlash memory)以及同步动态随机存取存储器(SDRAM)，或者动态内存(DRAM)等及其组合。视本发明电子系统及其核心模块最终系统设计所需而有所不同。如图2所示，设置于第二组件20上方使其配置空间较大，配置也较有弹性，可视系统设计所需而更换不同的模块组合，而不影响第二组件20的工艺以及空间配置。
第三组件30可为一电源管理组件(Power management IC)。第二组件20与第三组件30之间更耦接至少一电容42，以供电源管理组件能因实际所需对处理器(Processor)或可逻辑化组件(Programmable IC)提供电源。而至少一第四组件40除可为前述电容或电阻等被动组件外，亦可包括通讯组件，数字模拟转换组件(AD convertor)，频率振荡器…等已封装完成的组件，亦可为图标未模封的裸晶组件、或者晶圆级芯片尺寸封装(wafer levelCSP)的组件，使本发明电子系统及其核心模块的整体积集度更高，更微小化。
再者，如图2及图3所示，电源管理组件可通过电路基板3及电路基板焊锡5，对外耦接直流电源、开关、电池等或其它所需组件。处理器(Processor)或可逻辑化组件(Programmable IC)可通过电路基板3及电路基板焊锡5，对外耦接GPS模块、WIFI模块、GSM模块、触控模块、音源影像模块、显示模块、MEMS磁力计、FM模块、USB主控制器(USB hostcontroller)、通用输入输出接口(GPIO)等等。利用本发明，由于作为封装基板1的多层内联机基板是已完成核心模块中所有设计上大部分所需的电性连接，加上本发明以子母封装形成单一封装体的核心模块的技术特性，仅需低密度布线的电路基板3，即能实现本发明电子系统所需的各种功能。
如前所述，由于本发明的电子系统及其核心模块中，第一组件10、第二组件20、第三组件30以及至少一第四组件40均透过封装基板1形成电性连接，因此第一组件10、第二组件20、第三组件30以及至少一第四组件40的封装可采用表面贴装技术(Surface MountTechnology)，以单一回焊工艺即实现封装完成，而使封装技术使用单纯化，当然本发明亦非仅限于以单一回焊工艺实现封装完成。并且，第一组件10、第二组件20、第三组件30可不需要各别先行模封，而是视其需先行模封与否，且本发明于回焊前，或以母模封材料50对所有组件进行模封前，亦更可进行测试步骤，若有电性缺陷可于以母模封材料50进行模封即行修正，不仅大幅提高封装工艺的效率，更能提高最终整体良率避免封装缺陷，无法回工而导致组件的报废耗损，有效降低制造成本。
再者，如前所述由于本发明是以母模封材料50形成单一封装体的核心模块，并且具备高积集度特性，作为封装基板1的多层内联机基板是已完成核心模块中所有设计上大部分所需的电性连接，加上本发明子母封装的技术特性，于制作电子系统时所采用的电路基板，仅需低密度布线的电路板(PCB)即可。而无需如现今技术多必需采用高密度电路板(HDI PCB)。高密度电路板一般而言其结构至少包括6-8层，同时亦必需配合采用雷射钻孔形成其中的导通孔结构。而利用本发明，所需低密度布线的电路基板1的层数仅需4层以下，且其仅需采用机械钻孔形成其中的导通孔结构即能实现前述与所述至少一周边组件的接合。而相较于需采用高密度电路板(HDI PCB)作为电路基板的现有技术，通过本发明子母封装概念，形成单一封装体的核心模块，所采用的低密度布线的电路板(PCB)不仅成本大幅降低，制造更有效率，可靠度能更进一步有效地提升。
总的，本发明子母封装的概念，解决前开堆栈式封装层迭PoP技术中各组件皆需先行封装而徒增制造成本及工艺繁琐的缺点。提供了组件封装的多样结构，满足不同产品设计的功能需求，也降低了前开堆栈式封装层迭技术于完成封装模块后的测试复杂性。且各组件可视其所需，先行封装与否并不再受限制，因本发明提出的电子系统及其核心模块所具备子母封装的特性，最终会实施完整母模封材料的封装。再者，所有组件的电性连接皆透过单一封装基板实现，能对所有组件、第四组件的封装均采用表面贴装技术(SurfaceMount Technology)而以一次回焊即完成电性连接。且在回焊前能进行测试即行修正，大幅提高封装工艺的效率。
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明结构的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (46)

1.一种核心模块，其特征在于，包括：
一封装基板，具有多个焊垫；
一第一组件，封装在一第一封装基板上并通过多个第一接合件与对应所述第一组件的封装基板的这些焊垫接合，所述第一接合件位于所述第一封装基板的下表面；
一第二组件，通过多个第二接合件与对应所述第二组件的封装基板的这些焊垫接合，所述第二接合件位于所述第二组件的下表面；以及
一第三组件，通过多个第三接合件与对应所述第三组件的封装基板的这些焊垫接合，所述第三接合件位于所述第三组件的下表面，其中所述第一组件相对于封装基板位于第二组件的上方，所述第一组件、第二组件及第三组件之间均透过封装基板形成电性连接且以一母模封材料模封第一组件、第二组件及第三组件，所述第一接合件、所述第二接合件及所述第三接合件设置于同一平面上。
2.如权利要求1所述的核心模块，其特征在于，所述第一组件是以一第一模封材料进行模封。
3.如权利要求1所述的核心模块，其特征在于，所述第一接合件、所述第二接合件或所述第三接合件是至少选自焊锡、凸块或锡球之中的一种形态。
4.如权利要求1所述的核心模块，进一步包括至少一第四组件通过多个第四接合件与对应所述至少一第四组件的所述封装基板的这些焊垫接合，透过所述封装基板，与所述第一组件、第二组件及第三组件之间形成电性连接且所述母模封材料亦模封所述至少一第四组件。
5.如权利要求4所述的核心模块，其特征在于，所述第四接合件是至少选自焊锡、凸块或锡球之中的一种形态。
6.如权利要求1所述的核心模块，其特征在于，所述第二组件为一逻辑组件。
7.如权利要求6所述的核心模块，其特征在于，所述逻辑组件为一处理器。
8.如权利要求1所述的核心模块，其特征在于，所述第一组件为一存储元件。
9.如权利要求8所述的核心模块，其特征在于，所述存储元件包括至少一非挥发性内存。
10.如权利要求8所述的核心模块，其特征在于，所述存储元件包括一NAND闪存。
11.如权利要求8所述的核心模块，其特征在于，所述存储元件包括一NOR闪存。
12.如权利要求1所述的核心模块，其特征在于，所述第三组件为一电源管理组件。
13.如权利要求1所述的核心模块，其特征在于，所述封装基板为一薄膜基板。
14.如权利要求13所述的核心模块，其特征在于，所述薄膜基板是为一多层内联机基板。
15.如权利要求1所述的核心模块，其特征在于，所述封装基板的总厚度小于100μm。
16.如权利要求1所述的核心模块，其特征在于，所述封装基板中单一层的厚度小于20μm。
17.如权利要求1所述的核心模块，其特征在于，所述封装基板中的最小线宽小于30μm。
18.如权利要求1所述的核心模块，其特征在于，这些焊垫的周期距小于80μm。
19.如权利要求1所述的核心模块，其特征在于，所述第一组件、第二组件及第三组件是以单一回焊使这些第一接合件、第二接合件、及第三接合件与对应的焊垫接合。
20.如权利要求1所述的核心模块，其特征在于，所述第二组件为一裸晶组件。
21.如权利要求20所述的核心模块，其特征在于，这些第二接合件为多个微凸块。
22.一种电子系统，其特征在于，包括：
一封装基板，具有多个焊垫；
一第一组件，封装在一第一封装基板上并通过多个第一接合件与对应所述第一组件的封装基板的这些焊垫接合，所述第一接合件位于所述第一封装基板的下表面；
一第二组件，通过多个第二接合件与对应所述第二组件的封装基板的这些焊垫接合，所述第二接合件位于所述第二组件的下表面；
一第三组件，通过多个第三接合件与对应所述第三组件的封装基板的这些焊垫接合，所述第三接合件位于所述第三组件的下表面；以及
一电路基板，具有多个电路基板焊垫，通过多个电路基板焊锡与所述封装基板接合，其中所述第一组件相对于所述封装基板位于第二组件的上方，所述第一组件、第二组件及第三组件之间均透过封装基板形成电性连接且以一母模封材料模封第一组件、第二组件及第三组件，所述第一接合件、所述第二接合件及所述第三接合件设置于同一平面上。
23.如权利要求22所述的电子系统，其特征在于，所述第一组件是以一第一模封材料进行模封。
24.如权利要求22所述的电子系统，其特征在于，所述第一接合件、第二接合件或第三接合件是至少选自焊锡、凸块或锡球中的一种形态。
25.如权利要求22所述的电子系统，进一步包括至少一第四组件，通过多个第四接合件与对应所述至少一第四组件的封装基板的这些焊垫接合，透过所述封装基板，与第一组件、第二组件及第三组件之间形成电性连接且母模封材料亦模封至少一第四组件。
26.如权利要求25所述的电子系统，其特征在于，所述第四接合件是至少选自焊锡、凸块或锡球之中的一种形态。
27.如权利要求22所述的电子系统，其特征在于，所述第二组件为一逻辑组件。
28.如权利要求27所述的电子系统，其特征在于，所述逻辑组件为一处理器。
29.如权利要求22所述的电子系统，其特征在于，所述第一组件为一存储元件。
30.如权利要求29所述的电子系统，其特征在于，所述存储元件包括至少一非挥发性内存。
31.如权利要求29所述的电子系统，其特征在于，所述存储元件包括一NAND闪存。
32.如权利要求29所述的电子系统，其特征在于，所述存储元件包括一NOR闪存。
33.如权利要求22所述的电子系统，其特征在于，所述第三组件为一电源管理组件。
34.如权利要求22所述的电子系统，其特征在于，所述封装基板为一薄膜基板。
35.如权利要求34所述的电子系统，其特征在于，所述薄膜基板为一多层内联机基板。
36.如权利要求22所述的电子系统，其特征在于，所述封装基板的总厚度小于100μm。
37.如权利要求22所述的电子系统，其特征在于，所述封装基板中单一层的厚度小于20μm。
38.如权利要求22所述的电子系统，其特征在于，所述封装基板中的最小线宽于30μm。
39.如权利要求22所述的电子系统，其特征在于，这些焊垫的周期距小于80μm。
40.如权利要求22所述的电子系统，其特征在于，所述第一组件、第二组件及第三组件是以单一回焊使第一接合件、第二接合件、及第三接合件与对应的焊垫接合。
41.如权利要求22所述的电子系统，其特征在于，所述第二组件为一裸晶组件。
42.如权利要求41所述的电子系统，其特征在于，这些第二接合件为多个微凸块。
43.如权利要求22所述的电子系统，其特征在于，进一步包括至少一周边组件，所述电路基板通过这些电路基板焊锡与所述至少一周边组件接合。
44.如权利要求43所述的电子系统，其特征在于，所述至少一周边组件是选自GPS模块、WIFI模块、GSM模块、触控模块、音源影像模块、显示模块、MEMS磁力计、FM模块、USB host控制器、GPIO接口、直流电源、开关、电池中的至少其中一个。
45.如权利要求22所述的电子系统，其特征在于，所述电路基板的层数小于四层。
46.如权利要求22所述的电子系统，其特征在于，所述电路基板中的导通孔是以机械钻孔形成。
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