CN103890942A - 堆叠式封装体结构 - Google Patents

堆叠式封装体结构 Download PDF

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Publication number
CN103890942A
CN103890942A CN201280050766.XA CN201280050766A CN103890942A CN 103890942 A CN103890942 A CN 103890942A CN 201280050766 A CN201280050766 A CN 201280050766A CN 103890942 A CN103890942 A CN 103890942A
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CN
China
Prior art keywords
soldered ball
substrate layer
packaging body
nude film
bottom side
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Pending
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CN201280050766.XA
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English (en)
Inventor
高华宏
S-m·刘
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Marvell World Trade Ltd
Mawier International Trade Co Ltd
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Mawier International Trade Co Ltd
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Publication of CN103890942A publication Critical patent/CN103890942A/zh
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Abstract

本公开内容的实施例提供一种包括底部封装体和第二封装体的堆叠式封装体布置。第一封装体包括衬底层，该衬底层包括(i)顶部侧和(ii)与顶部侧相对的底部侧。另外，顶部侧限定基本上平坦的表面。第一封装体也包括耦合到衬底层的底部侧的裸片。第二封装体包括多行焊球，并且第二封装体经由多行焊球附着到衬底层的顶部侧的基本上平坦的表面。

Description

堆叠式封装体结构
相关申请的交叉引用
本公开内容要求于2012年8月13日提交的第13/584,027号美国专利申请的优先权，该美国专利申请要求于2011年8月19日提交的第61/525,521号美国临时专利申请的优先权，除了与本说明书不一致的那些部分(如果有)之外，出于所有目的而通过完全引用将该美国临时专利申请的全部说明书结合于此。
技术领域
本公开内容的实施例涉及堆叠式封装体(POP)结构并且更具体地涉及封装布置，这些封装布置并入具有裸片向下倒装(die-downflipped)结构的基部封装体。
背景技术
在本文中提供的背景技术描述是为了一般地呈现公开内容的背景。当前署名的发明人的工作在这一背景技术部分中描述的程度上以及该描述的可以在提交时未另外限定为现有技术的方面，既未明确地也未暗示地承认为相对于本公开内容的现有技术。
通常就许多多芯片封装布置而言，以堆叠式封装体(PoP)布置或者多芯片模块(MCM)布置之一来布置封装布置。这些封装布置往往相当厚(例如近似1.7毫米至2.0毫米)。
PoP布置可以包括在彼此上面组合两个或者更多封装体的集成电路。例如可以用两个或者更多存储器器件封装体来配置PoP布置。也可以利用在底部封装体中包括逻辑并且在顶部封装体中包括存储器(或者反之亦然)的混合逻辑存储器堆叠来配置PoP布置。
通常，与位于PoP布置的底部上的封装体(在本文中称为“底部封装体”)关联的裸片将位于底部封装体上方的封装体(在本文中称为“顶部封装体”)的覆盖面积(footprint)限制为某个尺寸。此外，这样的配置一般将顶部封装体限制为两行外围焊球。在图8中图示这样的封装布置800的示例并且该示例包括顶部封装体802和底部封装体804。正如可见，底部封装体804包括经由粘合剂810附着到衬底808的裸片806。裸片806用接线812经由接线键合工艺耦合到衬底808。提供焊球814用于将封装布置800耦合到另一衬底(未图示)，如例如印刷电路板(PCB)。顶部封装体802包括耦合到衬底818的裸片816。提供焊球820将顶部封装体802耦合到底部封装体804。顶部封装体802可以包括如果希望则一般为包封剂形式的外壳822。正如可见，可能由于存在底部封装体804的裸片806和外壳824(一般为包封剂的形式并且可以或者可以未被包括)而仅提供两行焊球820。因此，可能要求顶部封装体具有更大尺寸或者覆盖面积以在顶部封装体附着到底部封装体时避免底部封装体的裸片806。这样的封装布置800也可能对于顶部封装体802相对于裸片806和/或外壳824的间隙事项带来问题。
图9图示封装布置900的另一示例，其中已经用模具阵列工艺(Mold-Array-Process，MAP)创建底部封装体904。底部封装体904与图8的底部封装体804相似并且包括包封剂906。总体蚀刻包封剂906以暴露焊球908。备选地，蚀刻包封剂906，然后在开口910内沉积焊球908。这样的封装布置900同样由于存在裸片806和包封剂906而仅允许在顶部封装体802的外围周围包括两行焊球820。这样的封装布置800也可能对于顶部封装体802相对于裸片806和包封剂906的间隙事项以及相对于开口910的对准事项带来问题。
发明内容
在各种实施例中，本公开内容提供一种包括堆叠式封装体布置的堆叠式封装体结构，该堆叠式封装体布置包括底部封装体和第二封装体。第一封装体包括衬底层，该衬底层包括(i)顶部侧和(ii)与顶部侧相对的底部侧。另外，顶部侧限定基本上平坦的表面。第一封装体也包括耦合到衬底层的底部侧的裸片。第二封装体包括多行焊球，并且第二封装体经由多行焊球附着到衬底层的基本上平坦的表面。
本公开内容也提供一种方法，该方法包括提供包括衬底层的第一封装体。衬底层包括(i)顶部侧和(ii)与顶部侧相对的底部侧。衬底层的顶部侧限定基本上平坦的表面。第一封装体还包括耦合到衬底层的底部侧的裸片。该方法还包括：提供具有多行焊球的第二封装体，这些多行焊球附着到第二封装体的底表面；并且经由第二封装体的多行焊球将第二封装体附着到第一封装体的基本上平坦的表面。
附图说明
通过结合附图的以下具体描述，将容易理解本公开内容的实施例。为了有助于这一描述，相似标号表示相似结构单元。在附图的各图中通过示例而未通过限制来图示在本文中的实施例。
图1A示意地图示示例封装布置，该封装布置包括裸片向下倒装PoP结构的示例裸片布置。
图1B示意地图示顶部封装体附着到底部封装体的图1A的示例封装布置。
图2示意地图示另一示例封装布置，该封装布置包括裸片向下倒装PoP结构的另一示例裸片布置，该向下倒装PoP结构具有暴露的材料以提供用于散热的路径。
图3示意地图示另一示例封装布置，该封装布置包括裸片向下倒装PoP结构的另一示例裸片布置，该裸片向下倒装PoP结构被暴露以提供用于散热的路径。
图4示意地图示另一示例封装布置，该封装布置包括具有硅通孔(TSV)的裸片向下倒装PoP结构的另一示例裸片布置。
图5示意地图示另一示例封装布置，该封装布置包括具有嵌入印刷电路板(PCB)和/或插入体的裸片向下倒装PoP结构的另一示例裸片布置。
图6示意地图示另一示例封装布置，该封装布置包括具有嵌入PCB和/或插入体的裸片向下倒装PoP结构的另一示例裸片布置。
图7是用于在本文中描述的PoP结构的方法的工艺流程图。
图8示意地图示示例PoP封装布置。
图9示意地图示另一示例PoP封装布置。
具体实施方式
图1A图示根据一个实施例的封装布置100，其中堆叠式封装体(PoP)封装布置包括顶部封装体102和底部封装体104。出于示例目的，将封装体图示为分离项目。顶部封装体102包括衬底层106。在顶部封装体102内的裸片布置可以包括第一裸片108和第二裸片110，其中每个裸片108、110经由焊球112附着到衬底层106。这一配置可以包括在焊球112与衬底层116之间的空间中的下填充材料114。焊球112总体位于键合焊盘或者接触区域处(未图示)。裸片108、110可以经由倒装芯片操作耦合到衬底层106。备选地，接线键合工艺和粘合剂层(未图示)可以用来将裸片108、110耦合到衬底层106。此外，顶部封装体102可以包括两个或者更多个体顶部封装体102(未图示)，其中每个个体顶部封装体102包括一个或者多个裸片。
根据各种实施例，第一裸片108和第二裸片110是存储器器件，并且根据一个实施例，第一裸片108和第二裸片110是用于移动设备的移动双数据速率(mDDR)同步动态随机存取存储器(DRAM)。移动DDR也称为低功率DDR。然而可以利用其它类型的存储器器件，包括但不限于双数据速率同步动态随机存取存储器(DDRSDRAM)、动态随机存取存储器(DRAM)、NOR或者NAND闪存、静态随机存取存储器(SRAM)等。
根据另一实施例，具有第一裸片108和第二裸片110的顶部封装体102涉及专用产品，并且根据一个实施例，第一裸片108和/或第二裸片110可以代表用于移动设备的专用集成电路(ASIC)。
顶部封装体102还包括多个焊球115。多个焊球115可以附着到顶部封装体102的衬底层106的底部侧。在图1A的实施例中，多个焊球115形成用于在底部封装体104上电和物理附着或者堆叠顶部封装体102的配置。
为了清楚，在本文中可以并不具体图示和/或描述在顶部封装体102内使用的材料和/或在顶部封装体102内的其它部件。这样的材料和部件一般在本领域中是熟知的。
底部封装体104包括衬底层116，该衬底层包括顶部侧117a和底部侧117b。如图1A中所示，顶部侧117a定义底部侧104的基本上平坦的表面，即基本上无槽、凸块、缺口、沟等的基本上平滑的表面。在一个实施例中，顶部侧117a的基本上平坦的表面不含任何部件，这允许顶部侧117a接收(或者支持)顶部封装体102的各种设计和选择。因此，底部封装体104的平坦顶表面提供一种用于顶部封装体102的多个焊球115附着到底部封装体104的便利方式，这允许在设计顶部封装体102(或者多个个体顶部封装体102)并且由此设计封装布置100时的更大灵活性。
底部封装体104包括裸片118，该裸片在裸片向下倒装结构中经由粘合剂层120附着到衬底层116的底部侧117b。在其它实施例中，如在本文中将进一步讨论的那样，裸片118可以经由焊球附着到衬底层116的底部侧117b。
根据各种实施例，裸片118可以是存储器器件，比如用于移动设备的移动双数据速率(mDDR)同步动态随机存取存储器(DRAM)。可以利用其它类型的存储器器件，包括但不限于双数据速率同步动态随机存取存储器(DDR SDRAM)、动态随机存取存储器(DRAM)、NOR或者NAND闪存、静态随机存取存储器(SRAM)等。根据另一实施例，裸片118可以是用于创建混合逻辑存储器堆叠的逻辑器件，该混合逻辑存储器堆叠包括在底部封装体104上的逻辑和在顶部封装体102上的存储器。
裸片118具有包括一个或者多个键合焊盘112a、112b的表面。一个或者多个焊盘122a、122b总体包括导电材料，如比如铝或者铜。可以在其它实施例中使用其它适当材料。裸片118经由耦合到对应键合焊盘122a、122b的键合接线126a、126b而耦合到位于衬底层116上的一个或者多个衬底焊盘124a、124b。裸片118可以通过模制材料粘附到底部封装体104。在其它实施例中，裸片118可以经由倒装芯片或者传导粘合剂与衬底层116电互连。裸片118的电信号可以例如包括用于在裸片118上形成的集成电路(IC)器件(未图示)的输入/输出(I/O)信号和/或电源/接地。
根据一个实施例，经由模具阵列工艺(MAP)创建底部封装体104。底部封装体104还包括总体为包封剂这一形式的外壳128。蚀刻外壳128以暴露焊球129。备选地，在蚀刻外壳128之后向外壳128的蚀刻的开口131中添加焊球129。焊球130被添加到焊球129并且可以用来将封装布置100耦合到衬底(未图示)，如比如印刷电路板(PCB)、另一封装体等。备选地，在蚀刻外壳128之后向蚀刻的开口131中添加单独焊球(组合的焊球129和焊球130)。焊球130总体在底部封装体104的侧部或者外围周围，由此形成球栅阵列(BGA)。
为了清楚，在本文中可以未具体图示和/或描述在底部封装体104内使用的材料和在底部封装体104内的其它部件。这样的材料和部件一般在本领域中是熟知的。
图1B图示顶部封装体102附着到底部封装体104的封装布置100。在图1A和1B的实施例中，多个焊球115形成用于将顶部封装体102电和物理附着或者堆叠到底部封装体104的配置。如先前指出的那样，顶部封装体102可以包括附着到底部封装体104的两个或者更多个体顶部封装体。
本公开内容的附加实施例总体涉及包括具有裸片向下倒装结构的底部封装体104的各种实施例并且在图2至图6中图示的封装布置。为了简洁，在本文中未进一步讨论与图2至图7中的部件相同或者相似的图1中所示部件。
图2图示包括顶部封装体102和底部封装体204的封装布置200的另一实施例。在图2的实施例中，在裸片118的底部侧上包括热传导材料206。在一个实施例中，热传导材料206经由粘合剂层208附着到裸片118的底部侧。热传导材料206包括但不限于金属、硅或者适合用于良好热传导的任何材料。
底部封装体204包括耦合到热传导材料206的热界面材料(TIM)210。TIM210包括但不限于膜、油脂成分和下填充材料。膜可以是可以通过沉积非晶材料来制备的超薄、热传导材料。油脂成分可以包括具有高热传导率和优良分配特性的成分。常见TIM是白色膏或者热油脂，通常为氧化铝、氧化锌或者氮化硼填充的硅树脂油。一些类型的TIM使用微粉化或者磨成粉的银。另一类型的TIM包括相变材料。相变材料一般在室温为固体，但是在操作温度液化并且表现如同油脂。
可以基于希望的物理性质选择下填充材料。因此，热传导材料206提供用于向TIM210散热的路径。封装布置200可以耦合到衬底(未图示)，如比如PCB或者另一封装布置。可以在衬底中提供孔以容纳TIM210。
图3图示包括顶部封装体102和底部封装体304的封装布置300的一个实施例。裸片118经由焊球306附着到衬底层116。根据各种实施例，在焊球306之间在裸片118与衬底层116之间提供下填充材料308。下填充材料308提供对由焊球306形成的接头的保护。它也防止裸片118的内层的破裂和分层。下填充材料308可以是高纯度、低应力液体环氧树脂。总体而言，焊球306的尺寸越大，对于下填充材料308的需要就越少。
底部封装体304包括耦合到裸片118的背侧的热界面材料(TIM)310。TIM310包括但不限于如先前描述的膜、油脂成分和下填充材料。在图3的实施例中，暴露裸片118的背侧。裸片118的暴露的背侧提供用于向TIM310散热的路径。封装布置300可以耦合到衬底(未图示)，如比如PCB或者另一封装布置。可以在衬底中提供孔以容纳TIM310。
图4图示包括顶部封装体102和底部封装体404的封装布置400的一个实施例。裸片118经由焊块306附着到衬底层116。在位于底部封装体404的裸片118与衬底层116之间的空间中提供下填充材料308。下填充材料308提供对由焊球306形成的接头的保护。
在图4的实施例中，裸片118包括硅通孔(TSV)406。在一个实施例中，可以在外壳128内凹陷裸片118以帮助暴露裸片118的背侧。TSV406是穿过裸片118到达焊球306的竖直电连接过孔(竖直互连接入)。在一个实施例中，底部封装体404包括附着到底部封装体404的附加焊球408。附加焊球408可以例如用于接地/电源和输入/输出。
一个或者多个TSV406电耦合到键合焊盘(未图示)并且总体由导电材料(例如铜)填充以经过裸片118路由电信号。TSV406往往提供相对于键合接线的改进的性能，因为过孔的密度与键合接线比较明显更高并且连接的长度更短。裸片118的暴露的背侧提供底部封装体404的散热。因此，封装布置400可以对于使用封装布置400的电子设备提供增加的引脚计数和更高的速度。
图5图示包括顶部封装体102和底部封装体504的封装布置500的一个实施例。裸片118经由焊块306附着到衬底层510。
在图5的实施例中，底部封装体504包括附着到裸片118的底部侧的一个或者多个PCB和/或插入体506。根据各种实施例，PCB/插入体506使用热压缩工艺或者焊接回流工艺来键合到裸片118。也就是说，在PCB/插入体506和裸片118上形成一个或者多个导电结构(例如柱、凸块、焊盘、重分布层)以在PCB/插入体506与裸片118之间形成键合。
在一些实施例中，裸片118和PCB/插入体506均包括具有相同或者相似热膨胀系数(CTE)的材料(例如硅)。将具有相同或者相似CTE的材料用于裸片118和PCB/插入体506减少了与材料的加热和/或冷却失配相关联的应力。
PCB/插入体506向裸片118提供物理缓冲、支撑和加强媒介，尤其是在形成一个或者多个层以在外壳128中嵌入裸片118期间。也就是说，如在本文中描述的那样耦合到PCB/插入体506的裸片118提供受保护的集成电路结构，该集成电路结构比裸片118本身在结构上对与制作外壳128关联的应力更有弹性，从而造成底部封装体504的提高的产量和可靠性。
在一个实施例中，底部封装体504包括附加焊球512。附着到PCB/插入体506的附加焊球512可以例如用于接地/电源和输入/输出。
图6图示包括顶部封装体102和底部封装体604的封装布置600的一个实施例。裸片118经由粘合剂层120附着到衬底层116。如图所示，裸片118经由接线键合工艺耦合到衬底层116。
焊块606附着到裸片118的底部侧。PCB或者插入体608附着到焊球606。在一个实施例中，可以暴露或者凹陷PCB/插入体608。在一个实施例中，底部封装体604包括附加焊球610。附加焊球610可以例如用于接地/电源和输入/输出。图6的实施例可以允许附加引脚计数，并且提供用于底部封装体604的散热的经由PCB/插入体608的路径。
图7图示根据本公开内容的一个实施例的示例方法700。在702，方法700包括提供包括衬底层的第一封装体，其中衬底层包括(i)顶部侧和(ii)与顶部侧相对的底部侧，其中衬底层的顶部侧限定基本上平坦的表面，并且其中第一封装体还包括耦合到衬底层的底部侧的裸片。
在704，方法700包括提供具有多行焊球的第二封装体，这些多行焊球附着到第二封装体的底表面。
在706，方法700包括经由第二封装体的多行焊球将第二封装体附着到第一封装体的基本上平坦的表面。
该描述可以使用基于透视的描述，比如上/下、之上/之下、和/或、或者顶部/底部。这样的描述仅用来有助于讨论而未旨在于将在本文中描述的实施例的应用限制为任何特定取向。
出于本公开内容的目的，短语“A/B”意味着A或者B。出于本公开内容的目的，短语“A和/或B”意味着“(A)、(B)或者(A和B)”。出于本公开内容的目的，短语“A、B和C中的至少一个”意味着“(A)、(B)、(C)、(A和B)、(A和C)、(B和C)或者(A、B和C)”。出于本公开内容的目的，短语“(A)B”意味着“(B)或者(AB)”，也就是说，A是可选要素。
以在理解要求保护的主题内容时最有帮助的方式将各种操作依次描述为多个分立操作。然而不应解释描述顺序为意味着这些操作必然地依赖于顺序。具体而言，可以不按照呈现顺序执行这些操作。可以按照与描述的实施例不同的顺序执行描述的操作。在附加实施例中可以执行各种附加操作和/或可以省略描述的操作。
描述使用短语“在一个实施例中”、“在实施例中”或者相似言语，这些短语可以各自指代相同或者不同实施例中的一个或者多个实施例。另外，术语“包括”、“具有”等如关于本公开内容的实施例使用的那样同义。
术语芯片、集成电路、单片器件、半导体器件、裸片和微电子器件在微电子领域中经常可互换地使用。本发明适用于所有上述器件，因为它们在领域中广为理解。
虽然在本文中已经图示和描述某些实施例，但是被设计用于实现相同目的的广泛多种备选和/或等效实施例或者实现方式可以替换图示和描述的实施例，而未脱离本公开内容的范围。本公开内容旨在于覆盖在本文中讨论的实施例的任何改写或者变化。因此清楚地旨在于在本文中描述的实施例仅由权利要求及其等效含义限制。

Claims (22)

1.一种堆叠式封装体布置，包括：
第一封装体，包括：
衬底层，包括(i)顶部侧和(ii)与所述顶部侧相对的底部侧，其中所述衬底层的所述顶部侧限定基本上平坦的表面，以及
裸片，耦合到所述衬底层的所述底部侧；以及
第二封装体，包括多行焊球，
其中所述第二封装体经由所述多行焊球附着到所述第一封装体的所述衬底层的所述顶部侧的所述基本上平坦的表面。
2.根据权利要求1所述的堆叠式封装体布置，还包括：
粘合剂层，位于所述裸片与所述衬底层之间，
其中所述粘合剂层将所述裸片附着到所述第二封装体的所述衬底层的所述底部侧。
3.根据权利要求1所述的堆叠式封装体布置，还包括：
键合焊盘，位于所述裸片的所述底部侧上；以及
衬底焊盘，位于所述第二封装体的所述衬底层的所述底部侧上，
其中所述裸片的所述键合焊盘经由接线耦合到所述衬底层的所述衬底焊盘以路由所述裸片的电信号。
4.根据权利要求1所述的堆叠式封装体布置，其中所述多行焊球包括第一焊球，并且所述堆叠式封装体布置还包括：
第二焊球，附着到所述衬底层的所述底部侧以将所述裸片电连接到所述第二封装体的所述衬底层；以及
下填充材料，位于所述第二焊球与所述第二封装体的所述衬底层之间。
5.根据权利要求1所述的堆叠式封装体布置，其中所述多行焊球包括第一焊球，并且所述堆叠式封装体布置还包括：
第二焊球，附着到所述第二封装体的底部侧；并且
所述第二焊球位于所述第二封装体的外围周围以由此形成球栅阵列。
6.根据权利要求1所述的堆叠式封装体布置，其中
所述多行焊球包括第一焊球；
所述衬底层包括第一衬底层；
所述第一封装体包括布置于第二裸片旁边的第一裸片；并且
所述第一裸片和所述第二裸片中的每个裸片经由第二焊球连接到所述第一封装体中的第二衬底层。
7.根据权利要求1所述的堆叠式封装体布置，还包括：
热界面材料，附着到所述裸片的底部侧。
8.根据权利要求7所述的堆叠式封装体布置，还包括：
热传导材料，附着到所述热界面材料。
9.根据权利要求8所述的堆叠式封装体布置，其中所述热界面材料包括膜、油脂成分或者下填充材料之一。
10.根据权利要求1所述的堆叠式封装体布置，还包括：
附着到所述裸片的底部侧的(i)插入体或者(ii)印刷电路板之一。
11.根据权利要求1所述的堆叠式封装体布置，其中：
所述多行焊球包括第一多行焊球；
所述堆叠式封装体布置还包括第三封装体，所述第三封装体包括第二多行焊球；
所述第一封装体经由所述第一多行焊球附着到所述第二封装体的所述基本上平坦的表面；并且
所述第三封装体经由所述第二多行焊球附着到所述第二封装体的所述基本上平坦的表面。
12.根据权利要求1所述的堆叠式封装体布置，其中所述多行焊球包括第一焊球，并且所述堆叠式封装体布置还包括：
第二焊球，附着到所述衬底层的所述底部侧和所述裸片的顶部侧；以及
位于所述裸片中的多个硅通孔，其中所述多个硅通孔分别在至少一些所述第二焊球与多个第三焊球之间延伸，所述多个第三焊球附着到所述底部封装体的底部侧。
13.一种方法，包括：
提供包括衬底层的第一封装体，其中所述衬底层包括(i)顶部侧和(ii)与所述顶部侧相对的底部侧，其中所述衬底层的所述顶部侧限定基本上平坦的表面，并且其中所述第一封装体还包括耦合到所述衬底层的所述底部侧的裸片；
提供具有多行焊球的第二封装体，所述多行焊球附着到所述第二封装体的底表面；并且
经由所述第二封装体的所述多行焊球将所述第二封装体附着到所述第一封装体的所述基本上平坦的表面。
14.根据权利要求13所述的方法，其中将所述裸片附着到所述衬底层的所述底部侧包括经由粘合剂层将所述裸片附着到所述衬底层的所述底部侧。
15.根据权利要求13所述的方法，其中所述多行焊球包括第一焊球，并且将所述裸片附着到所述衬底层的所述底部侧包括经由第二焊球将所述裸片附着到所述衬底层的所述底部侧。
16.根据权利要求15所述的方法，还包括：
在位于(i)所述第二焊球之间以及(ii)所述裸片与所述第一封装体的所述衬底层的所述底部侧之间的空间之间提供下填充材料。
17.根据权利要求13所述的方法，还包括：
在所述裸片上提供键合焊盘，其中所述键合焊盘定位于所述裸片的底部侧上；
在所述衬底层上提供衬底焊盘，其中所述衬底焊盘定位于所述第一封装体的所述衬底层的所述底部侧上；并且
经由接线键合工艺将所述裸片上的所述键合焊盘耦合到所述衬底层上的所述衬底焊盘，以由此路由所述裸片的电信号。
18.根据权利要求13所述的方法，其中所述多行焊球包括第一焊球，并且所述方法还包括：
将第二焊球附着到所述第一封装体的底部侧，
其中所述第二焊球定位于所述第一封装体的右侧和左侧。
19.根据权利要求13所述的方法，还包括：
将热界面材料附着到所述裸片的底部侧。
20.根据权利要求13所述的方法，其中所述多行焊球包括第一焊球，并且所述方法还包括：
在所述衬底层的所述底部侧上附着第二焊球；
经由所述第二焊球将所述裸片附着到所述衬底层的所述底部侧；并且
在所述裸片中提供硅通孔以将所述第二焊球连接到第三焊球，所述第三焊球附着到所述第一封装体的底部侧。
21.根据权利要求13所述的方法，其中所述多行焊球包括第一焊球，并且所述方法还包括：
将第二焊球附着到所述裸片的底部侧；并且
将(i)插入体或者(ii)印刷电路板之一耦合到所述第二焊球。
22.根据权利要求13所述的方法，其中：
所述多行焊球包括第一多行焊球；并且
所述方法还包括：
提供具有第二多行焊球的第三封装体，所述第二多行焊球附着到所述第三封装体的底表面，并且
经由所述第二多行焊球将所述第三封装体附着到所述第一封装体的所述基本上平坦的表面。
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