CN102057481B - 具有电源和接地通孔的封装 - Google Patents

具有电源和接地通孔的封装 Download PDF

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Publication number
CN102057481B
CN102057481B CN200980122475.5A CN200980122475A CN102057481B CN 102057481 B CN102057481 B CN 102057481B CN 200980122475 A CN200980122475 A CN 200980122475A CN 102057481 B CN102057481 B CN 102057481B
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substrate
conductive
package substrate
integrated circuit
die attach
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CN102057481A (zh
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Q·H·洛
C·郭
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Avago Technologies General IP Singapore Pte Ltd
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Infineon Technologies North America Corp
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Abstract

一种丝焊设计集成电路具有衬底，该衬底具有正面和相反的背面。电路被设置在正面上。导电通孔被设置成从正面穿过衬底到背面，且电连接至电路，以使导电通孔仅为电路提供电源和接地服务。焊盘被设置在正面上，且电连接至电路以使焊盘仅为该电路提供信号通信。

Description

具有电源和接地通孔的封装
技术领域
本发明涉及集成电路领域。更具体地，本发明涉及用于集成电路的封装。
背景技术
在丝焊集成电路14中，焊盘22位于芯片14的周边，如图1所示。焊盘22典型地包括用于电源连接(电源)、接地连接(接地)以及信号连接的焊盘。集成电路14典型地被安装至封装衬底12，且丝焊连接在集成电路14与封装衬底12之间形成。因此，封装衬底12也具有构成丝焊的接合结构24。来自集成电路14上的电源和接地连接的焊丝通常与环绕封装衬底12中的安装了集成电路14的那部分的电源环16和接地环18建立连接，该部分被称为管芯附连焊盘20。
如本文中所使用的术语“集成电路”包括诸如在单片半导电衬底上形成的那些器件，该衬底诸如由硅或锗之类的四族材料、或由砷化镓之类的III-V族化合物或此类材料的混合物形成的衬底。该术语包括所形成的诸如存储器和逻辑的所有类型的器件，以及诸如MOS和双极的此类器件的所有设计。该术语还包括诸如平板显示器、太阳能电池以及电荷耦合器件的应用。
集成电路14上的电源和接地焊盘22占据了大量空间。在具有4∶1∶1的信号：电源：接地焊盘比例的一些设计中，电源和接地焊盘22占据了集成电路14上的焊盘22的三分之一，从而显著增大了芯片14的尺寸。
随着集成电路技术的发展，越来越小的空间中包含了越来越多的晶体管和其它器件。即使这些器件本身可被较小的芯片尺寸容纳，给定集成电路中器件数量的增加也表明需要更多数量的焊盘22，从而需要更大的芯片尺寸来容纳附加的焊盘22。这与持续减小集成电路14的芯片尺寸的一般市场压力相抵触。
封装衬底12上的电源环16和接地环18以及集成电路14上的电源和接地焊盘22导致在不向集成电路制造和封装组件中冒险加入许多工艺(这会导致高得多的成本)的情况下减小芯片14或封装衬底12的尺寸非常困难。
减小焊盘22和焊指(bonding finger)24所需空间的一种方法是减小焊盘22之间的间距并减小焊指24之间的间距。然而，为了不影响焊接工艺和焊丝的机械因素，这些间距只能被减小那么多。另一方法是从丝焊封装10换成倒装焊封装。然而，倒装焊封装一般比丝焊封装贵。
因此，所需要的是至少部分地克服诸如上述那些问题的系统。
发明内容
上述和其它要求通过一种丝焊设计集成电路得以满足，该集成电路具有衬底，该衬底具有正面和相反的背面。电路被设置在正面上。导电通孔被设置成从正面穿过衬底到背面，且电连接至电路，以使导电通孔仅为电路提供电源和接地服务。焊盘被设置在正面上，且电连接至电路以使焊盘仅为该电路提供信号通信。
以此方式，消除了旧集成电路设计中专用于电源和接地连接的所有焊盘，并由导电通孔替换，这样在集成电路中需要少得多的空间。因为导电通孔与衬底的背面建立电连接，所以几乎没有衬底正面上的表面积被用于电源和接地连接。因此，可使集成电路小很多，或容纳更多数量的信号焊盘。
在根据本发明该方面的各实施例中，导电通孔仅被设置在衬底的中心位置和衬底的角落位置中的至少一个处。在一些实施例中，导电通孔各自包括从正面到背面的单个垂直镗孔。在一些实施例中，至少一个导电通孔被设置在衬底的角落位置，从而当该衬底被单片化时，仅至少一个导电通孔的原始大小的四分之一保留在该衬底中。
根据本发明的另一方面，描述了一种丝焊设计封装衬底，该衬底具有正面和背面，且管芯附连焊盘设置在该衬底的正面，其中该管芯附连焊盘基本用导电表面覆盖。导电表面包括至少一个电源表面和至少一个接地表面。导电焊指被设置在正面上的管芯附连焊盘外部，且电连接被设置在背面上。导电迹线被设置在正面与背面之间，并将正面上的焊指与导电表面电连接至背面上的电连接。
在根据本发明该方面的各个实施例中，至少一个电源表面包括四个电源表面，这四个电源表面中的每一个设置在管芯附连焊盘的四个角落位置中的每一个中。在一些实施例中，至少一个接地表面包括设置于管芯附连焊盘的至少一个中心部分中的仅一个接地表面。在一些实施例中，管芯附连焊盘不大于封装衬底被设计成要容纳的集成电路。
根据本发明的又一方面，描述了一种封装集成电路，该集成电路具有如上所述的丝焊设计集成电路、如上所述的丝焊设计封装衬底，其中该丝焊设计封装衬底的导电表面与丝焊设计集成电路的导电通孔建立连接，且导电焊丝在焊盘与焊指之间形成电连接。
附图简述
通过参照结合附图考虑的详细描述，本发明的其它优点将显而易见，附图未按比例绘制以更清楚地表现细节，在所有的若干附图中，相同附图标记表示相同元件，且其中：
图1是现有技术的封装衬底设计，其中描绘了管芯附连焊盘、电源和接地环以及焊指。
图2是根据本发明一实施例的集成电路，其中描绘了导电通孔的三个位置以及用于信号连接的焊盘。
图3是根据本发明一实施例的不具有电源或接地环的封装衬底，其中描绘了较小的管芯附连焊盘和较多数量的焊指。
图4是根据本发明一实施例的封装集成电路的横截面，其中描绘了具有通过丝焊连接到封装衬底的信号连接与通过集成电路背面上的导电通孔到封装衬底的电源和接地连接的集成电路。
详细描述
现在参照图2，且根据本发明诸实施例，集成电路14被制造成具有设置在芯片14的一个或多个位置处的硅直通孔(TSV)26，诸如位于集成电路中心处或位于集成电路14的角落处。TSV 26a的角落位置可以整个位于芯片14的周边内，或被设置成使TSV 26b在集成电路14被单片化时切割成四分之一，以此方式使单个TSV 26b可由四个集成电路14的电路(共用公共角落位置的四个电路)共用，这四个集成电路在被单片化时变成四个独立的集成电路14。
TSV 26提供从设置在集成电路14的上表面上的电路到形成集成电路14的衬底的背面的导电通路。根据本发明，仅电源和接地连接通过TSV 26路由出去，因此在芯片14上不需要电源或接地焊盘22。因此，过去用于电源和接地焊盘22的所有空间现在被释放至其它用途，诸如使芯片14更小、增大用于信号连接的焊盘22的数量、增大集成电路14中的器件数量、或上述用途的组合。
如图3所述，封装衬底12被修改成具有设置在封装衬底12的管芯附连焊盘20中的TSV 26下方的导电表面28、30。在一些实施例中，导电表面28和30可与TSV 26对准，且基本不大于TSV 26，当芯片14被安装到封装衬底12时TSV 26与导电表面28和30建立电接触。然而，在其它实施例中，实际上封装衬底12的管芯附连焊盘20的整个表面被转换成导电表面28和30的图案，这使得芯片14与封装衬底12对准的重要性小得多。
导电表面28和30优选彼此电绝缘，以按照需要不产生电源和接地交叉，或不同电压的电源的交叉等。通过按照这种方式使用管芯附连焊盘20的较大部分，单个封装衬底设计12能容纳不同大小的集成电路14或具有不同TSV 26布置的集成电路设计14。导电表面28和30以及焊指24被路由至封装衬底12的另一面上的电连接。
与以上关于芯片12所描述的相似，可从封装衬底12消除电源16和接地18的焊环，从而在封装衬底12的表面上提供可用空间量的增加。在电源环16和接地环18被消除的情况下，用于信号连接的焊指24可更靠近管芯附连焊盘20，从而在封装衬底12的周边产生附加空间。该附加空间可用于使封装衬底12更小、增多可用于信号连接的焊指24的数量(诸如通过增加焊指24的附加环)，或这两者的组合。
因为也可使集成电路14更小，从而减小了管芯附连焊盘20的尺寸，所以安装在较小封装衬底12上的较小集成电14的总尺寸可被显著减小。此外，将焊指24移至更接近集成电路14减少了丝焊所需的焊丝量，从而提高了连接的电性能，并降低了给定封装集成电路10所需的焊丝的成本。较短的电源和接地连接还增强了热耗散和对由高级集成电路技术所产生的较大功率的处理。
现在参照图4，描述了根据本发明实施例的封装集成电路10的横截面，其中集成电路14具有通过丝焊连接30到封装衬底12的信号连接以及通过集成电路14背面上的导电通孔26到封装衬底12的电源和接地连接。电源和接地连接可诸如通过设置在TSV 26与导电表面28和30之间的各向异性导电环氧树脂34来形成。图4中还描绘了设置在封装衬底12的正面与背面之间的导电迹线38的表示。在本发明各实施例中设置了诸如球焊(已描述)和插针(未描述)的封装连接40。
集成电路14可诸如通过环氧化物底层填充材料36附连至封装衬底12的管芯附连焊盘20。诸如环氧化物的密封剂44被用于将集成电路14密封至封装衬底12，并保护该集成电路14和焊丝30。在一个实施例中，电源连接伸出至封装衬底12的边缘或角落，如44处所呈现，而接地连接伸出至封装衬底12的中心，如42处所呈现。
对本发明的优选实施例的上述描述以被呈现用于说明和描述的目的。它们不旨在穷举或将本发明限制为所公开的精确形式。根据上述示教，明显的修改和变化是可能的。选择和描述了实施例以尽量提供本发明的原理的最佳说明，从而使本领域普通技术人员能使各实施例中的本发明以及各种修改适用于所构想的特定用途。所有此类修改和变型在如由所附权利要求限定的本发明的范围内，本发明的范围根据其被清楚地、合法地以及公正地赋予的宽度来解释。

Claims (11)

1.一种丝焊设计封装衬底，包括：
具有正面和背面的衬底，
设置在所述衬底的正面上的管芯附连焊盘，所述管芯附连焊盘基本用导电表面覆盖，所述导电表面包括至少一个电源表面和至少一个接地表面，
设置在所述正面上的所述管芯附连焊盘之外的导电焊指，
设置在所述背面上的电连接，以及
设置在所述正面与所述背面之间的导电迹线，所述导电迹线将所述正面上的所述焊指和导电表面电连接至所述背面上的电连接。
2.如权利要求1所述的丝焊设计封装衬底，其特征在于，所述至少一个电源表面包括四个电源表面，这四个电源表面中的每一个设置在所述管芯附连焊盘的四个角落位置中的每一个中。
3.如权利要求1所述的丝焊设计封装衬底，其特征在于，所述至少一个接地表面包括设置于所述管芯附连焊盘的至少一个中心部分中的仅一个接地表面。
4.如权利要求1所述的丝焊设计封装衬底，其特征在于，所述管芯附连焊盘不大于所述封装衬底被设计成要容纳的集成电路。
5.一种封装集成电路，包括：
丝焊设计集成电路，包括：
具有正面和相反的背面的集成电路衬底，
设置在所述集成电路衬底的正面上的电路，
设置成从所述集成电路衬底的正面穿过所述集成电路衬底到所述集成电路衬底的背面的导电通孔，所述导电通孔电连接至所述电路，以使所述导电通孔仅为所述电路提供电源和接地服务，以及
设置在所述集成电路衬底的正面上的焊盘，所述焊盘电连接至所述电路，以使所述焊盘仅为所述电路提供信号通信，
丝焊设计封装衬底，包括：
具有正面和背面的封装衬底，
设置在所述封装衬底的正面上的管芯附连焊盘，所述管芯附连焊盘基本用导电表面覆盖，所述导电表面包括至少一个电源表面和至少一个接地表面，其中所述丝焊设计封装衬底的导电表面与所述丝焊设计集成电路的导电通孔建立电连接，
设置在所述封装衬底的正面上的所述管芯附连焊盘之外的导电焊指，
设置在所述封装衬底的背面上的电连接，以及
设置在所述封装衬底的正面与所述封装衬底的背面之间的导电迹线，所述导电迹线将所述封装衬底的正面上的焊指和导电表面电连接至所述封装衬底的背面上的电连接，以及
在所述焊盘与所述焊指之间形成电连接的导电焊丝。
6.如权利要求5所述的封装集成电路，其特征在于，所述导电通孔仅被设置在所述集成电路衬底的中心位置和所述集成电路衬底的角落位置中的至少一个处。
7.如权利要求5所述的封装集成电路，其特征在于，所述导电通孔中的每一个包括从所述集成电路衬底的正面到所述集成电路衬底的背面的单个垂直镗孔。
8.如权利要求5所述的封装集成电路，其特征在于，至少一个所述导电通孔被设置在所述集成电路衬底的角落位置，从而当所述集成电路衬底被单片化时，仅所述至少一个导电通孔的原始尺寸的四分之一保留在所述集成电路衬底中。
9.如权利要求5所述的封装集成电路，其特征在于，所述至少一个电源表面包括四个电源表面，这四个电源表面中的每一个设置在所述管芯附连焊盘的四个角落位置中的每一个中。
10.如权利要求5所述的封装集成电路，其特征在于，所述至少一个接地表面包括设置于所述管芯附连焊盘的至少一个中心部分中的仅一个接地表面。
11.如权利要求5所述的封装集成电路，其特征在于，所述管芯附连焊盘不大于所述丝焊设计集成电路。
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JP2013085007A (ja) 2013-05-09
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TWI453875B (zh) 2014-09-21
EP2338169A1 (en) 2011-06-29
KR20110053233A (ko) 2011-05-19
JP5350550B2 (ja) 2013-11-27
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US8350379B2 (en) 2013-01-08
CN102057481A (zh) 2011-05-11

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