CN202534641U - 已封装电子器件 - Google Patents

已封装电子器件 Download PDF

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Publication number
CN202534641U
CN202534641U CN2009901002420U CN200990100242U CN202534641U CN 202534641 U CN202534641 U CN 202534641U CN 2009901002420 U CN2009901002420 U CN 2009901002420U CN 200990100242 U CN200990100242 U CN 200990100242U CN 202534641 U CN202534641 U CN 202534641U
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China
Prior art keywords
pad
tsv
electronic device
terminal pins
hole
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CN2009901002420U
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English (en)
Inventor
T·D·博尼费尔德
G·P·莫里森
R·邓恩
S·S·肖汉
M·穆尔图扎
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

本实用新型公开一种已封装电子器件，其包括具有引线框架的封装，该引线框架具有管芯焊盘和互相之间电隔离并且与该管芯焊盘电隔离的多个引线管脚；以及第一集成电路管芯，其以面朝上配置方式位于该引线框架上；该第一集成电路管芯包括：衬底，其具有顶部表面和底部表面；该顶部表面包括电路，该电路具有输入焊盘、输出焊盘、电源焊盘和地焊盘；以及具有导电材料的多个通孔，该多个通孔从该顶部表面穿过该衬底延伸到该底部表面。本实用新型公开的已封装的电子器件改善了地连接和热耗散。

Description

已封装电子器件
技术领域
本发明的实施例涉及具有面朝上组装在封装中的管芯的集成电路(IC)器件，所述管芯包括穿透衬底通孔(TSV)。 
背景技术
封装面积(package footprint)的减小日益变得重要。如本领域中已知的，无引线封装(例如方形扁平无引脚封装(QFN))与引线封装相比提供减小的尺寸和改进的性能，所述引线封装具有从封装侧面延伸出去的引脚。常规组装使用多个引线键合，用于将IC管芯在电气上耦合到暴露在封装体的底部周边表面上的金属端。如本领域中已知的，在器件工作期间，引线键合表现为感性并且可以降低器件性能，特别是在高频工作期间。 
消除引线键合的替换解决方案是将IC管芯倒置组装为倒装芯片。然而，倒装芯片方法不能够将IC管芯或其他元件堆叠到封装内的主管芯(即与封装基板(例如PCB)邻近的管芯)的面上。而且，倒装芯片布置会明显减小通常在特定封装中可用的热耗散路径，例如QFN封装通常提供的大面积中心引线框架管芯焊盘，为了接触，所述管芯焊盘被暴露在封装的底部。 
发明内容
本发明的实施例包括已封装的电子器件，该电子器件包括含多个TSV的IC管芯。IC管芯被面朝上键合到引线框架，生成用于其I/O焊盘、地焊盘和(通常还有)电源焊盘的互连，这些焊盘在IC管芯的有源顶部含半导体的表面上并且由TSV耦合到封装的引线框架。通过本发明的实施例，消除了常规面朝上管芯组装器件所需的键合引线，导致了器件性能的改善，特别是对于高频工作。IC管芯和引线框架通常被配置为使得IC管芯的TSV与管芯焊盘和引线管脚对准。然而，可以在IC管芯的底部上使用重定向金属层(RDL)来去除对准需求。
在本发明的实施例中，不像倒装芯片布置，IC管芯的底部表面被键合到引线框架的管芯焊盘(其可以是接地的管芯焊盘)。与倒装芯片布置相比，通过低电阻路径和低热阻路径耦合到接地管芯焊盘的接地TSV的存在改善了地连接(例如到地的电阻减小)和热耗散。 
如在此使用的，术语“TSV”被宽泛地定义为包括具有用导电填充材料(例如金属(例如铜或钨)或简并掺杂的半导体(例如n+或p+掺杂的硅))填充的穿透通孔的任何晶圆或IC管芯。衬底可以是含硅的衬底，例如体硅衬底、锗硅衬底或绝缘体上的硅(SOI)衬底。TSV通孔提供从晶圆或IC管芯的底部延伸并且延伸到顶部晶圆或管芯表面上的接触层或任何一个金属互连层的电接触。TSV通常可以是由通孔在先处理或通孔在后处理来形成的。 
在本发明的一个实施例中，封装包括引线框架，该引线框架包括管芯焊盘和多个引线管脚，所述多个引线管脚包括围绕该管芯焊盘的、互相电隔离并且与该管芯焊盘电隔离的第一、第二和第三引线管脚。至少第一IC管芯以面朝上配置方式被组装在引线框架上。IC管芯包括衬底，该衬底具有有源顶部含半导体的表面和底部表面，其中顶部含半导体的表面包括集成电路，该集成电路具有至少一个输入焊盘、至少一个输出焊盘、至少一个电源焊盘和至少一个地焊盘。IC管芯包括多个TSV，所述多个TSV包括导电填充材料和围绕该导电填充材料的介电衬垫，其从含顶部半导体的表面(例如接触层或金属层)延伸到至少底部表面，并且通常是从底部表面延伸出一个距离，该距离在此被称为顶端高度。对于常规管芯焊盘布置，多个TSV通常包括第一TSV、第二TSV、第三TSV和第四TSV，所述第一TSV将输入焊盘耦合到第一引线管脚，所述第二TSV将输出焊盘耦合到第二引线管脚，所述第三TSV将电源焊盘耦合到第三引线管脚，所述第四TSV将地焊盘耦合到管芯焊盘。 
在一个实施例中，公开了一种已封装的电子器件，其特征在于，包括：封装，其包括引线框架，所述引线框架具有管芯焊盘和互相之间电隔离并且与所述管芯焊盘电隔离的多个引线管脚；以及第一集成电路管 芯，其以面朝上配置方式位于所述引线框架上；所述第一集成电路管芯包括：衬底，其具有顶部表面和底部表面；所述顶部表面包括电路，所述电路具有输入焊盘、输出焊盘、电源焊盘和地焊盘；以及具有导电材料的多个通孔，所述多个通孔从所述顶部表面穿过所述衬底延伸到所述底部表面；所述多个通孔中第一通孔和第二通孔的导电材料将所述输入焊盘和输出焊盘穿过所述衬底耦合到所述多个引线管脚中相应的第一引线管脚和第二引线管脚；以及所述多个通孔中第三通孔和第四通孔的导电材料将所述电源焊盘和所述地焊盘耦合到所述多个引线管脚中相应的第三引线管脚和第四引线管脚，或耦合到所述管芯焊盘的相应的第一部分和第二部分；所述第一、第二和第三通孔包括围绕所述导电材料的介电衬垫。 
在另一个实施例中，导电材料存在于从通孔突出的集成顶端，其中突出的顶端高度在1μm和50μm之间。 
在另一个实施例中，介电衬垫延伸到突出的集成顶端的侧壁上一定距离，距离是顶端高度的至少1％。 
在另一个实施例中，多个通孔中的其它通孔将地焊盘耦合到多个引线管脚的同一额外引线管脚或相应的不同的额外引线管脚，或耦合到管芯焊盘的同一部分或相应的不同的部分。 
在另一个实施例中，第一集成电路管芯至少部分地延伸在多个引线管脚上；第一、第二、第三和第四通孔分别与第一、第二、第三和第四引线管脚对准。 
在另一个实施例中，管芯焊盘包括分离的管芯焊盘；以及电源焊盘和地焊盘被耦合到分离的管芯焊盘提供的管芯焊盘的相应的不同的第一和第二部分。 
在另一个实施例中，突出的集成顶端包括焊料，焊料包括键合到突出的集成顶端的末端的盖层。 
在另一个实施例中，第一集成电路管芯包括金属，金属包括布置在底部表面上的再分布层，再分布层包括至少一个键合焊盘和至少一个金属迹线，金属迹线用于将多个通孔的至少一个的导电材料耦合到键合焊盘，并且键合焊盘接触多个引线管脚的至少一个。 
在另一个实施例中，多个通孔分别与多个引线管脚直接对准。 
在另一个实施例中，第二集成电路管芯，第二集成电路管芯以倒装芯片配置方式被安装在第一集成电路管芯的顶部上。 
附图说明
图1A是根据本发明的实施例的已封装的电子器件沿着封装的中心看去的剖面图，该电子器件包括TSV，所述TSV将IC管芯的顶部表面上的焊盘连接到封装的引线管脚(用于I/O连接)以及连接到封装的管芯焊盘(用于地连接)。 
图1B是根据本发明的实施例的已封装的电子器件沿着封装的一个边缘看去的剖面图，该电子器件包括TSV，所述TSV将IC管芯的顶部表面上的焊盘连接到封装的引线管脚(用于I/O连接)以及连接到封装的管芯焊盘(用于地连接)。 
图1C示出了根据本发明的实施例的示例性引线框架，用于面朝上安装含TSV的IC管芯，这里根据本发明的实施例，TSV提供信号I/O、电源(P)和地(G)，其将IC管芯(未示出)的顶部面上的I/O、P和G节点在电气上连接到用于I/O、P和G的引线框架焊盘/管脚。 
图1D示出了根据本发明的实施例的分离的管芯焊盘引线框架设计，含TSV的IC可以使用该设计形成已封装的电子器件。 
图1E示出了另一个根据本发明的实施例的分离的管芯焊盘引线框架设计，含TSV的IC可以使用该设计形成已封装的电子器件。 
图2是根据本发明的实施例的已封装的电子器件沿着封装的中心看去的剖面图，该电子器件包括TSV，所述TSV将第一IC管芯的顶部表面上的焊盘连接到封装用于I/O连接的引线管脚，以及连接到用于地连接的管芯焊盘，其中堆叠的第二IC管芯或其他电子元件被面对面地安装到该第一IC管芯。 
图3示出了根据本发明的实施例得到的电子器件结构的剖面图，该电子器件结构通过在金属覆盖的突出的集成TSV顶端之间生成互连而形成，所述TSV顶端被焊接到封装的引线框架的管芯焊盘。 
图4是根据本发明的实施例的管芯堆叠的电子器件沿着封装的中心看去的剖面图，该电子器件包括图1A中所示的含TSV的IC管芯并且在其底部表面上具有附加的金属RDL，所述IC管芯被安装到基于图 1C中所示的引线框架的、包括用于P和G的分离的管芯焊盘的引线框架。 
具体实施方式
本发明的实施例描述了已封装的电子器件，该电子器件包括封装，该封装包括引线框架，该引线框架包括管芯焊盘和面朝上安装在该引线框架上的第一IC管芯。IC管芯包括多个TSV，所述TSV包括导电填充材料，该材料提供从IC管芯(其包括集成电路)的顶部面上的I/O焊盘、地焊盘和(通常是)电源焊盘穿到管芯的底部面、到达封装的引线框架管脚和管芯焊盘的互连。TSV可以包括突出的集成TSV顶端，该TSV顶端包括导电填充材料，所述材料延伸超出IC管芯的底部一个顶端长度。如在此使用的，突出的集成TSV顶端包括导电填充材料和可选的衬垫，两者均从衬底的底部表面突出。 
顶端长度通常是1μm到50μm，典型地是至少5μm。TSV还可以包括衬垫，典型的是介电衬垫，这里期望TSV电隔离。在这个详细说明书的结尾，描述了一种用于形成TSV的示例性方法，用于形成具有介电衬垫TSV的管芯，所述TSV具有突出的集成TSV顶端，该TSV顶端从管芯的底部面突出，并且具有沿着顶端长度的一部分的介电顶端衬垫。然而，本发明的实施例也可以使用其他的工艺顺序。 
在整个该申请中，术语“引线框架”被定义为通过环氧材料或焊球基体在机械上附着到半导体管芯并且有助于将集成电路在电气上连接到另一电子元件的封装成分。典型地，工业中的引线框架是由导电金属例如铜或合金-42制成的，并且通常包含银、金或钯的薄涂层。然而，在该申请中，术语引线框架还指代面积阵列封装中常用的有机衬底或内插器。电子衬底或内插器由具有导电路径的绝缘材料组成，所述导电路径穿过内插器从一个表面延伸到相对的表面，形成电气入口和出口路径。 
图1A是根据本发明的实施例的已封装的电子器件100沿着封装的中心看去的剖面图，该电子器件100包括封装的引线框架130和面朝上安装在引线框架130上的IC管芯105。IC管芯105包括衬底104，该衬底具有有源顶部含半导体的顶部表面118和底部表面119。焊盘(来自多层金属化或接触层中的任何一层)115、116和117(a)-(d)耦合到功能电路 120的相应的节点，所述功能电路通常形成在顶部表面118之中或之上。 
引线框架130包括多个I/O信号引线框架管脚，所述管脚包括管脚131、电源管脚132和位于中心的、用于安装IC管芯105并且将其接地的管芯焊盘135。可以看出，IC管芯105延伸超出管芯焊盘135，到达引线框架管脚131和132。多个TSV(总的称为TSV 110)包括第一TSV 110(a)、第二TSV 110(b)和TSV 110(c)-(f)，所述第一TSV 110(a)将IC管芯105的焊盘115(例如VDD焊盘)耦合到引线管脚132，所述第二TSV 110(b)将另一焊盘116(例如输入或输出焊盘)耦合到引线管脚131，所述TSV 110(c)-(f)各自耦合其他焊盘117(a)-(d)以安装管芯焊盘135并且将其接地，用于IC管芯105的地连接。 
TSV 110包括导电填充材料(例如铜)中心部分111和用于使导电填充材料111在电气上与衬底104绝缘的外部介电衬垫112，并且TSV 110从含顶部半导体的表面118(例如接触层或金属层)延伸到至少底部表面119，且具有IC管芯105的背面上所示的暴露的突出的集成TSV顶端113，用于连接到引线框架130。可以看到，介电衬垫112延伸到突出的集成TSV顶端113的侧壁上。突出的集成TSV顶端113通常具有5微米到10微米的顶端高度，该高度从衬底104的底部表面119测量起。 
导电的管芯附着粘合或焊接区域141被示为与TSV 110成横向并且位于IC管芯105的底部表面119和引线框架130的管芯焊盘135以及引线管脚之间，用于改善TSV 110和引线框架130之间的电气和物理连接。在一个实施例中，例如对于QFN封装，使用导电粘合材料或含焊料的材料将导电的管芯附着材料(例如Ag填充的环氧树脂)置于管芯焊盘135和引线框架130的引线131、132上。与仅在管芯焊盘的部分上使用管芯附着粘合剂的常规QFN封装相比，这是不同的。替换地，如下面所描述的，TSV顶端110可以具有含焊料的盖，使得引线框架不需要焊料。在该实施例中，所示的成型塑料(mold compound)142还可以用作底部填充剂，以进一步将IC管芯105粘合到引线框架130。这种材料类别通常被称为成型底部填充剂。 
可以看到，引线框架130的I/O引线131和132的至少一部分延伸在IC管芯105之下。可以共同设计IC管芯105和引线框架130，以将TSV 110置于IC管芯105上某个位置，该位置与引线框架管脚131、132 对准。替换地，如下面相对图4所描述的，IC管芯可以包括RDL，在组装之前使用BEOL晶圆级工艺生成所述RDL，以避免需要共同设计IC的TSV 110和引线框架130，使得TSV 110的位置均与引线框架130的管脚对准。 
虽然没有示出，但是引线框架130可以包括在TSV 110的位置处的、在该引线框架顶部表面中的凹陷(dimple)，以有助于正确的放置和机械稳定性。而且，引线框架130可以具有与TSV的顶端上的表面处理(finish)兼容的表面处理，以有助于在TSV顶端113和引线框架130之间形成有力可靠的接头。例如，引线框架可以具有焊料表面处理，TSV顶端113可以是熟知键合到焊料的裸铜。替换地，在一个特定的实施例中，TSV顶端113和引线框架130可以都具有将很好键合在一起的Ni/Pd/Au表面处理。 
在一个实施例中，封装包括无引线封装，例如QFN、无引线QFP、无引线SOIC或无引线TSOP。在QFN实施例中，引线框架和封装设计可以将IC管芯以部分覆盖的方式放置在引线框架的引线管脚上，但是仍然保持大部分管芯面积触及接地的管芯安装焊盘。对于QFN，如本领域已知的，管芯安装焊盘也被暴露在封装的底部，以便焊料附着到印制电路板(这对于QFN封装是常见的)，以获得良好的热量耗散。在另一实施例中，封装包括引线封装，例如SOIC、引线QFP或引线TSOP。 
图1B是图1A中所示的本发明的已封装的电子器件100沿着封装的一个边缘看去的剖面图150，该电子器件包括沿着封装的中心的引线框架130。TSV 100被示为将IC管芯105的顶部表面上的焊盘115、116分别连接到用于P和I/O连接的封装的引线管脚132、131。在图1B中提供的边缘视图中没有示出到引线框架130的中心的、用于接地的管芯焊盘的TSV连接。 
图1C示出了根据本发明的实施例的示例性引线框架180，该引线框架用于面朝上安装含TSV的IC管芯，这里TSV提供将IC管芯(未示出)的顶部面上的I/O、P和G节点在电气上连接到用于信号I/O、P和G的引线框架焊盘/管脚的I/O、P和G。引线框架180包括分离的管芯焊盘170和用于信号I/O连接的多个较小的周边焊盘190，所述管芯焊盘具有多个相对大的电源(P)条和地(G)条175，使得能够进行高功率/电 流密度应用。P和G条175在面积上足够大(通常是较小周边焊盘190的面积的至少10x(例如＞50x))，以容纳多个TSV。例如，如果IC的所有P TSV管脚和G TSV管脚被组成/聚集在一起，例如通过背面RDL耦合在一起，则它们都可以连接到P和G条提供的较大的管芯焊盘区域，这将改善封装热性能，这对于高功率封装可以是特别有用。 
根据本发明的实施例以面朝上配置使用含TSV的IC所获得的明显优势是，由于为P/G连接所分配的TSV通常将非常小并且因此使用较少的管芯空间，因此不再需要为了大的矩形P/G焊盘而用完IC的BEOL(金属)层中的管芯空间，所述大的矩形P/G焊盘是标准的面朝下FC-QFN封装中所需的。虽然没有示出，但是IC通常将包括通常与P和G条175和周边焊盘190对准的TSV，虽然IC背面上的RDL层可以放松对准要求。如本领域已知的，这些条延伸到封装边缘作为要焊接到封装基板(例如客户的PCB)的分开的引线管脚，以耦合公共连接。 
图1D和1E各自示出了根据本发明的实施例的分离的管芯焊盘引线框架设计150和160，根据本发明的实施例的含TSV的IC可以使用所述引线框架设计来形成已封装的电子器件。所示的P和G焊盘与图1D和1E中示为“S”的周边信号焊盘相比是大的焊盘，以提供改进的热耗散。所示的P和G焊盘可以被耦合到多个TSV。 
图2是根据本发明的实施例的已封装的电子器件200沿着封装的中心看去的剖面图，该电子器件包括TSV 110，所述TSV将图1A中所示的第一(主)IC管芯105的顶部表面上的焊盘连接到用于I/O和P连接的封装引线管脚131和132以及连接到用于地连接的管芯焊盘135，其中堆叠的第二IC管芯或其他电子元件240面对面安装到该第一IC管芯105。 
图3示出了根据本发明的实施例的得到的电子器件结构的剖面图，所述电子器件结构是通过在金属加盖的突出的集成TSV顶端之间生成互连来形成的，所述TSV顶端被焊接到封装的引线框架的管芯焊盘。介电底部填充粘合剂342填充在间隙区域中。金属盖被示为315。在这个实施例中，互连是通过如下方式生成的：导电盖315(例如Cu/焊料或焊料合金或Ni/焊料或焊料合金)加盖在TSV顶端113的末端上，所述TSV顶端可以通过焊料333被焊接到管芯焊盘135和管脚131和132，之后在 TSV顶端113旁的间隙区域中形成非导电底部填充粘合剂342。将焊料施加到TSV顶端113的示例性处理选择包括直接化学Sn镀或浸Sn镀、使用光刻胶的镀覆、Showa Denko Super Juffit应用工艺或Senju PPS-Powder Prepreg覆盖工艺(sheet process)。当含TSV的晶圆在合适的载体上时，可以对该晶圆实施这些工艺。 
在一个实施例中，焊接包括回流工艺以附着IC管芯，之后是毛细管型底部填充，用于在IC管芯的底部表面和引线框架之间、在TSV顶端旁的间隙区域中形成介电底部填充层。在另一个实施例中，该方法还包括在IC管芯的底部表面上布置层压型底部填充薄膜，并且该焊接包括同时回流/固化工艺。在又一个实施例中，该方法还包括将无流动型底部填充薄膜布置在管芯焊盘上，其中该焊接包括同时回流/固化工艺。 
图4是根据本发明的实施例的管芯堆叠的电子器件400沿着封装的中心看去的剖面图，该电子器件包括图1A中所示的IC管芯105，其包括具有突出的集成顶端113的TSV 110，所述顶端113将IC管芯105的顶部表面118上的焊盘连接到类似于图1C中所示的引线框架180的引线框架，所述IC管芯在其底部表面119上具有金属RDL，所述引线框架包括用于P和G连接的分离的管芯焊盘170和用于I/O连接的周边引线管脚190。所示的堆叠的管芯包括有源IC 415，其被示为附着到IC管芯105的倒装芯片。无源元件(L，R，C)420被示为堆叠在主IC管芯105上并且相对于IC 415布置在侧面。IC管芯105包括在其底部表面119上的RDL 419。虽然在图4中没有示出，但是可以提供额外的有源元件，以生成多芯片模块或SiP，或堆叠的管芯(例如在存储器IC的情况下)。 
在组装之前通常用BEOL晶圆级工艺来生成RDL 419。RDL 419可以连接任何一个TSV 110并且将横向迹线(trace)提供到IC管芯105的底部119上的金属焊盘421，其中金属焊盘421被布置在与要键合到的引线框架管脚对准的位置上，以避免将TSV与这些位置对准的共同设计要求。这个实施例可以提供更灵活的IC管芯设计。 
本发明的实施例可以使用各种组装选择。在一个实施例中，使用回流工艺来将IC管芯附着到引线框架，之后使用毛细管型底部填充。在另一个实施例中，将层压型底部填充薄膜应用到IC管芯上，并且将IC管芯键合到引线框架可以包括同时回流/固化工艺。在又一个实施例中，无 流动型底部填充被应用到管芯焊盘上，并且使用同时回流/固化工艺将IC管芯键合到引线框架。 
下面描述了用于形成具有介电衬垫TSV的IC管芯的示例性工艺顺序，所述TSV具有集成TSV顶端，所述顶端从管芯的底部面突出，并且具有沿着顶端高度的一部分的介电顶端衬垫。本发明的实施例也可以使用其他工艺顺序。 
通过以下步骤来常规形成嵌入式通孔在先TSV：从顶部面进行通孔刻蚀(例如通过RIE)，其深度小于衬底/晶圆的厚度，通过在该通孔中形成介电衬垫来架构通孔，之后用导电填充材料来填充通孔。通常还包括阻挡金属层(例如Ta或TaN)，并且在一些实施例中，通常还包括种子层(例如用于铜)。接着，通常背磨晶圆以暴露嵌入式TSV的顶端。相比之下，下面所描述的工艺是示例性多步化学刻蚀工艺，该工艺处理具有嵌入式通孔在先TSV的晶圆，以形成突出的集成TSV顶端，该工艺不使用机械刻蚀，以避免TSV顶端与研磨工具接触。在此所描述的多步化学刻蚀工艺完成衬底减薄处理，所述衬底减薄处理开始于背磨，接着典型的是化学机械抛光(CMP)，轻柔地去除(即非机械方式)嵌入式通孔在先TSV顶端的底部和机械去除工艺之后剩余的衬底的底部面之间的保护衬底的层，以形成突出的集成TSV顶端。 
本发明者发现，避免TSV顶端与背磨工具直接物理接触避免了或至少明显减小了对导电填充材料、扩散阻挡层金属(如果存在)和围绕TSV的介电衬垫的机械损伤，也减少了或消除了弄脏底部衬底表面上的导电填充材料(例如金属)。如在此所限定的，“化学刻蚀”是指无机械刻蚀的湿法或干法(例如等离子体)刻蚀。如果CMP工艺被配置为通过提供在晶圆材料(例如硅)和介电衬垫之间大于10∶1的选择比而类似于化学刻蚀的作用并且因此至多具有最小机械成分，则在此所使用的“无机械刻蚀的化学刻蚀”可以包括CMP。例如，在特定的布置中，不具有磨蚀粒子的CMP工艺(例如没有粒子具有大于等于硅石的莫氏硬度的莫氏硬度)可以提供最小机械成分。 
可以使用第一背面刻蚀、以相对于衬垫的选择比刻蚀晶圆的底部表面，以形成具有初始顶端高度为Hinitial的突出的集成TSV顶端。用于第一背面刻蚀的刻蚀选择比通常是足够高，以避免去除介电衬垫而暴露突 出的集成TSV顶端的导电填充材料。第一背面刻蚀通常具有晶圆材料(例如硅)和介电衬垫之间大于10∶1的选择比，典型的是100∶1到1000∶1，或更大。小于大约10的选择比通常将引起介电衬垫的过度损耗。 
第一背面刻蚀工艺可以包括多种湿法刻蚀选择，所述多种湿法刻蚀选择包括季铵碱(例如通常被称为TMAH的((CH3)4NOH；四甲基氨氢氧化物))、KOH、胆碱、酸(例如HF、硝酸、硫酸和磷酸)的混合物。替换地，通常也可以使用干法刻蚀工艺，例如含氟的等离子体刻蚀。作为另一替换，如果CMP被配置为提供晶圆材料(例如硅)和介电衬垫之间大于10∶1的选择比，则可以使用CMP。 
由第一背面刻蚀去除的晶圆的厚度范围通常是在晶圆内小于6％，其中晶圆之间平均变化小于5％。在第一背面刻蚀中所刻蚀的总的衬底量通常是从5μm到50μm。 
第二背面刻蚀用于从突出的集成TSV顶端的至少末端去除介电衬垫。这个处理可以包括湿法刻蚀工艺(例如HF或稀释的HF)或基于氟的等离子体刻蚀。介电衬垫可能从衬底的底部表面变得凹陷，在突出的集成TSV顶端的周边上形成介电衬垫凹口，因为通常以与晶圆(例如硅)的背面表面的刻蚀速率相比明显较大的刻蚀速率来去除介电衬垫。然而，第二背面刻蚀工艺可以被选择为以相对于刻蚀介电衬垫的速率足够高的速率来刻蚀衬底的底部表面，以避免或至少限制这类介电凹口的形成。 
第二背面刻蚀通常应该具有刻蚀介电衬垫和刻蚀导电填充材料之间大于2∶1的选择比，典型的是大于10∶1。低于大约2∶1的较低的选择比可以引起导电填充材料的过度损耗。 
由第二背面刻蚀去除的介电衬垫的厚度范围通常应该是在晶圆内小于10％，其中在晶圆之间平均变化小于10％。介电衬垫的总的刻蚀量通常是从0.2μm到10μm。 
第二背面刻蚀也可以是一系列两个或多于两个的刻蚀条件，其用来去除介电衬垫的全部厚度，以暴露突出的集成TSV顶端的导电填充材料的表面。导电填充材料的被暴露的表面通常应当是没有明显腐蚀(即氧化物)。如上面所指出的，第二背面刻蚀也可以被选择为去除突出的集成TSV顶端的导电填充材料的表面上的阻挡金属层(如果存在)。 
第三背面刻蚀用于从衬底的底部表面去除衬底材料(例如硅)，以实 现所期望的TSV顶端高度。如上面所描述的，顶端高度通常可以是从1μm到50μm的范围，并且典型的是依赖于特定封装设计的相隔距离(standoff distance)和用来将TSV键合到工件的焊点而选择。第三背面刻蚀工艺具有对导电填充材料的选择比，并且通常还具有对介电衬垫的选择比。得到的在集成TSV顶端上的介电衬垫(在此称为介电顶端衬垫)的高度具有高度Hdielectric。Hdielectric通常范围从0.1μm到50μm，并且典型的是顶端高度的10％到90％，例如3μm到顶端高度减去3μm。突出的集成TSV顶端可以包括暴露的顶端部分，其包括在突出的集成TSV顶端的末端上的暴露的导电填充材料。从而，暴露的顶端部分延伸超过介电顶端衬垫。 
与第一背面刻蚀类似，第三背面刻蚀工艺通常具有晶圆材料(例如硅)和介电衬垫之间大于10∶1的选择比，并且典型的是100∶1到1000∶1，或更大，并且可以包括具有各种选择的湿法刻蚀，所述各种选择包括TMAH、KOH、胆碱、酸(例如HF、硝酸、硫酸和磷酸)的混合物。替换地，通常可以使用干法刻蚀工艺，例如含氟的等离子体刻蚀。作为另一替换，如果CMP被配置为提供晶圆材料(例如硅)和介电衬垫之间大于10∶1的选择比，则可以使用CMP。 
第三背面刻蚀通常提供衬底(例如硅)刻蚀和TSV的导电填充材料之间大于2∶1的选择比，典型的是大于10∶1的选择比。较低的选择比可以引起导电填充材料的过度损耗。 
本发明的实施例可以被集成到多种工艺流程中，以形成多种器件和相关产品。半导体衬底可以包括在其中的各种元件和/或在其上的各种层。这些可以包括阻挡层、其他介电层、器件结构、有源元件和无源元件(包括源极区域、漏极区域、位线、基极、发射极、集电极、导电线、导电通孔等)。而且，本发明可以用在多种工艺中，包括双极、CMOS、BiCMOS和MEMS。 
本发明涉及的本领域技术人员应理解，有许多其他实施例和修改落入所主张的发明的范围内。 

Claims (10)

1.一种已封装的电子器件，其特征在于，包括：
封装，其包括引线框架，所述引线框架具有管芯焊盘和互相之间电隔离并且与所述管芯焊盘电隔离的多个引线管脚；以及
第一集成电路管芯，其以面朝上配置方式位于所述引线框架上；所述第一集成电路管芯包括：
衬底，其具有顶部表面和底部表面；所述顶部表面包括电路，所述电路具有输入焊盘、输出焊盘、电源焊盘和地焊盘；以及
具有导电材料的多个通孔，所述多个通孔从所述顶部表面穿过所述衬底延伸到所述底部表面；所述多个通孔中第一通孔和第二通孔的导电材料将所述输入焊盘和输出焊盘穿过所述衬底耦合到所述多个引线管脚中相应的第一引线管脚和第二引线管脚；以及所述多个通孔中第三通孔和第四通孔的导电材料将所述电源焊盘和所述地焊盘耦合到所述多个引线管脚中相应的第三引线管脚和第四引线管脚，或耦合到所述管芯焊盘的相应的第一部分和第二部分；所述第一、第二和第三通孔包括围绕所述导电材料的介电衬垫。
2.根据权利要求1所述的已封装的电子器件，其特征在于，其中所述导电材料存在于从所述通孔突出的集成顶端，其中突出的顶端高度在1μm和50μm之间。
3.根据权利要求2所述的已封装的电子器件，其特征在于，其中所述介电衬垫延伸到所述突出的集成顶端的侧壁上一定距离，所述距离是所述顶端高度的至少1％。
4.根据权利要求1所述的已封装的电子器件，其特征在于，其中所述多个通孔中的其它通孔将所述地焊盘耦合到所述多个引线管脚的同一额外引线管脚或相应的不同的额外引线管脚，或耦合到所述管芯焊盘的同一部分或相应的不同的部分。 
5.根据权利要求1所述的已封装的电子器件，其特征在于，其中所述第一集成电路管芯至少部分地延伸在所述多个引线管脚上；所述第一、第二、第三和第四通孔分别与所述第一、第二、第三和第四引线管脚对准。
6.根据权利要求1所述的已封装的电子器件，其特征在于，其中所述管芯焊盘包括分离的管芯焊盘；以及所述电源焊盘和所述地焊盘被耦合到所述分离的管芯焊盘提供的所述管芯焊盘的所述相应的不同的第一和第二部分。
7.根据权利要求2所述的已封装的电子器件，其特征在于，其中所述突出的集成顶端包括焊料，所述焊料包括键合到所述突出的集成顶端的末端的盖层。
8.根据权利要求7所述的已封装的电子器件，其特征在于，其中所述第一集成电路管芯包括金属，所述金属包括布置在所述底部表面上的再分布层，所述再分布层包括至少一个键合焊盘和至少一个金属迹线，所述金属迹线用于将所述多个通孔的至少一个的导电材料耦合到所述键合焊盘，并且所述键合焊盘接触所述多个引线管脚的至少一个。
9.根据权利要求8所述的已封装的电子器件，其特征在于，其中所述多个通孔分别与所述多个引线管脚直接对准。
10.根据权利要求9所述的已封装的电子器件，其特征在于，还包括第二集成电路管芯，所述第二集成电路管芯以倒装芯片配置方式被安装在所述第一集成电路管芯的顶部上。 
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