JP2007504676A - スタック式電子アセンブリ - Google Patents
スタック式電子アセンブリ Download PDFInfo
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Abstract
【解決手段】本発明の実装例は、限られた範囲又はモジュールにマウントされるメモリ密度を向上するスタック式チップスケールパッケージを提供する。新規なスタガールーチンスキームによりスタック構造のすべての階層で同じトレースルーチンを用いることができ、チップスケールパッケージのスタック内の個々のメモリデバイスに効率よくアクセスできる。ボールグリッドアレイチップスケールパッケージ構造と熱矛盾のない材料を組み合わせることにより、熱によるクラック発生リスクが低減するとともに熱放出が向上する。さらに、この構造により、チップスケールパッケージにコンデンサや抵抗といったサポートコンポーネントのマウントが可能となる。
【選択図】図1
Description
・樹脂含有量に応じて熱膨張係数の範囲が6.0−9.0ppm/°CのArlon(Thermount)85NT;
・樹脂含有量に応じて熱膨張係数の範囲が7.0−10.0ppm/°CのArlon(Thermount)85NT;
・基準の熱膨張係数が5.5ppm/°C以上のCMC(銅−モリブデン−銅 コア)、銅の厚みを変えてCTEを調整するとこの係数が変わる(例えば、(銅−モリブデン−銅)5/90/5=5.58ppm/°C、13/74/13=5.8ppm/°C);
・基準の熱膨張係数が5.1ppm/°C以上のCIC(銅−インバール−銅)コア、銅の厚みを変えてCTEを調整するとこの係数が変わる(例えば、(銅−インバール−銅)20/60/20=5.2ppm/°C);
・熱膨張係数が4.5−6.5ppm/°Cの範囲のセラミックコア(例えば、AlNは4.5でアルミナが6.5)がある。
Claims (26)
- 第1の面と反対側の第2の面とを具え熱膨張係数を調整した材料からなる基板と;
前記基板の第1の面に複数の固い下側接続部材を用いてマウントされたメモリダイであって、前記基板が前記メモリダイの熱膨張係数と十分にマッチする熱膨張係数であるメモリダイと;
前記基板の第1の面にボールグリッドアレイ配列で設けられた半田ボールであって、1以上が前記下側接続部材の少なくとも1以上と電気的に接続している半田ボールと;
前記基板の第2の面に取り付けられた複数のパッドであって、各パッドが前記複数の半田ボールの1以上にスタガールーチンスキームで電気的に接続されているパッドと;
前記基板の第2の面において前記メモリダイの実質的に反対側に取り付けられる1以上の電子コンポーネントであって、当該電子コンポーネントと前記メモリダイが基板から突出する距離の合計が、前記半田ボールとパッドが前記基板から突出する距離より短い電子コンポーネントを具えることを特徴とするチップスケールパッケージ。 - 請求項1のチップスケールパッケージがさらに、前記第1の面に1以上の半田ボールを前記メモリダイに電気的に接続する導電線を具えることを特徴とするチップスケールパッケージ。
- 請求項1のチップスケールパッケージにおいて、前記基板が、前記メモリダイの熱膨張係数に十分にマッチするよう調整された熱膨張材料を含むことを特徴とするチップスケールパッケージ。
- 請求項1のチップスケールパッケージにおいて、前記下側接続部材は前記メモリダイの下面の大部分が露出するよう設けられていることを特徴とするチップスケールパッケージ。
- 第1の面と反対側の第2の面とを具える基板と;
前記基板の第1の面に半田ボールを用いてマウントされた半導体デバイスと;
前記基板の第1の面にオールグリッドアレイ配列で設けられた複数の半田ボールであって、1以上が前記半導体デバイスと電気的に接続された半田ボールと;
前記基板の第2の面に取り付けられたパッドであって、各パッドが前記複数の半田ボールの1又はそれ以上にスタガールーチンスキームで接続されたパッドと;
前記基板の第2の面に取り付けられた1以上の電気コンポーネントとを具えることを特徴とするチップスケールパッケージ。 - 請求項5のチップスケールパッケージにおいて、前記電気コンポーネントが、前記基板の第2の面において前記半導体デバイスのほぼ反対側に取り付けられていることを特徴とするチップスケールパッケージ。
- 請求項6のチップスケールパッケージにおいて、前記電気コンポーネントはコンデンサと抵抗を含むことを特徴とするチップスケールパッケージ。
- 請求項5のチップスケールパッケージにおいて、前記電気コンポーネントと半導体デバイスが前記基板から突出する合計の距離が、前記半田ボールとパッドが前記基板から突出する距離より小さいことを特徴とするチップスケールパッケージ。
- 請求項5のチップスケールパッケージにおいて、前記基板が、前記半導体デバイスの熱膨張計数と十分にマッチする熱膨張計数を有する熱膨張材料を含むことを特徴とするチップスケールパッケージ。
- 請求項5のチップスケールパッケージにおいて、前記半導体デバイスがシリコンデバイスであり、前記基板が当該シリコンデバイスの熱膨張係数と十分にマッチする調整された熱膨張材料を含んでなることを特徴とするチップスケールパッケージ。
- 請求項5のチップスケールパッケージがさらに、前記半田ボールの1以上を半導体デバイスに電気的に接続する導電線を前記第1の面に具えることを特徴とするチップスケールパッケージ。
- 請求項5のチップスケールパッケージにおいて、前記半導体デバイスがシリコンメモリデバイスであることを特徴とするチップスケールパッケージ。
- 請求項5のチップスケールパッケージにおいて、前記半導体デバイスが固い下側接続部材を用いて前記第1の面に取り付けられていることを特徴とするチップスケールパッケージ。
- 請求項13のチップスケールパッケージにおいて、前記固い下側接続部材は、前記半導体デバイスの下面の大部分を露出するよう構成されていることを特徴とするチップスケールパッケージ。
- 積層構造に配置される複数のチップスケールパッケージを具え、当該複数のチップスケールパッケージが、
第1の面と反対側の第2の面とを具え熱膨張係数を調整した材料からなる基板と;
前記基板の第1の面の線に下側接続部材を用いて接続される半導体デバイスであって、前記基板が前記半導体デバイスの熱膨張係数と実質的にマッチする熱膨張係数を有する半導体デバイスと;
前記基板の第1の面にボールグリッドアレイ配列で設けられた複数の半田ボールであって、当該半田ボールの少なくとも1つが前記半導体デバイスに接続されている半田ボールと;
前記基板のだい2の面に取り付けられた複数のパッドであって、各パッドが前記複数の半田ボールの1又はそれ以上にスタガールーチンスキームで接続されたパッドと;
前記基板の第2の面において前記半導体デバイスのほぼ反対側の領域にマウントされた1又はそれ以上の電子コンポーネントとを具え、
前記電子コンポーネントと前記半導体デバイスが基板から突出する距離の合計が、前記半田ボールとパッドとが前記基板から突出する距離より短いことを特徴とする積層型電子アセンブリ。 - 請求項15の積層型電子アセンブリにおいて、前記複数のチップスケールパッケージが同一のルーチントレースを具えることを特徴とする積層型電子アセンブリ。
- 請求項15の積層型電子アセンブリにおいて、第1のチップスケールパッケージの第1の面の半田ボールが、第2のチップスケールパッケージの第2の面のパッドに接続されることを特徴とする積層型電子アセンブリ。
- 請求項15の積層型電子アセンブリにおいて、前記スタガールーチンスキームは、第1のチップスケールパッケージの複数の半田ボールから積層中の各チップスケールパッケージの同じ下側接続部材へのアクセスが可能であることを特徴とする積層型電子アセンブリ。
- 請求項15の積層型電子アセンブリにおいて、前記下側接続部材は前記半導体デバイスの下面を露出するよう構成されていることを特徴とする積層型電子アセンブリ。
- メモリモジュールであって、当該メモリモジュールを他のデバイスと接続するインターフェースを具える主基板と;前記主基板の第1の面に接続される1又はそれ以上のメモリデバイスのスタックとを具え、
少なくとも1のメモリデバイスのスタックが、
積層構造に配置され、第1の面と反対側の第2の面とに同じルーチントレースを具える複数のチップスケールパッケージを具え、各チップスケールパッケージが、
第1の面と反対側の第2の面とを具える基板と、
下側接続部材を用いて前記基板の第1の面のトレースに電気的に接続されたメモリ半導体ダイと、
前記基板の第1の面に配設され、少なくとも1以上が前記メモリ半導体ダイに電気的に接続された複数の半田ボールとを具えることを特徴とするメモリモジュール。 - 請求項20に記載のメモリモジュールにおいて、
前記基板が熱膨張調整材料でなり、
前記基板が前記メモリ半導体ダイの熱膨張係数と実質的にマッチする熱膨張係数を有し、
前記複数の半田ボールは前記基板の第1の面にボールグリッドアレイ配列で配設され、
各チップスケールパッケージがさらに、
前記基板の第2の面に接続され、各々が前記半田ボールの1又はそれ以上にスタガールーチンスキームで電気的に接続された複数のパッドと、
前記基板の第2の面において前記メモリ半導体ダイとほぼ反対側の領域に設けられる1又はそれ以上の電子コンポーネントとを具え、前記電子コンポーネントとメモリ半導体ダイとが前記基板から突出する合計の距離が、前記半田ボールとパッドが前記基板から突出する距離よりも短いことを特徴とするメモリモジュール。 - 請求項21に記載のメモリモジュールにおいて、前記スタガールーチンスキームは、第1のチップスケールパッケージの複数の半田ボールからスタック中の各チップスケールパッケージの同じ下側接続部材へのアクセスが可能であることを特徴とするメモリモジュール。
- 前記メモリモジュールがデュアルインラインメモリモジュールであることを特徴とする請求項20に記載のメモリモジュール。
- 請求項20のメモリモジュールがさらに、前記主基板の第2の面に接続された1又はそれ以上のメモリデバイスを具えることを特徴とするメモリモジュール。
- 請求項20のメモリモジュールにおいて、前記チップスケールパッケージは、チップスケールパッケージの第1の面の半田ボールが別のチップスケールパッケージの第2の面のパッドに接続されることによりスタックされることを特徴とするメモリモジュール。
- 請求項20のメモリモジュールにおいて、前記下側接続部材が、前記メモリ半導体ダイの下面をほぼ露出するよう構成されていることを特徴とするメモリモジュール。
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- 2004-08-25 KR KR1020067004539A patent/KR100953051B1/ko not_active IP Right Cessation
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- 2004-08-25 JP JP2006526125A patent/JP4588027B2/ja not_active Expired - Fee Related
- 2004-08-25 EP EP04782199A patent/EP1685600A4/en not_active Withdrawn
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WO2022209737A1 (ja) * | 2021-03-31 | 2022-10-06 | 株式会社村田製作所 | 高周波モジュール及び通信装置 |
Also Published As
Publication number | Publication date |
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KR100953051B1 (ko) | 2010-04-14 |
JP4588027B2 (ja) | 2010-11-24 |
EP1685600A1 (en) | 2006-08-02 |
US20050051903A1 (en) | 2005-03-10 |
US7180165B2 (en) | 2007-02-20 |
KR20060079207A (ko) | 2006-07-05 |
WO2005027225A1 (en) | 2005-03-24 |
CN1846311A (zh) | 2006-10-11 |
EP1685600A4 (en) | 2008-05-14 |
USRE42363E1 (en) | 2011-05-17 |
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