TWI385779B - 多層系統晶片模組結構 - Google Patents

多層系統晶片模組結構 Download PDF

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TWI385779B
TWI385779B TW098136383A TW98136383A TWI385779B TW I385779 B TWI385779 B TW I385779B TW 098136383 A TW098136383 A TW 098136383A TW 98136383 A TW98136383 A TW 98136383A TW I385779 B TWI385779 B TW I385779B
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module
circuit substrate
connection
layer system
layer
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TW098136383A
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TW201115714A (en
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Chun Ming Huang
Chien Ming Wu
Chih Chyau Yang
Shih Lun Chen
Chin Long Wey
Chi Shi Chen
Chi Sheng Lin
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Nat Chip Implementation Ct Nat Applied Res Lab
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Priority to TW098136383A priority Critical patent/TWI385779B/zh
Priority to US12/685,723 priority patent/US8199510B2/en
Publication of TW201115714A publication Critical patent/TW201115714A/zh
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Publication of TWI385779B publication Critical patent/TWI385779B/zh

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Description

多層系統晶片模組結構
本發明係為一種多層系統晶片模組結構，特別為一種應用於系統晶片之多層系統晶片模組結構。
電子產品在一般人的生活中，佔有舉足輕重的地位，而隨著電子產品在市場的佔有比例逐年上升，為了迎合消費者的使用習慣，如何在短時間內不斷開發多樣化的電子產品，以吸引消費者目光，便是如何提前搶得市場佔有率的關鍵。
而為了縮短產品的開發時程並同時降低成本，所以在不同產品內之系統晶片大多採用同一規格的基本架構之方式進行設計。舉例來說，不同型號之攜帶型通訊產品，其系統晶片設計之基頻部份可使用同一規格之元件，例如：微控制器、數位訊號處理器、匯流排、數位類比轉換器、編/解碼器、調變器…等。當基本架構選定之後，系統設計者可依市場需求及成本考量進行功能擴充之設計，例如不同功率之攜帶型通訊產品。
在上述之系統晶片的開發設計階段中，系統設計者可自行選用或由廠商提供所需之基本架構，並且還可引入委外設計之矽智財(silicon intellectual property)，但設計完成之系統晶片仍須經過製造及驗證。因此雖然系統設計者可參與所有設計，但後續之製造及驗證卻需要耗費高昂的人力成本。
所以對系統設計者來說，若能將設計整合延伸至製造及驗證階段，也就是若能將單一封裝系統晶片中的部份實體採用預先製造及驗證完成的成品，系統設計者便能僅專注於系統晶片中功能擴充部份的設計、製造及驗證，藉此大幅縮短系統晶片的開發時間及測試流程，進而降低設計錯誤機率，並能減少開發成本。再者，由於消費者對電子產品在縮小其體積上的要求越來越高，因此若能有效減少系統晶片的體積，將可有助於縮小電子產品的體積，以符合消費者的需求。
本發明係為一種多層系統晶片模組結構，其係藉由連接模組層電訊連接兩電路基板模組層，以可利用三維結構之方式構成系統晶片模組結構，進而使得系統設計者可以更靈活之方式設計系統晶片模組結構。
本發明係為一種多層系統晶片模組結構，藉由連接模組之設置，以達到隨需求增設電路基板模組之功效，進而可輕易擴充系統晶片模組之功能。
本發明係為一種多層系統晶片模組結構，其中電路基板模組層中之電路基板模組可先行製造及驗證，以縮短系統晶片模組之驗證時程。
本發明係為一種多層系統晶片模組結構，其係提供系統設計者組合不同功能之電路基板模組，以形成各式之系統晶片模組，進而提供多樣性系統晶片模組。
本發明係為一種多層系統晶片模組結構，由於電路基板模組可先行製造及驗證，因此系統設計者僅需針對特殊規格進行功能擴充設計，進而達到節省研發時間及成本之功效。
為達上述功效，本發明係提供一種多層系統晶片模組結構，其包括：至少二電路基板模組層，並且每一電路基板模組層係由至少一電路基板模組所構成，又電路基板模組具有：一第一電路基板；至少一預置元件，其係設置且電訊連接於第一電路基板；以及至少一第一連接介面，其係設置且電訊連接於第一電路基板，並與預置元件電訊連接；以及至少一連接模組層，其係由至少一連接模組所構成，並且連接模組層係設置於二電路基板模組層之間，並使二多層電路基板模組層之第一連接介面彼此電訊連接；其中連接模組具有：一第二電路基板，其具有至少二第二線路層並且分別構成第二電路基板之一第三表面及一第四表面；以及至少二第二連接介面，其係分別設置於第三表面及第四表面並且分別與對應之第二線路層電訊連接，又該些第二連接介面係分別對應電訊連接於二電路基板模組層之第一連接介面。
藉由本發明的實施，至少可達到下列進步功效：
一、以利用連接模組層電訊連接兩電路基板模組層，以達到可以三維結構之方式構成系統晶片模組結構之功效，並使得系統晶片模組之結構更為彈性。
二、藉由連接模組之設置，以隨需求增設電路基板模組之功效，進而達到可輕易擴充系統晶片模組功能之功效。
三、由於電路基板模組層中之電路基板模組可先行製造及驗證，以縮短系統晶片模組之驗證時程，進而達到節省研發時間及成本之功效。
四、提供系統設計者組合不同功能之電路基板模組，以形成各 式之系統晶片模組，進而提供多樣性系統晶片模組。
為了使任何熟習相關技藝者了解本發明之技術內容並據以實施，且根據本說明書所揭露之內容、申請專利範圍及圖式，任何熟習相關技藝者可輕易地理解本發明相關之目的及優點，因此將在實施方式中詳細敘述本發明之詳細特徵以及優點。
第1圖係為本發明之一種多層系統晶片模組結構100之第一實施例之立體實施例示意圖。第2圖係為本發明之一種多層系統晶片模組結構100之第二實施例之立體實施例示意圖。第3A圖係為本發明之一種電路基板模組210之第一實施態樣。第3B圖係為本發明之一種電路基板模組210之第二實施態樣。第4A圖係為本發明之一種連接模組310之第一實施態樣。第4B圖係為本發明之一種連接模組310之第二實施態樣。第5A圖係為本發明之一種多層系統晶片模組結構110之第一實施態樣之剖視實施例圖。第5B圖係為第5A圖之電路方塊實施例示意圖。第6A圖係為本發明之一種多層系統晶片模組結構100之第二實施態樣之分解剖視實施例圖。第6B圖係為本發明之一種多層系統晶片模組結構100之第三實施態樣之剖視實施例圖。第7圖係為本發明之一種多層系統晶片模組結構120之應用實施例示意圖。
如第1圖所示，本實施例係為一種多層系統晶片模組結構100，其包括：至少二電路基板模組層200；以及至少一連接模 組層300，其中連接模組層300係設置於每兩電路基板模組層200之間，以使得兩電路基板模組層200之間得以藉由連接模組層300彼此電訊連接，進而構成三維立體之系統晶片模組結構100，以縮小系統晶片模組結構100之體積。
如第1圖及第2圖所示，電路基板模組層200，係由至少一電路基板模組210所構成，以使得電路基板模組210可構成一平面結構，而電路基板模組210係例如第3A圖及第3B圖所示，其具有：一第一電路基板211；至少一預置元件212；以及至少一第一連接介面213。
如第3A圖及第3B圖所示，第一電路基板211，其可以藉由至少二第一線路層214所構成，而最外層的第一線路層214可構成一第一表面215及一第二表面216，而第一表面215可以是第一電路基板211的上表面，第二表面216便可以是第一電路基板211的下表面。又每一第一線路層214可具有獨立之電路設計並可彼此電訊連接，以使得第一電路基板211內可建置高密度之電路結構而符合更複雜之應用。
如第3A圖所示，電路基板模組210之預置元件212係設置且電訊連接於第一電路基板211，而預置元件212可藉由覆晶、銲線…等技術與第一電路基板211形成電訊連接。
預置元件212可具有至少一晶粒或複數個晶粒或非晶粒元件，而由於晶粒係為裸晶型式，因此電路基板模組210可再進一步具有一封裝體220，用以封裝晶粒，以避免晶粒受到水氣影響或外力破壞。非晶粒則可利用堆疊封裝之技術電訊連接於第一電路基板211(圖未示)，以使得電路基板模組210之預置 元件212可具有堆疊封裝之元件。預置元件212亦可具有至少一晶片或複數個晶片，而晶片則為已封裝完成之晶片(圖未示)。
預置元件212可以是一處理器元件或一記憶體元件、一輸入輸出元件、一無線裝置元件、一電源管理元件、一感測器元件、一散熱裝置元件或一顯示元件…等。而根據預置元件212的類型、功能上的不同，以使得電路基板模組210可以是一處理器子模組、一記憶體子模組、一輸入輸出子模組、一無線裝置子模組、一電源管理子模組、一電源子模組、一感測器子模組、一散熱裝置子模組、一顯示子模組、一連線繞線子模組或其組合。
第一連接介面213，其係設置且電訊連接於第一電路基板211，並且與預置元件212電訊連接。第一連接介面213可以是複數個銲點或是複數個銲球，而銲球則可以構成一銲球陣列。第一連接介面213可以設置在第一表面215，或是同時設置在第一表面215及第二表面216上，並與其第一線路層214電訊連接。
舉例來說，如第3A圖及第3B圖所示，第一表面215上可配置有複數銲點，又銲點可與構成第一表面215之第一線路層214電訊連接，另外在第二表面216上亦可配置有複數銲球，而銲球則可與構成第二表面216之第一線路層214電訊連接，又因為兩第一線路層214之間已彼此電訊連接，因此銲點及銲球之間也可彼此電訊連接。
如第3A圖所示，預置元件212可僅設置在第一表面215上，並與第一表面215之第一線路層214電訊連接，以利用銲 球及銲點與外界電訊連接，另外預置元件212也可僅設置在第二表面216上(圖未示)，並與第二表面216之第一線路層214電訊連接。又或者如第3B圖所示，預置元件212可分別設置在第一表面215及第二表面216上，並分別與第一表面215及第二表面216之第一線路層214電訊連接，以使得分設於第一表面215及第二表面216上的預置元件212皆可利用銲點及銲球與外界電訊連接。
如第1圖所示，連接模組層300，其係由至少一連接模組310所構成，以使得連接模組310可構成一平面結構。如第4A圖及第4B圖所示，連接模組310具有：一第二電路基板311；以及至少二第二連接介面312。
第二電路基板311，其可藉由至少二第二線路層313所構成，而最外層的第二線路層313可構成一第三表面314及一第四表面315，其中第三表面314可以是第二電路基板311的上表面，第四表面315則可以是第二電路基板311的下表面。同樣的每一第二線路層313可具有獨立之電路設計並可彼此電訊連接，以使得第二電路基板311內可建置高密度之電路結構。
第二連接介面312，其係分別設置於第二電路基板311之第三表面314及第四表面315，並且分別與對應之第二線路層313電訊連接。如第4B圖所示，第二連接介面312可以是一銲球陣列。
如第1圖及第2圖所示，可利用連接模組310的第二連接介面312分別與電路基板模組210的第一連接介面213電訊連接，以使得設置於兩電路基板模組層200之間的連接模組層 300可提供電路基板模組210電訊號傳遞的路徑，進而利用連接模組310之設置以達到同時以水平及垂直之方向連接電路基板模組210之功效。
如第5A圖及第7圖所示，根據電路基板模組210中預置元件212類型的不同，電路基板模組210可分為共通元件電路基板模組210a與功能元件電路基板模組210b，而共通元件電路基板模組210a係例如為處理器子模組或記憶體子模組…等，而功能元件電路基板模組210b則可以是輸入輸出子模組、無線裝置子模組、電源管理子模組、電源子模組、感測器子模組、散熱裝置子模組、顯示子模組、連線繞線子模組…等。
而系統設計者可先將共通元件電路基板模組210a利用連接模組310相互連接後，再根據功能的需求，增設功能元件電路基板模組210b，以達到輕易擴充系統晶片模組結構100功能之功效。另外由於電路基板模組210皆可先行製造及驗證，因此可大幅縮短系統晶片模組結構100之驗證時程，以節省研發時間及成本。
舉例來說，如第5A圖所示，系統晶片模組結構110可以由複數層電路基板模組層200a、200b、200c及複數層連接模組層300所構成，而一電路基板模組層200a中之共通元件電路基板模組210a可同時設置處理器元件410、北橋晶片元件411、動態隨機存取記憶體(Dynamic Random Access Memory,DRAM)元件412於同一第一電路基板211a上，另一電路基板模組層200b中可同時設置南橋晶片元件413、微型硬碟元件414及快閃記憶體(flash memory)元件415於同一第一電路基板 211b上，又再另一電路基板模組層200c中更可同時設置顯示晶片元件416、網路裝置元件417、輸入輸出元件418於同一第一電路基板211c上。
第5B圖係為上述電路基板模組210a、210b及連接模組310a、310b、310c、310d間之電路方塊圖，而如第5B圖所示，處理器元件410及動態隨機存取記憶體元件412可透過北橋晶片元件411與南橋晶片元件413交換電訊號，而北橋晶片元件411與南橋晶片元件413之間則可透過兩連接模組310a、310b進行電訊連接，而南橋晶片元件413則可與微型硬碟元件414及快閃記憶體元件415電訊連接。顯示晶片元件416、網路裝置元件417與輸入輸出元件418可透過兩連接模組310c、310d與南橋晶片元件413電訊連接，藉此可構成一個完整具有個人電腦功能的系統晶片結構110。
更佳的是，由於電路基板模組210的第一連接介面213與連接模組310的第二連接介面312的規格相符，因此系統設計者可隨時隨需求藉由連接模組310而增設電路基板模組210，並且可以各種不同方式連接電路基板模組210。例如第6A圖所示，在同一電路基板模組層200中可具有三電路基板模組210，而同一連接模組層300中可具有二連接模組310，而每一連接模組310的第二連接介面312係分設於第二電路基板311的兩端，因此可藉由連接模組310作為電路基板模組210間電訊號傳遞的路徑。又第6B圖所示，連接模組310e不單單可以作橫向的電訊號傳遞，還可以在連接模組310e之間，再電訊連接另一連接模組310f，以作為縱向的電訊號傳遞路徑。
如第6A圖及第6B圖所示，為了提高系統晶片模組結構100的散熱效率，可在連接模組310的第二電路基板311上設置至少一散熱孔洞316，以使得熱能可藉由散熱孔洞散除，另外如第7圖所示，功能元件電路基板模組210b也可以具有一散熱孔洞217，同樣的共通元件電路基板模組210a也可以具有散熱孔洞217(圖未示)，藉以提升電路基板模組210a、210b的散熱效能。
如第7圖所示，系統晶片模組結構120中共通元件電路基板模組210a可先建置完成後，再於系統晶片模組結構120最外層設置功能元件電路基板模組210b，以擴充系統晶片模組結構120的功能。而功能元件電路基板模組210b係包括例如輸入埠元件511、輸出埠元件512、散熱裝置元件513、無線裝置元件514、通用序列匯流排(USB)元件515、顯示元件516、網路埠元件517、通用異步串行收發傳輸(Universal Asynchronous Receiver/Transmitter,UART)元件518。更佳的是，為了再進一步提升功能元件電路基板模組210b的散熱效能，散熱裝置元件513恰可對應設置於散熱孔洞217處，以提高系統晶片模組結構120之散熱速率。
如第1圖、第2圖、第5A圖及第7圖所示，最外層的電路基板模組210還可進一步具有一接觸式連接部600，其係設置於第一電路基板211上並與第一電路基板211電訊連接，又接觸式連接部600可以為一金手指(圖未示)、一針腳陣列(如第1圖及第7圖所示)、一銲球陣列(如第2圖所示)或一平面柵格陣列(如第5A圖所示)，藉此可利用接觸式連接部600使系統 晶片模組結構100、110、120可與外部電源或裝置進行電訊連接。
惟上述各實施例係用以說明本發明之特點，其目的在使熟習該技術者能瞭解本發明之內容並據以實施，而非限定本發明之專利範圍，故凡其他未脫離本發明所揭示之精神而完成之等效修飾或修改，仍應包含在以下所述之申請專利範圍中。
100、110、120‧‧‧多層系統晶片模組結構
200、200a、200b、200c‧‧‧電路基板模組層
300‧‧‧連接模組層
210‧‧‧電路基板模組
210a‧‧‧共通元件電路基板模組
210b‧‧‧功能元件電路基板模組
211、211a、211b、211c‧‧‧第一電路基板
212‧‧‧預置元件
213‧‧‧第一連接介面
214‧‧‧第一線路層
215‧‧‧第一表面
216‧‧‧第二表面
217‧‧‧散熱孔洞
220‧‧‧封裝體
310‧‧‧連接模組
310a、310b、310c、310d‧‧‧連接模組
310e、310f‧‧‧連接模組
311‧‧‧第二電路基板
312‧‧‧第二連接介面
313‧‧‧第二線路層
314‧‧‧第三表面
315‧‧‧第四表面
316‧‧‧散熱孔洞
410‧‧‧處理器元件
411‧‧‧北橋晶片元件
412‧‧‧動態隨機存取記憶體元件
413‧‧‧南橋晶片元件
414‧‧‧微型硬碟元件
415‧‧‧快閃記憶體元件
416‧‧‧顯示晶片元件
417‧‧‧網路裝置元件
418‧‧‧輸入輸出元件
511‧‧‧輸入埠元件
512‧‧‧輸出埠元件
513‧‧‧散熱裝置元件
514‧‧‧無線裝置元件
515‧‧‧通用序列匯流排元件
516‧‧‧顯示元件
517‧‧‧網路埠元件
518‧‧‧通用異步串行收發傳輸元件
600‧‧‧接觸式連接部
第1圖係為本發明之一種多層系統晶片模組結構之第一實施例之立體實施例示意圖。
第2圖係為本發明之一種多層系統晶片模組結構之第二實施例之立體實施例示意圖。
第3A圖係為本發明之一種電路基板模組之第一實施態樣。
第3B圖係為本發明之一種電路基板模組之第二實施態樣。
第4A圖係為本發明之一種連接模組之第一實施態樣。
第4B圖係為本發明之一種連接模組之第二實施態樣。
第5A圖係為本發明之一種多層系統晶片模組結構之第一實施態樣之剖視實施例圖。
第5B圖係為第5A圖之電路方塊實施例示意圖。
第6A圖係為本發明之一種多層系統晶片模組結構之第二實施態樣之分解剖視實施例圖。
第6B圖係為本發明之一種多層系統晶片模組結構之第三實施態樣之剖視實施例圖。
第7圖係為本發明之一種多層系統晶片模組結構之應用實施例 示意圖。
100．．．多層系統晶片模組結構
200．．．電路基板模組層
210．．．電路基板模組
213．．．第一連接介面
300．．．連接模組層
310．．．連接模組
312．．．第二連接介面
600．．．接觸式連接部

Claims (18)

  1. 一種多層系統晶片模組結構，其包括：至少二電路基板模組層，並且每一該電路基板模組層係由至少一電路基板模組所構成，又該電路基板模組具有：一第一電路基板；至少一預置元件，其係設置且電訊連接於該第一電路基板；以及至少一第一連接介面，其係設置且電訊連接於該第一電路基板，並與該預置元件電訊連接；以及至少一連接模組層，其係由至少一連接模組所構成，並且該連接模組層係設置於二該電路基板模組層之間，並使二該多層電路基板模組層之該第一連接介面彼此電訊連接；其中該連接模組具有：一第二電路基板，其具有至少二第二線路層並且分別構成該第二電路基板之一第三表面及一第四表面；以及至少二第二連接介面，其係分別設置於該第三表面及該第四表面並且分別與對應之該第二線路層電訊連接，又該些第二連接介面係分別對應電訊連接於二該電路基板模組層之該第一連接介面。
  2. 如申請專利範圍第1項所述之多層系統晶片模組結構，其中該電路基板模組係為一處理器子模組、一記憶體子模組、一輸入輸出子模組、一無線裝置子模組、一電源管理子模組、一電源子模組、一感測器子模組、一散熱裝置子模組、一顯示子模組、一連線繞線子模組或其組合。
  3. 如申請專利範圍第1項所述之多層系統晶片模組結構，其 中該電路基板模組具有至少一散熱孔洞。
  4. 如申請專利範圍第1項所述之多層系統晶片模組結構，其中該第一電路基板係具有至少二第一線路層並且分別構成該第一電路基板之一第一表面及一第二表面。
  5. 如申請專利範圍第1項所述之多層系統晶片模組結構，其中該預置元件係具有至少一晶粒或至少一晶片。
  6. 如申請專利範圍第1項所述之多層系統晶片模組結構，其中該預置元件係具有複數個晶粒或複數個晶片。
  7. 如申請專利範圍第6項所述之多層系統晶片模組結構，其中該些晶粒或該些晶片係設置於該第一電路基板之一第一表面或一第二表面。
  8. 如申請專利範圍第6項所述之多層系統晶片模組結構，其中該些晶粒或該些晶片分別設置於該第一電路基板之一第一表面及一第二表面。
  9. 如申請專利範圍第1項所述之多層系統晶片模組結構，其中每一該電路基板模組進一步具有至少一封裝體，其係封裝該預置元件。
  10. 如申請專利範圍第1項所述之多層系統晶片模組結構，其中該第一連接介面係設置於該第一電路基板之一第一表面或一第二表面。
  11. 如申請專利範圍第1項所述之多層系統晶片模組結構，其中該第一連接介面係設置於該第一電路基板之一第一表面及一第二表面。
  12. 如申請專利範圍第1項所述之多層系統晶片模組結構，其 中該第一連接介面係為一銲球陣列。
  13. 如申請專利範圍第1項所述之多層系統晶片模組結構，其中該第一電路基板進一步具有一接觸式連接部，其係設置並電訊連接於該第一電路基板。
  14. 如申請專利範圍第13項所述之多層系統晶片模組結構，其中該接觸式連接部係為一銲球陣列。
  15. 如申請專利範圍第13項所述之多層系統晶片模組結構，其中該接觸式連接部係為一針腳陣列。
  16. 如申請專利範圍第13項所述之多層系統晶片模組結構，其中該接觸式連接部係為一平面柵格陣列。
  17. 如申請專利範圍第1項所述之多層系統晶片模組結構，其中該第二連接介面係為一銲球陣列。
  18. 如申請專利範圍第1項所述之多層系統晶片模組結構，其中該連接模組具有至少一散熱孔洞。
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