TW201347051A - 連接記憶體晶粒形成記憶體系統的方法與設備 - Google Patents

連接記憶體晶粒形成記憶體系統的方法與設備 Download PDF

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TW201347051A
TW201347051A TW102102899A TW102102899A TW201347051A TW 201347051 A TW201347051 A TW 201347051A TW 102102899 A TW102102899 A TW 102102899A TW 102102899 A TW102102899 A TW 102102899A TW 201347051 A TW201347051 A TW 201347051A
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memory device
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die
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Byoung-Jin Choi
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Mosaid Technologies Inc
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Abstract

一種連接多數記憶體裝置晶粒至在晶粒間不需要軌跡的基板的方法、系統與設備。第一實施例指定一記憶裝置晶粒予以匹配至另一記憶體裝置晶粒的連接法，作為當以交錯形式安裝在基板的兩側。結果為連接多數積體電路的菊鍊陣列，其具有減低之電容性負載。在記憶體裝置晶粒間之匯流排上之電容性負載被減低。因為在基板的兩側上的短線共享一導孔，所以，減低了導孔數量。另一實施例安排該等晶粒為閉環路。

Description

連接記憶體晶粒形成記憶體系統的方法與設備
本發明有關於用於數位電子裝置中之記憶體裝置，更明確地說，有關於具有多數記憶體裝置晶粒的記憶體系統，該等記憶體裝置晶粒連接為串聯形式，以可用於菊鍊及閉環路記憶體系統中。
記憶體裝置被用以儲存資料於例如電腦的數位電子裝置中。近年來，對於高頻寬及低功率消耗的大記憶體系統的需求已經增加。早先在數位電子中之多晶粒記憶體裝置包含有多數晶粒並聯連接至一共同匯流排，此系統被認定為多投匯流排所連接。具有幾個記憶體裝置晶粒並聯連接至一共同匯流排的多投連接法係被經常使用於大記憶體系統中。
圖1顯示具有雙側記憶體裝置安裝之多投連接法的先前技術實施例。記憶體裝置晶粒1及2係被安裝在基板6的第一側7。晶粒3及4被安裝在基板6的分別 直接相反於晶粒1及2的相反側上。基板6可以為多層PCB，或其他類似基板，例如陶瓷晶圓。基板6經常包含內部繞線信號軌跡9及10於記憶體裝置晶粒1-4之間。穿過導孔11至18的短線允許信號軌跡9及10被連接至基板6的相反面7及8。穿過導孔11至18的短線通常終結於表面7及8上的墊21-28中。墊21至28被組態以連接至銲錫球29或由記憶體裝置晶粒1至4至信號軌跡的其他連接法。穿過導孔之短線允許銲錫球29或由記憶體裝置晶粒至信號軌跡9及10的其他連接法。導孔11至18係被製造有較信號軌跡9及10為寬的間距，以提供額外的寬度，並且，使用幾個此等導孔可以限制可以被繞線穿過該基板的單一層的軌跡數目。這可能強迫其他層及額外成本。連接至一匯流排的記憶體裝置晶粒的數目很大。各個記憶體裝置晶粒及長軌跡的電容性負載造成在該匯流排上的大電容性負載，使得其很難取得高頻寬。同時，較大的電容性負載也表示較大之功率消耗。
新進設計使用多數記憶體裝置晶粒被串聯連接之的連接法。如此作的理由為藉由限制記憶體裝置晶粒的數目，來降低匯流排上的電容性負載。此一記憶體晶粒陣列通常稱為菊鍊。一種變化例以將在菊鍊中之最後晶粒連接至第一晶粒以形成一環路，此裝置被稱為環鍊。圖2顯示具有雙側記憶體裝置安裝的菊鍊內連線或環路鍊內連線的先前技藝實施例。記憶體裝置晶粒31及32被安裝至基板36的第一側37。晶粒33及34被安裝至基板36的 相反側38，大致與晶粒31及32相對。基板36可以為多層PCB，或其他例如陶瓷晶圓的類似基板。基板36包含內部繞線信號軌跡39於晶粒31與外側之間，及軌跡40於記憶體裝置晶粒31及32之間，及軌跡41於記憶體裝置晶粒32與34之間，及軌跡42於記憶體裝置晶粒34與33之間，及軌跡43於記憶體裝置晶粒33與外側之間。穿過導孔46至54之短線允許連接至銲錫球56或由記憶體裝置晶粒31至34至信號軌跡39至43的其他連接法。因為記憶體裝置晶粒31至34係彼此點對點連接，所以，在該匯流排上的記憶體裝置晶粒31至34的電容性負載係較小，及軌跡36至43的長度係短於圖1的多投連接法，使得匯流排上的總電容性負載減低。然而，在記憶體裝置晶粒之間仍有軌跡36至54，使得這很難取得高頻寬及低功率消耗。
本發明提供一種用以連接在晶粒間不需要軌跡的多數記憶體裝置晶粒的方法與設備。在第一實施例是，這是藉由指定一個記憶體裝置晶粒予以匹配至另一記憶體裝置晶粒的連接法，作為當以交錯形式安裝在基板的兩側。結果為連接多數積體電路內部電壓的菊鍊陣列，並控制為具有減低之電容性負載。在記憶體裝置晶粒間之匯流排上之電容性負載被減低。因為在基板的兩側上的兩短線共享一個導孔，所以，減低了導孔數量。
另一實施例提供一種方法與設備，用以連接在晶粒間也不需要軌跡的多數記憶體裝置晶粒。這是藉由指定一個記憶體裝置晶粒予以匹配至另一記憶體裝置晶粒的連接法，作為當以交錯形式安裝在基板的兩側。結果為連接多數積體電路內部電壓的環路鏈陣列，並相較於傳統繞線，被以減低之電容性負載控制。在記憶體裝置晶粒間之匯流排上之電容性負載被減低。因為在基板的兩側上的短線共享一個導孔，所以，減低了導孔數量。
本發明藉由消除在匯流排間之長度差及減低在記憶體裝置晶粒間之匯流排上的電容性負載，而改良效能。其進一步藉由減低在記憶體裝置晶粒間之匯流排上的電容性負載，而減低功率消耗。結果為藉由移除軌跡及減低在基板中之導孔數目，而降低了基板製造成本。
1-4‧‧‧記憶體裝置晶粒
6‧‧‧基板
7‧‧‧第一側
8‧‧‧相反面
9，10‧‧‧信號軌跡
11-18‧‧‧導孔
21-28‧‧‧墊
29‧‧‧銲錫球
31-34‧‧‧記憶體裝置晶粒
36‧‧‧基板
37‧‧‧第一側
38‧‧‧相反側
39-43‧‧‧信號軌跡
46-54‧‧‧導孔
56‧‧‧銲錫球
57-59‧‧‧導孔
61，62‧‧‧導孔
63‧‧‧側
64‧‧‧側
71‧‧‧連接晶片
72-79‧‧‧晶粒
80‧‧‧基板
81‧‧‧側
82‧‧‧側
本發明之其他特性及優點將由以下的詳細說明，配合上附圖而更明確，其中：圖1顯示具有雙側記憶體裝置安裝的多投連接法的先前技術實施例。
圖2顯示具有雙側記憶體裝置安裝的菊鍊或環路鍊內連線的先前技術實施例。
圖3顯示依據本發明實施例安裝之具有雙側記憶體裝置的菊鍊或環路鍊內連線。
圖4顯示依據本發明實施例的一球陣列的記 憶體裝置晶粒。
圖5為一方塊圖，顯示菊鍊內連線的連接法。
圖6為圖3實施例的透視圖。
圖7為一方塊圖，顯示環路鍊內連線的連接法。
圖8為另一實施例的透視圖。
應注意的是，於所有附圖中，相類似元件係以相類似元件符號表示。
圖3顯示具有雙側記憶體裝置安裝的菊鏈內連線連接法的實施例。記憶體裝置晶粒51、52、53及54係以交錯形式被安裝在基板56的兩側上。基板56可以為多層PCB、陶瓷晶圓或任何其他基板。短線透過導孔57將晶粒51連接至晶粒53。短線透過導孔58將晶粒52連接至晶粒53。短線透過導孔59將晶粒52連接至晶粒54。導孔61及62分別將晶粒54及51連接至外側。至晶粒57-62的連接法可以藉由銲錫球及墊、接觸、插座、或其他來自記憶體裝置晶粒51、52、53及54的連接法。安裝在基板56的一側63上的晶粒51及52係被連接至安裝在基板的另一側64的記憶體裝置晶粒53及54。因為基板的兩側之短線共享一導孔，所以導孔的數目被減少50%，及各個導孔可以具有較大的間距。基板56在兩記 憶體裝置晶粒間並沒有內部繞線信號軌跡。在基板56內的層數可以由於較大之導孔間距及在記憶體裝置晶粒間沒有軌跡而減低。因為記憶體裝置晶粒51至54係此以點對點方式連接及在記憶體裝置晶粒間沒有軌跡，所以，在匯流排上的電容性負載係小於任何一先前技術者。
圖4顯示在本發明所用之一典型球陣列的記憶體裝置晶粒。球的名稱為例子之一並可以由於裝置間而有所不同。
圖5為記憶體裝置晶粒的配置方塊圖，其係被顯示為如圖4的菊鍊內連線。
圖6為使用圖4晶粒的圖3實施例的透視圖。應注意的是，晶粒51及52係被安裝在基板56的側63上，以缺口朝上，以及，晶粒53及54係被安裝在基板56的相反側64上，以缺口朝下。此架構確保最小導孔長度。
圖7為記憶體晶粒的配置的方塊圖，如圖4所示為環路鍊內連線。連接晶片71可以為另一記憶體裝置晶粒或介面晶片。連接晶片71也可以被移除並由基板軌跡完成連接。如所示，點(...)表示任意數量的晶粒。
圖8為圖7架構的透視圖，其具有加入第二實施例的八個晶粒72-79。連接晶片71也可以為另一記憶體裝置晶粒或介面晶片。連接晶片71也可以被移除並由基板軌跡完成連接。應注意的是，連接晶片71係與晶粒73及74一起被安裝在基板80的一側81，具有缺口朝 上，及晶粒76及78則被安裝具有缺口朝下。基板80的相反側82上，則具有晶粒77與79，具有缺口朝上，及晶粒72及75具有缺口朝下。此架構確保最小導孔長度。
51-54‧‧‧記憶體裝置晶粒
56‧‧‧銲錫球
63、64‧‧‧側

Claims (7)

  1. 一種多晶粒封裝，包含：基板；及多數記憶體晶粒，安裝在該基板的一側，及第二多數記憶體晶粒，安裝在該基板的相反側，並相對於該多數記憶體晶粒呈交錯形式。
  2. 如申請專利範圍第1項所述之多晶粒封裝，其中有四個晶粒串聯連接。
  3. 如申請專利範圍第1項所述之多晶粒封裝，更包含控制器，安裝在該基板的一側，架構以連接該等晶粒成為閉環路。
  4. 一種用以建構多晶粒封裝的方法，包含步驟：設有多數晶粒，安裝多數晶粒在基板的一側，及交錯地安裝第二多數晶粒於該基板的另一側並與在該基板的另一側中之該多數第一晶粒呈相反取向。
  5. 一種記憶體系統，包含：基板，及多數記憶體晶粒，安裝在該基板的一側，及第二多數晶粒，安裝在該基板的另一側並與該第一多數晶粒交錯，及一控制器，連接至該第一及該第二多數晶粒，架構以控制該等晶粒的操作。
  6. 如申請專利範圍第5項所述之記憶體系統，其中該控制器被架構以連接該等晶粒成為菊鍊架構。
  7. 如申請專利範圍第5項所述之記憶體系統，其中該控制器被架構以連接該等晶粒成為閉環路架構。
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