US20050195629A1 - Interchangeable connection arrays for double-sided memory module placement - Google Patents

Interchangeable connection arrays for double-sided memory module placement Download PDF

Info

Publication number
US20050195629A1
US20050195629A1 US10792350 US79235004A US2005195629A1 US 20050195629 A1 US20050195629 A1 US 20050195629A1 US 10792350 US10792350 US 10792350 US 79235004 A US79235004 A US 79235004A US 2005195629 A1 US2005195629 A1 US 2005195629A1
Authority
US
Grant status
Application
Patent type
Prior art keywords
memory
columns
connections
signals
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10792350
Inventor
Michael Leddige
Kuljit Bains
John Sprietsma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by G11C11/00
    • G11C5/02Disposition of storage elements, e.g. in the form of a matrix array
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007Types of components
    • H05K2201/10159Memory
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15Position of the PCB during processing
    • H05K2203/1572Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product
    • Y02P70/60Greenhouse gas [GHG] capture, heat recovery or other energy efficient measures relating to production or assembly of electric or electronic components or products, e.g. motor control
    • Y02P70/611Greenhouse gas [GHG] capture, heat recovery or other energy efficient measures relating to production or assembly of electric or electronic components or products, e.g. motor control the product being a printed circuit board [PCB]

Abstract

A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate.

Description

    BACKGROUND
  • Currently, memory packages, such as dual, in-line memory modules (DIMM) may reside on both sides of a printed circuit board (PCB) or other substrate. This increases memory density for the system. Signals for the memories may route through the substrate, which may have several layers. With memory packages on both sides of the substrate, signal routing and integrity may become an issue.
  • Signals being routed through the substrate may connect to balls or connections to the DIMM on opposite sides of the packages. For examples, signals going to the closest side of the package on the one side of the substrate will generally end up having to go to the farthest side of the package on the other side of the substrate. The DIMM for the other side of the package is turned ‘upside down’ to mount it on the other side, causing the relevant connection to be on the other side of the package from the signal origination.
  • BRIEF DESCRIPTION OF THE DRAWINGS
  • Embodiments of the invention may be best understood by reading the disclosure with reference to the drawings, wherein:
  • FIG. 1 shows a prior art embodiment of a double-sided, dual, in-line memory module mounting.
  • FIG. 2 shows an embodiment of a double-sided, dual, in-line memory module mounting.
  • FIGS. 3 a and 3 b show alternative arrangements of memory packages on a substrate.
  • FIG. 4 shows an embodiment of a memory system using double-sided memory modules.
  • FIGS. 5 a and 5 b show alternative embodiments of stacked memory modules.
  • FIG. 6 shows a connection diagram for an embodiment of a dual, in-line memory module having interchangeability.
  • FIG. 7 shows a connection diagram for an alternative embodiment of a dual, in-line memory module.
  • FIG. 8 shows a connection diagram for another alternative embodiment of a dual, in-line memory module.
  • FIG. 9 shows a block diagram of an embodiment of a method to design dual, in-line memory module.
  • DETAILED DESCRIPTION OF THE EMBODIMENTS
  • FIG. 1 shows a prior art embodiment of a double-sided, dual, in-line memory module (DIMM) mounting on a substrate. Double-sided refers to the fact that the memory modules are mounted on opposite sides of the substrate. The substrate 10 may be a multi-layered PCB, or any other substrate upon which DIMMs are mounted. Memory modules 12 a and 12 b are mounted on opposite sides of the substrate from each other, as are memory modules 14 a and 14 b. The substrate 10 has internally routed signal traces 16 a and 16 b. Stub 18 through via 13 allows the solder ball or other connection from the module 12 a to connect to the first signal trace 16 a.
  • The via 13 is manufactured on a larger pitch than the signal traces to afford extra width, and the use of several vias can limit the number of traces that can be routed through a single layer of the substrate 10. This may force additional layers and extra costs. In addition, to avoid shorting signals into the internal power and ground plane layers of the substrate 10, anti-pads are typically used in the power plane layers, which compromise power delivery to the memories within the modules.
  • Double-data rate memory (DDR) uses both the rising and falling edges of a clock signal to operate the memory, resulting in twice the speed of memories using either the leading or the falling edge of the clock signal. DDR3 is the third version of DDR. In DDR3, as well as other memory types, the command/address bus is a daisy-chained or ‘fly-by’ bus. This type of bus may have problems with signal integrity due to the unequal routing lengths caused by double-sided memory mounting.
  • As shown in FIG. 1, signal 16 a has a first routing length 28 a between the connections 20 and 26. The second routing length is between connection 26 on module 12 b and ball 30 on module 14 a. The second routing length 28 b is far shorter than the first. A similar length difference occurs for signal 16 b, with the first routing length being from connection 22 to connection 24, and the second routing length being from connection 24 on module 12 a to connection 32 on module 14 b. It must be noted that connections 20, 22, 24, 26, 30, 32, 34 and 36, are shown here as solder balls, but could be any type of connection used to provide connection between the integrated circuit die and the substrate.
  • The difference in routing lengths results in non-uniform effective channel impedance. This limits the ability of the devices to receive recognizable signals. Typically, systems are designed to have very regularly and evenly spaced loads and the line is tuned to match the loads. If there is no impedance matching, the signal integrity becomes questionable and higher data rates cannot be supported.
  • In one approach, the prior art has attempted to perform routing in the semiconductor of the die itself. Connections are redefined to be a different signal using logic in the die to ‘mirror’ the signal. Logic required in the data path introduces latency in the path, as well as overhead into the device manufacture.
  • It is possible to interchange the physical connectivity of the various connections at the memory module level, avoiding introduction of logic in the data path, while providing the same benefits as mirroring. An example is shown in FIG. 2.
  • The routing lengths in this embodiment have become uniform. The term ‘uniform’ as used here does not mean that they are exactly the same, although that may be the case. Uniformity, as used here, means that the impedances in the signal paths are closely matched to each other between loads. Routing length 1 is now the length from the connection 20 to the connection 30, and routing length 2 is the length from the connection 30 to the connection for the same signal on the next device, not shown. The loads are now more uniformly spaced, which allows the devices to support higher data rates with good signal integrity.
  • In addition, the configuration shown in FIG. 2 has a reduced number of vias. The interchange of signals from the far side of the bottom-side memory modules 12 b and 14 b have moved to the near side allow the signals to share vias. Reducing the number of vias eases the restrictions on trace spacing, allowing more traces to be placed in a given layer. In turn, this may reduce the number of layers needed in the substrate, reducing costs, as well as mitigating shorts in the power and ground planes.
  • In order for this approach to be practical, there must be some signals that can be interchanged between the two sides of the module. In order to allow better understanding of the definition of interchangeable signals, it is helpful to discuss how memory modules are typically laid out on a substrate. As shown in FIG. 3, a memory controller 38 has a data output of 64 bytes. Each module 40 a-40 h on the substrate 10 is a X8 module; each one can receive 8 bytes of memory.
  • It must be noted that in one embodiment of the invention, the interchangeable signals can be selected such that the footprint of the different types of packages can be optimized. As shown in memory module 40 a, for example, the data lines have been arranged such that is the package is a X4/X8 package, the data lines are either DQ0-3 for a X4 memory, or DQ0-7 for a X8 package. If the package is a X16 package, all of the data lines are present and DQ0-15 are available for interchangeability. Also, while data lines may be interchangeable within a byte ‘lane,’ such as DQ[0:7] and DQ[8:15], the adaptability of the interchangeable signals to different package types is enhance if the interchangeability is limited to be within nibbles, such as DQ[0:3], DQ[4:7], DQ[8:1] and DQ[12:15].
  • Interchangeability actually occurs at the controller 38. The DRAM and the DIMM have no ‘knowledge’ of what is on any data, whether that data is actually for DQ1 or DQ15. Therefore, these signals are interchangeable. Other types of signals have been identified as being interchangeable, as will be discussed further on. It must be noted that while the data out of the controller is 64 bytes, there are also address and rank-based signals that are sent from the controller in a daisy-chained or ‘fly-by’ fashion. The signals are passed along a bus and it is the distance between the relevant connections to this bus for which the routing length is desired to be uniform. The interchanging of the signals transmitted from the connections as shown in FIG. 2 is what provides this uniformity.
  • Interchangeability is possible in most memory layouts. For example, the memory system in FIG. 4 employs double-sided memory substrates. In addition to the modules 40 a-40 h on the side facing the viewer, modules such as 42 a are on the side away from the viewer. Memory modules arranged in such a system are generally addressed using rank-based signals, such as chip select (CS). In this particular embodiment, the address and rank based signals for the two different ranks are shown coming out of the controller. Generally, rank-based signals are not interchangeable.
  • Similarly, interchangeability can be performed using ‘stacked’ memory modules, such as those shown in FIGS. 5 a and 5 b. FIG. 5 a shows an example of a stacked memory arrangement where the connections between the two memory dies 44 a and 44 b are internal and they use a common connection array such as ball 46. In FIG. 5 b, each module 44 a and 44 b have their own external connection array, such as solder balls 46 a and 46 b. Interchangeability can be employed in this arrangement as well.
  • Modules are generally arranged as an array of connections, in rows and columns. As will be discussed with regards to FIGS. 6-8, the arrangement of the connections will be assumed to be in at least four columns, although three columns are possible. This assumption is based upon a typical DRAM layout of 15 or 16 rows of connections by 9 columns. Generally there are no connections in the middle 3 columns, leaving 3 columns on either ‘side’ of the module.
  • In the discussion of interchangeable signals, several different signal abbreviations may be used. These are included with their descriptions in the table below.
    Abbreviation Signal Name Comments
    VSS Core ground Usually tied together
    VSSQ I/O ground at substrate
    VDD Core power Usually tied together
    VDDQ I/O power at substrate
    RFU Reserved for future use
    CLK/CLK# DRAM input clock
    DQ[0:15] Data signals Lower and upper bytes
    (0:7, 8:15)
    DQS/DQS# Strobes for data clock One for upper and
    into the DRAM lower bytes
    DM Data mask signal One for upper and
    lower bytes
    VREFDQ Voltage reference pin
    for data
    CS Chip select
    CKE Clock enable
    ODT On-die termination
    RAS Row address select
    CAS Column address select
    WE Write enable
    RST Reset
    ZQ Impedance calibration pin
    sCS Stacked chip select
    sCKE Stacked clock enable
    sODT Stacked on-die termination
    sZQ Stacked impedance
    calibration pin
    A[0:15] Address
    BA[0:3] Bank address
    VREFCA Voltage reference for
    command/address
  • Interchangeable signals will generally include DQ signals within a byte ‘lane’ such as DQ[0:7] and DQ[8:15]. Bank addresses, BA[0:3] may be interchangeable. It is possible that BA[2:3] are not present, so only BA[0:1] may be interchanged. Address connections within a row, such as A[3:9] are interchangeable. Generally, VDD and VSS connection locations can be moved around to share vias as well, although this is not shown in the example.
  • FIG. 6 shows a general embodiment of a memory module layout to allow for interchangeable signals. As can be seen, the example is a 16×9 array of connections. The array has been arranged in nine columns, with the outer two columns 51, 52, 58 and 59 on either side being identified as for use by interchangeable signals and the middle two columns 53 and 56 being identified as for use by non-interchangeable signals. The outer two columns on each side may be interchangeable providing four interchangeable columns, or only the outer one column on each side providing only two interchangeable columns.
  • A more specific embodiment of a connection 16×9 layout is shown in FIG. 7. In this example, VDDQ and VSSQ have had their locations redefined to share vias front to back. Further, A3 and A4, A5 and A6, and A7 and A8 can share vias at the DIMM level. This particular layout has a further advantage that there are only 4 signals per row of the DIMM, allowing better trace separation for the signal traces, further increasing the signal integrity. Reserved for future use (RFU) connections at column 52, rows J and L may be used for sODT, and sCS. Similarly, RFU at column 58, row J could be used for sCKE, and at row D for sZQ.
  • It is possible to get a 15×9 connection layout with some modifications of these rules. If a 2:1 ration of signal to ground pattern can be achieved, and 2 connections are removed, it is possible to achieve a 15×9 connection layout with interchangeable connections. An embodiment of this is shown in FIG. 8. In this embodiment, the ODT signal has been removed and the bank address 3, BA3 and address 15, A15, share a connection. The RFU connection at column 52, row L becomes BA0.
  • With these possible layouts in mind, it is helpful to return to FIGS. 1 and 2. Imagine that the connections 20 and 22 correspond to a location in column 1 of a connection array, and connections 24 and 26 correspond to a location in column 9. In FIG. 1, this results in the uneven routing lengths and the extra vias. If the controller were to interchange the signals between columns 1 and 9, moving the signals that had previously been using connection 22 to column 9 and the signals previously using connection 26 to column 1, the result would appear as in FIG. 2. The connections 22 and 26 remain in the same place, the signals that had been routed to those columns are interchanged so that connections 20 and 22, and 24 and 26 can be connected together. The availability of interchangeable signals between the outer columns of the connection array allow for the optimization of the connection layout for double-sided DIMM or other module placement.
  • Further adjustments and variations on the interchangeable signals are of course possible. For example, the interchangeable signals can also be applied to stacked DRAM technology. In addition, variations of the package type can be employed. For example, the X16 package type may be used, as well as the X4/X8 package type.
  • Thus, although there has been described to this point a particular embodiment for a method and apparatus for interchangeable connections in a memory module, it is not intended that such specific references be considered as limitations upon the scope of this invention except in-so-far as set forth in the following claims.

Claims (16)

  1. 1. A memory module, comprising:
    an array of connections arranged in rows and columns such that there are first and second outer columns, and those connections in the first and second outer columns can be interchanged.
  2. 2. The memory module of claim 1, wherein the first outer column is a nearside column and the second outer column is a far-side column.
  3. 3. The memory module of claim 1, wherein there are third and fourth outer columns having interchangeable connections.
  4. 4. The memory module of claim 1, the memory module further comprising a package selected from the group comprised of: X16, and X4/X8.
  5. 5. A memory system, comprising:
    a first memory module mounted on a first side of a substrate, the first memory module comprising:
    an array of connections arranged in rows and columns such that there are first and second outer columns, and that connections in the first and second outer columns can be interchanged;
    a second memory module mounted on a second side of the substrate, comprising:
    an array of connections arranged in rows and columns such that there are first and second outer columns, and that connections in the first and second outer columns can be interchanged;
    a memory controller to control interchange of signals between first and second outer columns of the memory modules;
    signal traces in the substrate, wherein the connection in the first and second outer columns of the first and second memory modules are arranged such that signals routed on the traces have uniform routing lengths.
  6. 6. The memory system of claim 5, the substrate further comprising a multi-layered printed circuit board.
  7. 7. The memory system of claim 6, signal traces further comprising multiple signal traces in multiple layers of the printed circuit board.
  8. 8. The memory system of claim 5, the memory modules being packaged in a package selected from the group comprised of: X16 and X4/X8.
  9. 9. A memory device, comprising:
    a memory array having an array of memory connections arranged in rows and columns;
    a module to receive the memory array;
    a connector on the module having an array of connector connections arranged in rows and columns, such that the memory connections and the connector connections can be interchanged.
  10. 10. The memory device of claim 9, the module further comprising a dual, in-line memory module.
  11. 11. The memory array of claim 10, the module being selected from the group comprised of: a X16 package, and an X4/X8 package.
  12. 12. A method of designing a memory device, comprising:
    determining an interchangeable set of memory signals and a fixed set of memory signals;
    arranging the interchangeable set of memory signals in outer columns of a connection array; and
    arranging the fixed set of memory signals in inner columns of a connection array.
  13. 13. The method of claim 12, determining an interchangeable set of memory signals further comprising identifying address connections within a row as being interchangeable.
  14. 14. The method of claim 12, determining an interchangeable set of memory signals further comprising identifying bank address connections as being interchangeable.
  15. 15. The method of claim 12, arranging the interchangeable set of memory signals in outer column further comprising arranging the interchangeable set of memory signals in two outer columns on each side of the connection array.
  16. 16. The method of claim 12, arranging the interchangeable set of memory signals in outer column further comprising arranging the interchangeable set of memory signals in one outer column on each side of the connection array.
US10792350 2004-03-02 2004-03-02 Interchangeable connection arrays for double-sided memory module placement Abandoned US20050195629A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10792350 US20050195629A1 (en) 2004-03-02 2004-03-02 Interchangeable connection arrays for double-sided memory module placement

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US10792350 US20050195629A1 (en) 2004-03-02 2004-03-02 Interchangeable connection arrays for double-sided memory module placement
JP2007500868A JP2007525769A (en) 2004-03-02 2005-02-14 Interchangeable connection array for duplex dimm arrangement
PCT/US2005/004595 WO2005093757A1 (en) 2004-03-02 2005-02-14 Interchangeable connection arrays for double-sided dimm placement
EP20050713488 EP1723654B1 (en) 2004-03-02 2005-02-14 Interchangeable connection arrays for double-sided dimm placement
DE200560022053 DE602005022053D1 (en) 2004-03-02 2005-02-14 Interchangeable connection-arrays for double-sided dimm-placement
CN 200580006652 CN1926632B (en) 2004-03-02 2005-02-14 Interchangeable connection arrays for double-sided memory module placement
US11899497 US8099687B2 (en) 2004-03-02 2007-09-05 Interchangeable connection arrays for double-sided DIMM placement
US13339525 US8438515B2 (en) 2004-03-02 2011-12-29 Interchangeable connection arrays for double-sided DIMM placement
US13888627 US8775991B2 (en) 2004-03-02 2013-05-07 Interchangeable connection arrays for double-sided DIMM placement

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US11899497 Continuation US8099687B2 (en) 2004-03-02 2007-09-05 Interchangeable connection arrays for double-sided DIMM placement

Publications (1)

Publication Number Publication Date
US20050195629A1 true true US20050195629A1 (en) 2005-09-08

Family

ID=34911834

Family Applications (4)

Application Number Title Priority Date Filing Date
US10792350 Abandoned US20050195629A1 (en) 2004-03-02 2004-03-02 Interchangeable connection arrays for double-sided memory module placement
US11899497 Active US8099687B2 (en) 2004-03-02 2007-09-05 Interchangeable connection arrays for double-sided DIMM placement
US13339525 Active US8438515B2 (en) 2004-03-02 2011-12-29 Interchangeable connection arrays for double-sided DIMM placement
US13888627 Active US8775991B2 (en) 2004-03-02 2013-05-07 Interchangeable connection arrays for double-sided DIMM placement

Family Applications After (3)

Application Number Title Priority Date Filing Date
US11899497 Active US8099687B2 (en) 2004-03-02 2007-09-05 Interchangeable connection arrays for double-sided DIMM placement
US13339525 Active US8438515B2 (en) 2004-03-02 2011-12-29 Interchangeable connection arrays for double-sided DIMM placement
US13888627 Active US8775991B2 (en) 2004-03-02 2013-05-07 Interchangeable connection arrays for double-sided DIMM placement

Country Status (6)

Country Link
US (4) US20050195629A1 (en)
EP (1) EP1723654B1 (en)
JP (1) JP2007525769A (en)
CN (1) CN1926632B (en)
DE (1) DE602005022053D1 (en)
WO (1) WO2005093757A1 (en)

Cited By (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060170097A1 (en) * 2005-02-02 2006-08-03 Moon-Jung Kim Printed wires arrangement for in-line memory (IMM) module
US20080037353A1 (en) * 2006-07-31 2008-02-14 Metaram, Inc. Interface circuit system and method for performing power saving operations during a command-related latency
US20080062734A1 (en) * 2004-03-02 2008-03-13 Leddige Michael W Interchangeable connection arrays for double-sided DIMM placement
US7730338B2 (en) 2006-07-31 2010-06-01 Google Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US7761724B2 (en) 2006-07-31 2010-07-20 Google Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US8019589B2 (en) 2006-07-31 2011-09-13 Google Inc. Memory apparatus operable to perform a power-saving operation
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
EP2419971A1 (en) * 2009-04-17 2012-02-22 Hewlett-Packard Company Method and system for reducing trace length and capacitance in a large memory footprint background
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US8154935B2 (en) 2006-07-31 2012-04-10 Google Inc. Delaying a signal communicated from a system to at least one of a plurality of memory circuits
US8169233B2 (en) 2009-06-09 2012-05-01 Google Inc. Programming of DIMM termination resistance values
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8280714B2 (en) 2006-07-31 2012-10-02 Google Inc. Memory circuit simulation system and method with refresh capabilities
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US8566516B2 (en) 2006-07-31 2013-10-22 Google Inc. Refresh management of memory modules
US8582339B2 (en) 2005-09-02 2013-11-12 Google Inc. System including memory stacks
US8588017B2 (en) 2010-10-20 2013-11-19 Samsung Electronics Co., Ltd. Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same
US20130314968A1 (en) * 2011-02-09 2013-11-28 Ian Shaeffer Offsetting clock package pins in a clamshell topology to improve signal integrity
US20140159237A1 (en) * 2012-12-10 2014-06-12 Heung-Kyu Kwon Semiconductor package and method for routing the package
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US8972673B2 (en) 2006-07-31 2015-03-03 Google Inc. Power management of memory circuits by virtual memory simulation
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US20180027682A1 (en) * 2016-07-22 2018-01-25 Intel Corporation Thermally Efficient Compute Resource Apparatuses and Methods
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006005955B4 (en) * 2005-02-02 2007-01-25 Samsung Electronics Co., Ltd., Suwon Inline Memory Module
US8856434B2 (en) 2008-09-26 2014-10-07 Cypress Semiconductor Corporation Memory system and method
US8095747B2 (en) * 2008-09-26 2012-01-10 Cypress Semiconductor Corporation Memory system and method
CN101727970B (en) 2009-11-03 2012-11-21 深圳市共进电子股份有限公司 Method for reducing radiation generated by synchronous dynamic random access memory (SDRAM)
CN102289400B (en) * 2011-09-05 2013-07-31 浪潮电子信息产业股份有限公司 Method for increasing DIMM (Double Inline Memory Module) testing efficiency
CN102508749B (en) * 2011-10-19 2013-08-14 浪潮集团有限公司 Method for testing dual inline memory modules (DIMM)
WO2013110179A1 (en) 2012-01-27 2013-08-01 Mosaid Technologies Incorporated Method and apparatus for connecting memory dies to form a memory system
US9786354B2 (en) * 2013-07-10 2017-10-10 Samsung Electronics Co., Ltd. Memory module
US9934143B2 (en) 2013-09-26 2018-04-03 Intel Corporation Mapping a physical address differently to different memory devices in a group
JP6067541B2 (en) * 2013-11-08 2017-01-25 株式会社東芝 Assembly method of the memory system and the memory system
US9265152B2 (en) 2013-12-17 2016-02-16 Lenovo Enterprise Solutions (Singapore) Pte. Ltd. Dual side staggered surface mount dual in-line memory module
WO2017018991A1 (en) * 2015-07-24 2017-02-02 Hewlett Packard Enterprise Development Lp Modification of a bus channel
US9818457B1 (en) 2016-09-30 2017-11-14 Intel Corporation Extended platform with additional memory module slots per CPU socket

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6307769B1 (en) * 1999-09-02 2001-10-23 Micron Technology, Inc. Semiconductor devices having mirrored terminal arrangements, devices including same, and methods of testing such semiconductor devices
US20040230932A1 (en) * 2002-09-27 2004-11-18 Rory Dickmann Method for controlling semiconductor chips and control apparatus
US20050007807A1 (en) * 2002-10-17 2005-01-13 Martin Chris G. Apparatus and method for mounting microelectronic devices on a mirrored board assembly
US20050030815A1 (en) * 2002-05-21 2005-02-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory module
US20050036350A1 (en) * 2003-08-13 2005-02-17 So Byung-Se Memory module
US20060171247A1 (en) * 2005-02-03 2006-08-03 Wolfgang Hoppe Semiconductor memory module with bus architecture
US20060233037A1 (en) * 2003-09-19 2006-10-19 Rory Dickman Method and apparatus for operating electronic semiconductor chips via signal lines

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5208782A (en) * 1989-02-09 1993-05-04 Hitachi, Ltd. Semiconductor integrated circuit device having a plurality of memory blocks and a lead on chip (LOC) arrangement
EP0473796A4 (en) * 1990-03-15 1994-05-25 Fujitsu Ltd Semiconductor device having a plurality of chips
JPH07135301A (en) * 1993-09-16 1995-05-23 Mitsubishi Electric Corp Semiconductor memory
JPH07288282A (en) * 1994-04-18 1995-10-31 Hitachi Ltd Semiconductor device
JP3718008B2 (en) * 1996-02-26 2005-11-16 株式会社ルネサス東日本セミコンダクタ Memory module and method of manufacturing the same
JP3904296B2 (en) * 1996-11-12 2007-04-11 新潟精密株式会社 Memory system
US6202110B1 (en) * 1997-03-31 2001-03-13 International Business Machines Corporation Memory cards with symmetrical pinout for back-to-back mounting in computer system
JP2000340737A (en) * 1999-05-31 2000-12-08 Mitsubishi Electric Corp Semiconductor package and body mounted therewith
US7404032B2 (en) * 2000-01-05 2008-07-22 Rambus Inc. Configurable width buffered module having switch elements
US6574724B1 (en) * 2000-02-18 2003-06-03 Texas Instruments Incorporated Microprocessor with non-aligned scaled and unscaled addressing
US6449166B1 (en) * 2000-08-24 2002-09-10 High Connection Density, Inc. High capacity memory module with higher density and improved manufacturability
KR100454123B1 (en) * 2001-12-06 2004-10-26 삼성전자주식회사 Semiconductor integrated circuit devices and modules with the same
US6875930B2 (en) * 2002-04-18 2005-04-05 Hewlett-Packard Development Company, L.P. Optimized conductor routing for multiple components on a printed circuit board
JP4242117B2 (en) 2002-07-11 2009-03-18 株式会社ルネサステクノロジ Storage device
JP2004055009A (en) * 2002-07-18 2004-02-19 Renesas Technology Corp Semiconductor memory module
DE10238812B4 (en) * 2002-08-23 2005-05-25 Infineon Technologies Ag A semiconductor memory device with variable contact assignment and corresponding semiconductor device
DE10258199B4 (en) * 2002-12-12 2005-03-10 Infineon Technologies Ag Circuit arrangement having a number of integrated circuit components on a carrier substrate and method for testing such a circuit arrangement
US7183643B2 (en) * 2003-11-04 2007-02-27 Tessera, Inc. Stacked packages and systems incorporating the same
US20050195629A1 (en) * 2004-03-02 2005-09-08 Leddige Michael W. Interchangeable connection arrays for double-sided memory module placement
US7260691B2 (en) * 2004-06-30 2007-08-21 Intel Corporation Apparatus and method for initialization of a double-sided DIMM having at least one pair of mirrored pins
US7417883B2 (en) * 2004-12-30 2008-08-26 Intel Corporation I/O data interconnect reuse as repeater
US7359279B2 (en) * 2005-03-31 2008-04-15 Sandisk 3D Llc Integrated circuit memory array configuration including decoding compatibility with partial implementation of multiple memory layers
JP4321543B2 (en) 2006-04-12 2009-08-26 トヨタ自動車株式会社 Vehicle environment monitoring device
DE102006051514B4 (en) * 2006-10-31 2010-01-21 Qimonda Ag Memory module and method of operating a memory module
US8689508B2 (en) * 2008-05-28 2014-04-08 Steeltec Supply, Inc. Extra strength backing stud having notched flanges
JP2009293938A (en) 2008-06-02 2009-12-17 Denso Corp Turn detector, program, and vehicle orientation detector
JP2011031779A (en) 2009-08-03 2011-02-17 Kanto Auto Works Ltd clip

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6307769B1 (en) * 1999-09-02 2001-10-23 Micron Technology, Inc. Semiconductor devices having mirrored terminal arrangements, devices including same, and methods of testing such semiconductor devices
US20050030815A1 (en) * 2002-05-21 2005-02-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory module
US20040230932A1 (en) * 2002-09-27 2004-11-18 Rory Dickmann Method for controlling semiconductor chips and control apparatus
US20050007807A1 (en) * 2002-10-17 2005-01-13 Martin Chris G. Apparatus and method for mounting microelectronic devices on a mirrored board assembly
US20050036350A1 (en) * 2003-08-13 2005-02-17 So Byung-Se Memory module
US20060233037A1 (en) * 2003-09-19 2006-10-19 Rory Dickman Method and apparatus for operating electronic semiconductor chips via signal lines
US20060171247A1 (en) * 2005-02-03 2006-08-03 Wolfgang Hoppe Semiconductor memory module with bus architecture

Cited By (77)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8099687B2 (en) * 2004-03-02 2012-01-17 Intel Corporation Interchangeable connection arrays for double-sided DIMM placement
US8775991B2 (en) 2004-03-02 2014-07-08 Intel Corporation Interchangeable connection arrays for double-sided DIMM placement
US20080062734A1 (en) * 2004-03-02 2008-03-13 Leddige Michael W Interchangeable connection arrays for double-sided DIMM placement
US7394160B2 (en) * 2005-02-02 2008-07-01 Samsung Electronics Co., Ltd. Printed wires arrangement for in-line memory (IMM) module
US20060170097A1 (en) * 2005-02-02 2006-08-03 Moon-Jung Kim Printed wires arrangement for in-line memory (IMM) module
US8060774B2 (en) 2005-06-24 2011-11-15 Google Inc. Memory systems and memory modules
US8615679B2 (en) 2005-06-24 2013-12-24 Google Inc. Memory modules with reliability and serviceability functions
US9171585B2 (en) 2005-06-24 2015-10-27 Google Inc. Configurable memory circuit system and method
US10013371B2 (en) 2005-06-24 2018-07-03 Google Llc Configurable memory circuit system and method
US9507739B2 (en) 2005-06-24 2016-11-29 Google Inc. Configurable memory circuit system and method
US8359187B2 (en) 2005-06-24 2013-01-22 Google Inc. Simulating a different number of memory circuit devices
US8386833B2 (en) 2005-06-24 2013-02-26 Google Inc. Memory systems and memory modules
US8811065B2 (en) 2005-09-02 2014-08-19 Google Inc. Performing error detection on DRAMs
US8582339B2 (en) 2005-09-02 2013-11-12 Google Inc. System including memory stacks
US8619452B2 (en) 2005-09-02 2013-12-31 Google Inc. Methods and apparatus of stacking DRAMs
US9542352B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US8089795B2 (en) 2006-02-09 2012-01-03 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US9542353B2 (en) 2006-02-09 2017-01-10 Google Inc. System and method for reducing command scheduling constraints of memory circuits
US9632929B2 (en) 2006-02-09 2017-04-25 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US9727458B2 (en) 2006-02-09 2017-08-08 Google Inc. Translating an address associated with a command communicated between a system and memory circuits
US8566556B2 (en) 2006-02-09 2013-10-22 Google Inc. Memory module with memory stack and interface with enhanced capabilities
US8797779B2 (en) 2006-02-09 2014-08-05 Google Inc. Memory module with memory stack and interface with enhanced capabilites
US8112266B2 (en) 2006-07-31 2012-02-07 Google Inc. Apparatus for simulating an aspect of a memory circuit
US20080037353A1 (en) * 2006-07-31 2008-02-14 Metaram, Inc. Interface circuit system and method for performing power saving operations during a command-related latency
US8244971B2 (en) 2006-07-31 2012-08-14 Google Inc. Memory circuit system and method
US8280714B2 (en) 2006-07-31 2012-10-02 Google Inc. Memory circuit simulation system and method with refresh capabilities
US8327104B2 (en) 2006-07-31 2012-12-04 Google Inc. Adjusting the timing of signals associated with a memory system
US7730338B2 (en) 2006-07-31 2010-06-01 Google Inc. Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits
US8340953B2 (en) 2006-07-31 2012-12-25 Google, Inc. Memory circuit simulation with power saving capabilities
US8154935B2 (en) 2006-07-31 2012-04-10 Google Inc. Delaying a signal communicated from a system to at least one of a plurality of memory circuits
US8972673B2 (en) 2006-07-31 2015-03-03 Google Inc. Power management of memory circuits by virtual memory simulation
US8868829B2 (en) 2006-07-31 2014-10-21 Google Inc. Memory circuit system and method
US7761724B2 (en) 2006-07-31 2010-07-20 Google Inc. Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit
US8671244B2 (en) 2006-07-31 2014-03-11 Google Inc. Simulating a memory standard
US8019589B2 (en) 2006-07-31 2011-09-13 Google Inc. Memory apparatus operable to perform a power-saving operation
US8041881B2 (en) 2006-07-31 2011-10-18 Google Inc. Memory device with emulated characteristics
US8631220B2 (en) 2006-07-31 2014-01-14 Google Inc. Adjusting the timing of signals associated with a memory system
US8566516B2 (en) 2006-07-31 2013-10-22 Google Inc. Refresh management of memory modules
US8745321B2 (en) 2006-07-31 2014-06-03 Google Inc. Simulating a memory standard
US9047976B2 (en) 2006-07-31 2015-06-02 Google Inc. Combined signal delay and power saving for use with a plurality of memory circuits
US8077535B2 (en) 2006-07-31 2011-12-13 Google Inc. Memory refresh apparatus and method
US8595419B2 (en) 2006-07-31 2013-11-26 Google Inc. Memory apparatus operable to perform a power-saving operation
US8090897B2 (en) 2006-07-31 2012-01-03 Google Inc. System and method for simulating an aspect of a memory circuit
US8601204B2 (en) 2006-07-31 2013-12-03 Google Inc. Simulating a refresh operation latency
US8796830B1 (en) 2006-09-01 2014-08-05 Google Inc. Stackable low-profile lead frame package
US8370566B2 (en) 2006-10-05 2013-02-05 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8751732B2 (en) 2006-10-05 2014-06-10 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8397013B1 (en) 2006-10-05 2013-03-12 Google Inc. Hybrid memory module
US8977806B1 (en) 2006-10-05 2015-03-10 Google Inc. Hybrid memory module
US8055833B2 (en) 2006-10-05 2011-11-08 Google Inc. System and method for increasing capacity, performance, and flexibility of flash storage
US8130560B1 (en) 2006-11-13 2012-03-06 Google Inc. Multi-rank partial width memory modules
US8760936B1 (en) 2006-11-13 2014-06-24 Google Inc. Multi-rank partial width memory modules
US8446781B1 (en) 2006-11-13 2013-05-21 Google Inc. Multi-rank partial width memory modules
US8209479B2 (en) 2007-07-18 2012-06-26 Google Inc. Memory circuit system and method
US8080874B1 (en) 2007-09-14 2011-12-20 Google Inc. Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween
US8111566B1 (en) 2007-11-16 2012-02-07 Google, Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US8675429B1 (en) 2007-11-16 2014-03-18 Google Inc. Optimal channel design for memory devices for providing a high-speed memory interface
US8730670B1 (en) 2007-12-18 2014-05-20 Google Inc. Embossed heat spreader
US8081474B1 (en) 2007-12-18 2011-12-20 Google Inc. Embossed heat spreader
US8705240B1 (en) 2007-12-18 2014-04-22 Google Inc. Embossed heat spreader
US8631193B2 (en) 2008-02-21 2014-01-14 Google Inc. Emulation of abstracted DIMMS using abstracted DRAMS
US8438328B2 (en) 2008-02-21 2013-05-07 Google Inc. Emulation of abstracted DIMMs using abstracted DRAMs
US8386722B1 (en) 2008-06-23 2013-02-26 Google Inc. Stacked DIMM memory interface
US8762675B2 (en) 2008-06-23 2014-06-24 Google Inc. Memory system for synchronous data transmission
US8819356B2 (en) 2008-07-25 2014-08-26 Google Inc. Configurable multirank memory system with interface circuit
US8335894B1 (en) 2008-07-25 2012-12-18 Google Inc. Configurable memory system with interface circuit
US8866023B2 (en) * 2009-04-17 2014-10-21 Hewlett-Packard Development Company, L.P. Method and system for reducing trace length and capacitance in a large memory footprint
US20120175160A1 (en) * 2009-04-17 2012-07-12 Kadri Rachid M Method and system for reducing trace length and capacitance in a large memory footprint
EP2419971A4 (en) * 2009-04-17 2013-03-27 Hewlett Packard Co Method and system for reducing trace length and capacitance in a large memory footprint background
EP2419971A1 (en) * 2009-04-17 2012-02-22 Hewlett-Packard Company Method and system for reducing trace length and capacitance in a large memory footprint background
US8169233B2 (en) 2009-06-09 2012-05-01 Google Inc. Programming of DIMM termination resistance values
US8588017B2 (en) 2010-10-20 2013-11-19 Samsung Electronics Co., Ltd. Memory circuits, systems, and modules for performing DRAM refresh operations and methods of operating the same
US9336834B2 (en) * 2011-02-09 2016-05-10 Rambus Inc. Offsetting clock package pins in a clamshell topology to improve signal integrity
US20130314968A1 (en) * 2011-02-09 2013-11-28 Ian Shaeffer Offsetting clock package pins in a clamshell topology to improve signal integrity
US10056321B2 (en) * 2012-12-10 2018-08-21 Samsung Electronics Co., Ltd. Semiconductor package and method for routing the package
US20140159237A1 (en) * 2012-12-10 2014-06-12 Heung-Kyu Kwon Semiconductor package and method for routing the package
US20180027682A1 (en) * 2016-07-22 2018-01-25 Intel Corporation Thermally Efficient Compute Resource Apparatuses and Methods

Also Published As

Publication number Publication date Type
EP1723654B1 (en) 2010-06-30 grant
DE602005022053D1 (en) 2010-08-12 grant
US20080062734A1 (en) 2008-03-13 application
WO2005093757A1 (en) 2005-10-06 application
US8775991B2 (en) 2014-07-08 grant
US8099687B2 (en) 2012-01-17 grant
JP2007525769A (en) 2007-09-06 application
CN1926632B (en) 2011-08-03 grant
US20120199973A1 (en) 2012-08-09 application
US8438515B2 (en) 2013-05-07 grant
EP1723654A1 (en) 2006-11-22 application
US20130341790A1 (en) 2013-12-26 application
CN1926632A (en) 2007-03-07 application

Similar Documents

Publication Publication Date Title
US7414917B2 (en) Re-driving CAwD and rD signal lines
US6208546B1 (en) Memory module
US7053478B2 (en) Pitch change and chip scale stacking system
US6542393B1 (en) Dual-bank memory module with stacked DRAM chips having a concave-shaped re-route PCB in-between
US7324352B2 (en) High capacity thin module system and method
US6889304B2 (en) Memory device supporting a dynamically configurable core organization
US7123497B2 (en) Memory module and memory system
US7200021B2 (en) Stacked DRAM memory chip for a dual inline memory module (DIMM)
US6121681A (en) Semiconductor device
US20080094808A1 (en) Methods and apparatus of dual inline memory modules for flash memory
US6937494B2 (en) Memory module, memory chip, and memory system
US7181584B2 (en) Dynamic command and/or address mirroring system and method for memory modules
US7289386B2 (en) Memory module decoder
US20050036350A1 (en) Memory module
US7266639B2 (en) Memory rank decoder for a multi-rank Dual Inline Memory Module (DIMM)
US6381141B2 (en) Integrated device and method for routing a signal through the device
US20050281096A1 (en) High-density memory module utilizing low-density memory components
US5012389A (en) Board wiring pattern for a high density memory module
US20060004981A1 (en) Apparatus and method for initialization of a double-sided dimm having at least one pair of mirrored pins
US7830692B2 (en) Multi-chip memory device with stacked memory chips, method of stacking memory chips, and method of controlling operation of multi-chip package memory
US8659141B2 (en) Stub minimization using duplicate sets of terminals for wirebond assemblies without windows
US20020043719A1 (en) Semiconductor device
US6757751B1 (en) High-speed, multiple-bank, stacked, and PCB-mounted memory module
US8516185B2 (en) System and method utilizing distributed byte-wise buffers on a memory module
US7636274B2 (en) Memory module with a circuit providing load isolation and memory domain translation

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTEL CORPORATION (A DELAWARE CORPORATION), CALIFO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEDDIGE, MICHAEL W.;BAINS, KULJIT;SPRIETSMA, JOHN T.;REEL/FRAME:015084/0142;SIGNING DATES FROM 20040301 TO 20040302