JP2009010073A - 半導体パッケージおよびこれを用いた半導体装置 - Google Patents
半導体パッケージおよびこれを用いた半導体装置 Download PDFInfo
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- JP2009010073A JP2009010073A JP2007168495A JP2007168495A JP2009010073A JP 2009010073 A JP2009010073 A JP 2009010073A JP 2007168495 A JP2007168495 A JP 2007168495A JP 2007168495 A JP2007168495 A JP 2007168495A JP 2009010073 A JP2009010073 A JP 2009010073A
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- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/1579—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Abstract
【解決手段】フリップチップ接続用パッド16が形成された領域の外方に、ランドパッド18の形成領域が設けられた半導体パッケージ60において、ランドパッド18の形成領域に、ランドパッド18を露出させるように保護部材39が形成され、保護部材39は、フリップチップ接続用パッド16を囲んで配置される枠状構造部39Aと、枠状構造部39Aの外方側に配置される支持膜部39Bと、からなることを特徴とする半導体パッケージ60およびこれを用いた半導体装置70である。
【選択図】図11
Description
低粘性のアンダーフィル樹脂を使用した場合には、アンダーフィル樹脂がフリップチップ接続領域から多少流れ出すことがある。従来は、見栄えを多少損ねる程度であり無視できたが、半導体チップそのものが小型化し、半導体チップ、その他の電子部品の搭載密度が高くなってくると、このアンダーフィル樹脂の流れ出しが、周辺のチップや電子部品に悪影響をもたらすおそれが生じてきた。
フリップチップ接続用パッド16には半導体素子10に(図12参照)形成されたバンプ12(金バンプ)が接合されるのに対して、BGA接続やLGA接続等のランドパッド18にははんだボールや接続用のピン等が接続される。このため、フリップチップ接続用パッド16では銅パッドの表面にはんだが被着される。また、BGA接続やLGA接続等のランドパッド18においても銅パッドを用いることもできるが、より好適なランドパッド18とするには、銅パッドの表面にめっき36(たとえば、ニッケルめっきと金めっき)を施すことが望ましい。
具体的には、ランドパッド18となるパッド部18aにめっき36を処理する際においては、フリップチップ接続用パッド16となるパッド部16aをめっきレジストにより被覆してめっき36を施し、フリップチップ接続用パッド16となるパッド部16aにはんだ粉52によりはんだコートをする際においては、ランドパッド18にマスキングテープ42を貼り付け、ランドパッド18を被覆した状態で処理している。
また、前記支持膜部は、前記ランドパッドの最外周位置よりも外方側に形成されていることを特徴とする。
以上の構成を採用することにより、BGA接続やLGA接続をするためのランドパッド形成領域に対してマスキングテープを隙間なく貼り付けることができるため、半導体パッケージの歩留まりが向上し、半導体パッケージの製造コストを低減することができる。
また、異種の半導体パッケージを本発明における半導体パッケージに積層してもよい。
図1は、片面銅張りの樹脂基板にレジストパターンを形成した状態を示す断面図である。レジストパターン34は、樹脂基板30に貼り付けられた銅箔31にレジストフィルム33を被着し、レジストフィルム33を露光および現像することにより形成される。レジストパターン34は、図示しない所要の配線パターン、フリップチップ接続用パッド16、BGA接続またはLGA接続をするためのランドパッド18のパターン部分を被覆するように形成されている。
図3は、樹脂基板の表面にフリップチップ接続用パッドとなるパッド部とランドパッドのみを露出させた状態でソルダーレジストが被着されている状態を示す断面図である。樹脂基板30の表面をソルダーレジスト38によって被覆し、露光および現像をして樹脂基板30の表面にフリップチップ接続用パッドとなるパッド部16aとランドパッド18となるパッド部18aのみを露出させる。
具体的には、フリップチップ接続後において半導体素子10を上にした状態で半導体装置70を正面側から見た場合、半導体装置70が上に凸状となる変形をすることが知られている。そこで、ソルダーレジスト38を半導体パッケージ60の基板に2度塗布することにより、半導体装置70を凹状に変形させようとする応力を増すことができ、半導体装置70に生じる反りを緩和させることができる。
マスキングテープ42によりランドパッド18の形成領域を確実に覆うためには、支持膜部39Bを、最外方のランドパッド18の配設位置よりもさらに外方側の位置に少なくとも1つ配設しておけばよい。
なお、マスキングテープ42は、実際には樹脂フィルムからなるセパレータから剥離して対象物に粘着して使用する。マスキングテープ42を枠状構造部39Aおよび支持膜部39Bの表面にそれぞれ粘着することにより、ランドパッド18は外部からシールされた状態になる。
なお、上述したはんだ粉52を粘着層50によりパッド部16aの表面に付着させ、リフローによってパッド部16aの表面にはんだ52aを被着させる方法としては、たとえば特開平7−7244号公報に記載されている方法を利用することができる。
以上のようにしてフリップチップ接続用パッド16とランドパッド18を備えた基板を形成した後、樹脂基板30の下面に形成されたパッドPに外部接続端子15を取り付ければ、図11に示す半導体パッケージ60が得られる。この半導体パッケージ60は、フリップチップ接続用パッド16が形成された領域の外方に位置するランドパッド18の形成領域に、ランドパッド18を露出させるようにして保護部材である2層目のソルダーレジスト39により、枠状構造部39Aと枠状構造部39Aの外方側に枠状構造部39Aを囲むように枠状に形成された支持膜部39Bとが形成されている。図11における半導体パッケージ60には、支持膜部39Bによる枠体が2箇所に形成されている。
上述したマスキングテープ42を使用する半導体パッケージ60の製造方法はこれらの問題がない点で優れており、実際の半導体パッケージ60の量産方法として好適に利用することができる方法として有効である。
アンダーフィル樹脂37を注入する際にアウトガスが発生することがあるが、ランドパッド18が形成された領域には枠状構造部39Aと支持膜部39Bがランドパッド18の表面位置よりも高い位置に突出しているため、アウトガスがランドパッド18に接触することを防ぎランドパッド18の表面を保護することができる。これにより、ランドパッド18の表面処理(例えば、ニッケルめっきと金めっき)の状態を好適に維持することが可能となる。図12は、本実施形態にかかる半導体パッケージを用いた半導体装置の構造例を示す断面図である。
先にも説明したとおり、下層側半導体装置70Bにおけるランドパッド18は、枠状構造部39Aと支持膜部39Bとによりアンダーフィル樹脂37を注入する際におけるアンダーフィル樹脂37からのアウトガスから保護されているため、上層側の半導体装置70Aにおけるはんだボール15Aと下層側の半導体装置70Bのランドパッド18に高品位な状態で接続することが可能となり、接続の信頼性が向上する。
支持膜部39Bは、枠状構造部39Aと共にランドパッド18の形成領域内をマスキングテープ42によって平坦に遮蔽することができればよく、格子状や散点的に形成されていても良いし、ランドパッド18の形成領域内の全体に配設し、ランドパッド18部分のみを露出させた形態であってもよい。さらには、枠状構造物39Aの外方側に支持膜部39Bを複数形成した形態を採用することもできる。
さらに、本実施形態においては、図4に示すように樹脂基板30の表面全体を1層目のソルダーレジスト38によって被覆し、露光および現像をして樹脂基板30の表面にフリップチップ接続用パッドとなるパッド部16aとランドパッド18となるパッド部18aのみを露出させた後、図5に示すようにランドパッド18の形成領域に2層目のソルダーレジストを被着することにより枠状構造部39Aと支持膜部39Bを形成する形態について説明しているが、フリップチップ接続用パッド16の形成領域に1層目のソルダーレジスト38を被着させず、1層目のソルダーレジスト38により枠状構造部と支持膜部を形成する形態であっても本実施形態と同様の作用効果を得ることができる。
12 バンプ
14 基板
15 外部接続端子
15A はんだボール
16 フリップチップ接続用パッド
16a フリップチップ接続用パッドとなるパッド部
18 ランドパッド
18a ランドパッドとなるパッド部
30 樹脂基板
31 銅箔
33 レジストフィルム
34 レジストパターン
36 めっき
37 アンダーフィル樹脂
38 ソルダーレジスト
39 2層目のソルダーレジスト(保護部材)
39A 枠状構造部
39B 支持膜部
40 ワーク
42 マスキングテープ
50 粘着層
52 はんだ粉
52a はんだ
54 フラックス
60 半導体パッケージ
70,70A,70B 半導体装置
D ダム
P パッド
S 隙間
Claims (7)
- フリップチップ接続用パッドが形成された領域の外方に、ランドパッドの形成領域が設けられた半導体パッケージにおいて、
前記ランドパッドの形成領域に、ランドパッドを露出させるように保護部材が形成され、
該保護部材は、前記フリップチップ接続用パッドを囲んで配置される枠状構造部と、該枠状構造部の外方側に配置される支持膜部と、からなることを特徴とする半導体パッケージ。 - 前記支持膜部は、前記枠状構造部を外方側から囲む枠状に形成されていることを特徴とする請求項1記載の半導体パッケージ。
- 前記支持膜部は、前記枠状構造部の外方側に散点的に形成されていることを特徴とする請求項1記載の半導体パッケージ。
- 前記支持膜部は、前記ランドパッドの最外周位置よりも外方側に形成されていることを特徴とする請求項1〜3のうちのいずれか一項に記載の半導体パッケージ。
- 前記枠状構造部と前記支持膜部の高さは同じ高さに形成されていることを特徴とする請求項1〜4のうちのいずれか一項に記載の半導体パッケージ。
- 請求項1〜5のうちのいずれか一項記載の半導体パッケージに、半導体素子が搭載された半導体装置であって、
半導体パッケージに搭載された半導体素子がフリップチップ接続により接続されていることを特徴とする半導体装置。 - 請求項6記載の半導体装置を上下方向に積層し、上層側の半導体装置における外部接続端子が下層側の半導体装置におけるランドパッドに接続されていることを特徴とする半導体装置。
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US12/146,924 US7825499B2 (en) | 2007-06-27 | 2008-06-26 | Semiconductor package and trenched semiconductor power device using the same |
TW097123884A TWI445146B (zh) | 2007-06-27 | 2008-06-26 | 半導體封裝及使用其之半導體裝置 |
CN2008101261361A CN101335253B (zh) | 2007-06-27 | 2008-06-27 | 半导体封装体以及使用半导体封装体的半导体器件 |
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JP2004281939A (ja) * | 2003-03-18 | 2004-10-07 | Fujitsu Ltd | 半導体装置とその製造方法、および半導体装置前駆体とその製造方法 |
JP2007504676A (ja) * | 2003-09-05 | 2007-03-01 | サンミナ−エスシーアイ コーポレーション | スタック式電子アセンブリ |
JP2007115789A (ja) * | 2005-10-19 | 2007-05-10 | Matsushita Electric Ind Co Ltd | 積層型半導体装置および積層型半導体装置の製造方法 |
Cited By (5)
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JP2010087018A (ja) * | 2008-09-29 | 2010-04-15 | Kyocer Slc Technologies Corp | 配線基板およびその製造方法 |
JP2012079854A (ja) * | 2010-09-30 | 2012-04-19 | Renesas Electronics Corp | 半導体装置の製造方法 |
JP2012204733A (ja) * | 2011-03-28 | 2012-10-22 | Kyocer Slc Technologies Corp | 配線基板 |
JP2014103198A (ja) * | 2012-11-19 | 2014-06-05 | J Devices:Kk | 半導体装置及びその製造方法 |
US9293419B2 (en) | 2014-04-17 | 2016-03-22 | Panasonic Intellectual Property Management Co., Ltd. | Semiconductor package and semiconductor device |
Also Published As
Publication number | Publication date |
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CN101335253A (zh) | 2008-12-31 |
TW200903759A (en) | 2009-01-16 |
US20090001606A1 (en) | 2009-01-01 |
US7825499B2 (en) | 2010-11-02 |
TWI445146B (zh) | 2014-07-11 |
CN101335253B (zh) | 2012-06-13 |
JP4986738B2 (ja) | 2012-07-25 |
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