CN104795371B - 扇出型封装件及其形成方法 - Google Patents

扇出型封装件及其形成方法 Download PDF

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Publication number
CN104795371B
CN104795371B CN201410827179.8A CN201410827179A CN104795371B CN 104795371 B CN104795371 B CN 104795371B CN 201410827179 A CN201410827179 A CN 201410827179A CN 104795371 B CN104795371 B CN 104795371B
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layer
opening
conductive layer
dielectric layer
packaging part
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CN104795371A (zh
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施婉婷
刘乃玮
林俊成
黄震麟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种封装件，其中的一个实施例是包括模塑料的封装件，模塑料横向包封具有接触焊盘的芯片。第一介电层形成在模塑料和芯片上面，并且具有暴露接触焊盘的第一开口。第一金属化层形成在第一介电层上面，其中，第一金属化层填充第一开口。第二介电层形成在第一金属化层和第一介电层上面，并且具有位于第一开口上方的第二开口。第二金属化层形成在第二介电层上面并且形成在第二开口中。本发明还提供了一种制造封装件的方法。

Description

扇出型封装件及其形成方法
技术领域
本发明总体涉及半导体器件，更具体地，涉及封装件及其形成方法。
背景技术
半导体器件用于各种电子应用中，作为实例，诸如,个人计算机、手机、数码相机和其他电子设备。半导体器件通常通过以下步骤制造：在半导体衬底上方循序地沉积绝缘或介电层、导电层和半导体材料层，以及使用光刻来图案化各个材料层以在其上形成电路部件和元件。通常在单个半导体晶圆上制造数十或数百个集成电路。通过沿着划线锯切集成电路来分割单独的管芯。然后分别封装单独的管芯，例如，封装成多芯片模块或其他类型的封装件。
通过不断地减小最小特征尺寸，半导体工业持续地改进各种电子部件(例如，晶体管、二极管、电阻器、电容器等)的集成度，这允许更多的部件集成到给定区域。在一些应用中，诸如集成电路管芯的这些较小的电子部件也可能需要比之前的封装件利用较小面积的较小的封装。
发明内容
根据本发明的一方面，提供了一种封装件，包括：芯片，包括衬底和位于衬底上的接触焊盘；模塑料，横向包封芯片；第一介电层，位于模塑料和芯片上面，并且具有暴露接触焊盘的第一开口；第一金属化层，位于第一介电层上面，其中，第一金属化层填充第一开口并且横向延伸在模塑料上方；第二介电层，位于第一金属化层和第一介电层上面，并且具有位于第一开口上方的第二开口；第二金属化层，位于第二介电层上面并且通过第二开口电连接至第一金属化层，并且横向延伸在模塑料上方。
优选地，第二金属化层形成在第二开口中并且与第一金属化层物理接触。
优选地，第二金属化层用作第二开口的侧壁和底部的衬垫。
优选地，第一金属化层包括第一晶种层和在第一晶种层上形成的第一导电层。
优选地，第一晶种层包括钛，而第一导电层包括铜。
优选地，第二金属化层包括第二晶种层和在第二晶种层上形成的第二导电层。
优选地，第二晶种层包括钛，而第二导电层包括铜。
优选地，该封装件还包括：位于第二金属化层上的凸块。
优选地，该封装件还包括：位于第二金属化层和第二介电层上面以及位于凸块的一部分周围的保护层。
优选地，芯片包括位于衬底上并且覆盖接触焊盘的一部分的钝化层，并且第一介电层形成在钝化层上面。
根据本发明的另一方面，提供了一种封装件，包括：芯片，包括衬底和位于衬底上的接触焊盘；模塑料，横向包封芯片；第一介电层，位于模塑料和芯片上面，并且具有暴露接触焊盘的第一开口；第一晶种层，位于第一介电层上面并且用作第一开口的侧壁和底部的衬垫；第一导电层，位于第一晶种层上面并且填充第一开口；第二介电层，位于第一导电层上面并且具有直接位于第一开口上方的第二开口；第二晶种层，位于第二介电层上面并且用作第二开口的侧壁和底部的衬垫；以及第二导电层，位于第二晶种层上面。
优选地，第二导电层沿着第二开口的侧壁和底部形成。
优选地，第一晶种层包括钛，而第一导电层包括铜。
优选地，第二晶种层包括钛，而第二导电层包括铜。
优选地，该封装件还包括：位于第二导电层上的凸块。
优选地，该封装件还包括：位于第二导电层和第二介电层上面以及位于凸块的一部分周围的保护层。
根据本发明的又一方面，提供了一种方法，包括：提供具有接触焊盘的芯片；形成横向包封芯片的模塑料，透过模塑料暴露接触焊盘；在模塑料和芯片上方形成第一介电层；在第一介电层中形成暴露接触焊盘的第一开口；第一导电层形成在第一介电层上面并且填充第一开口，其中，第一开口中的第一导电层具有平坦的表面；在第一导电层和第一介电层上方形成第二介电层；在第二介电层中形成位于第一开口上方的第二开口，从而露出第一导电层；以及在第二介电层上面形成第二导电层，并且第二导电层通过第二开口与第一导电层物理接触。
优选地，通过镀速大于1μm/min的镀铜工艺而形成第一导电层。
优选地，在第一开口形成的第一导电层具有宽度(W)和高度(H)，并且W/H的比率小于20。
优选地，在第一开口形成的第一导电层具有宽度(W)和高度(H)，并且W/H的比率大于2。
附图说明
为了更完全地理解本实施例及其优势，现结合附图参考以下描述，其中：
图1至图8是根据实施例的结构在制造工艺期间的各个截面图。
具体实施方式
下面将详细讨论本实施例的制造与使用。然而，应该理解，本发明提供了可以在各种具体上下文中实现的许多适用的发明构思。讨论的具体实施例仅是说明公开的主题的制造和使用的具体方式，而不限制不同实施例的范围。
将关于具体上下文描述实施例，即，扇出型封装件结构。然后，其他实施例也可以应用于其他封装件结构。下面的图和讨论示出了简化的结构以不使各个部件模糊，并且省略对本领域一般技术人员来说显而易见的多余的部件。图中的相同参考数字指的是相同的部件。虽然可以将方法实施例描述为以特定顺序进行实施，但是其他实施例可以以任何逻辑顺序进行实施。
图1至图8示出了根据实施例的结构在制造工艺期间的各个截面图。
图1示出了通过粘合膜202粘附至载体衬底200的两个芯片10。在实施例中，两芯片10形成为晶圆的一部分，然后分割该晶圆以形成单独的芯片10。例如，芯片10可以是逻辑集成电路、存储器管芯、模拟管芯或其他任何管芯。每个芯片10均包括衬底12、衬底12上的接触焊盘14以及上覆衬底12和接触焊盘14的钝化层16。衬底12可以包括诸如块状半导体衬底、绝缘体上半导体衬底等的半导体衬底，根据半导体工艺，在半导体衬底上形成电路，电路包括诸如晶体管的有源器件和/或诸如电容器、电感器等的无源器件。在半导体衬底中形成的电路可以是适于特定应用的任何类型的电路。例如，电路可以包括多个互连的以执行一种或多种功能的N型金属氧化物半导体(NMOS)和/或P型金属氧化物半导体(PMOS)器件，诸如，晶体管、电容器、电阻器、二极管、光电二极管、熔丝等。可以使用包括存储器结构、处理结构、传感器、放大器、功率分布、输入/输出电路等的各种结构来执行各功能。对于给定应用，可以视情况使用其他电路。介电层和金属线形成在电路上。例如，介电层可以通过任何合适的方法(诸如，旋压、化学汽相沉积(CVD)和/或等离子体增强CVD(PECVD))由低介电常数(低K)介电材料(诸如，磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟化硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物以及它们的组合等)形成。例如由铜、钨、铝和/或它们的合金形成的金属线形成在介电层中，并且将电路电连接在一起和/或将电路电连接至接触焊盘14。
接触焊盘14形成在衬底12的最上面的介电层上以电连接至下面的金属化层。在一些实施例中，接触焊盘14由铝、铝铜、铝合金、铜、铜合金等形成。钝化层16形成在衬底12的顶面上方，并且钝化层16被图案化以形成暴露接触焊盘14的至少一部分的开口16a。钝化层16可以是单层或层压的多层结构。在一些实施例中，钝化层16由介电材料(诸如，未掺杂的硅酸盐玻璃(USG)、氮化硅、氧化硅、氮氧化硅或无孔材料形成)。在一些实施例中，通过化学汽相沉积(CVD)、物理汽相沉积(PVD)或其他任何合适的工艺形成钝化层16。
在实施例中，使用例如取放工具将芯片10放置在载体衬底200上，并且通过诸如任何合适的粘合剂的粘合膜202(诸如，UV胶(当暴露于UV光时，UV胶失去其粘附特性)或线上膜(FOW)材料)将芯片10粘附至载体衬底200。载体衬底200可以是晶圆形式的衬底或面板形式的衬底。取决于芯片10的尺寸、载体衬底200的尺寸和具体应用，几十个芯片10或几百个芯片10或更多的芯片可以附接至载体衬底200。芯片10具有第一侧10F(本文中也称为前侧10F)和第二侧10B(本文中也称为后侧10B)。在一些实施例中，通过将芯片10放置在载体衬底200上的预定位置处，芯片10的后侧10B附接至粘合膜202，从而使得芯片10面朝上安装在载体衬底200上。
在图2中，模塑料18形成为至少横向包封芯片10。通过横向包封，意味着模塑料形成为在所有侧面上围绕芯片，但是不延伸在芯片的顶面上方。形成模塑料18以填充各芯片10之间的间隙。模塑料18可以使用压缩模塑、层压等形成。模塑料18可以是环氧基复合物等。例如，可以使用在约120℃和约340℃之间的温度下的恒温或斜坡升温热工艺来固化模塑料18。模塑料18在形成时可以初始覆盖芯片10(即，延伸在芯片10的顶面上方)，然后经过研磨工艺以暴露芯片10上方的牺牲层(未示出)。可以使用溶剂、化学物质等来去除牺牲层。在一实例中，对牺牲层具有选择性的湿蚀刻剂(诸如，例如约3％至约5％KOH的稀KOH溶液)用于去除牺牲层。在一些实施例中，芯片10的前侧10F未由模塑料18覆盖，从而使得暴露接触焊盘14和钝化层16。在实施例中，钝化层16的顶面低于模塑料18的顶面。在一些实施例中，钝化层16的顶面与模塑料18的顶面基本平齐。
参照图3，第一介电层30形成在芯片10的钝化层和接触焊盘14上方以及模塑料18上方。在一些实施例中，第一介电层30包括聚苯并恶唑(PBO)层、聚酰亚胺层、苯并环丁烯(BCB)层、环氧化物层、光敏材料层、其他合适的聚合物材料或它们的组合。第一介电层30可以通过旋涂工艺、层压工艺等或它们的组合来沉积。然后，通过光刻和/或蚀刻工艺来图案化第一介电层30以形成开口30a，下面的接触焊盘14通过开口30a暴露。在至少一些实施例中，开口30a定位在钝化层16的开口16a上方。在示出的实施例中，开口30a的尺寸(例如，直径)小于开口16a的尺寸。在其他预期的实施例中，开口30a的尺寸可以大于或等于开口16a的尺寸。
在图4中，第一金属化层32形成在第一介电层30上作为多条迹线，并且第一金属化层32填充开口30a以形成多个直接位于相应的接触焊盘14上方的第一通孔连接件34。在一些实施例中，第一通孔连接件34(当从“自顶向下”视图观察时)可以是环形、类环形、矩形、类正方形、三角形、六边形、八边形等。而且，第一通孔连接件34可以是封闭形、破碎的或断开的形状。在实施例中，第一金属化层32包括第一晶种层32a和第一导电层32b。例如，第一晶种层32a沉积在第一介电层30上方，作为第一介电层30的开口30a的底部和侧壁的衬垫。第一晶种层32a可以是通过原子层沉积(ALD)、溅射、另一物理汽相沉积(PVD)工艺等而沉积的铜、钛、钽、氮化钛、氮化钽、铜和钛的组合(Ti/Cu)等或它们的组合。导电层32b形成在第一晶种层32a上并且填充第一介电层30的开口30a。第一导电层32b可以是通过诸如化学镀、电镀等的镀工艺形成的铜、铜合金、铝、铝合金、钨、钨合金或它们的组合。在实施例中，通过改变添加剂选择和控制铜溶液的浓度来实施镀铜工艺，从而使得开口30a中的第一导电层32b的表面形成平坦的金属表面32s。例如，以大于约1μm/min的镀速来实施镀铜工艺。在开口30a中形成的第一导电层32b具有宽度W和高度H。例如，高于H小于10μm。高度H可以为约3μm。在实施例中，W/H的比率大于约2。在另一实施例中，W/H的比率小于约20。在又另一实施例中，W/H的比率在2和20之间。接下来，实施光刻和蚀刻工艺以图案化第一导电层32b和第一晶种层32a，从而形成期望的第一金属化层32的图案。第一金属化层32是钝化后互连(PPI)结构，其可以用作互连层、电源线、再分布线(RDL)、电感器、电容器或任何无源部件。
在图5中，第二介电层40形成在第一介电层30和第一金属化层32上方。在一些实施例中，第二介电层40包括聚苯并恶唑(PBO)层、聚酰亚胺层、苯并环丁烯(BCB)层、环氧化物层、光敏材料层、其他合适的聚合物材料或它们的组合。第二介电层40可以通过旋涂工艺、层压工艺等或它们的组合沉积。然后，通过光刻和/或蚀刻工艺来图案化第二介电层40以形成开口40a，下面的第一金属化层32的部分通过开口40a暴露。在至少一些实施例中，由于开口40a定位在第一介电层30的开口30a上方，所以通过开口40a暴露第一通孔连接件34。例如，开口40a的尺寸基本等于开口30a的尺寸。开口40a的尺寸可以大于或小于开口30a的尺寸。
接下来，如图6所示，第二金属化层42形成在第二介电层40上作为多条迹线或着陆台，并且第二金属化层42形成在开口40a中以形成多个直接位于相应的第一通孔连接件34上方的第二通孔连接件44。在一些实施例中，第二通孔连接件44可以是环形、类环形、矩形、类正方形、三角形、六边形、八边形等。而且，第二通孔连接件44可以是封闭形、破碎的或断开的形状。在实施例中，第二金属化层42包括第二晶种层42a和第二导电层42b。例如，第二晶种层42a沉积在第二介电层40上方，作为第二介电层40的开口40a的底部和侧壁的衬垫。第二晶种层42a可以是通过原子层沉积(ALD)、溅射、另一物理汽相沉积(PVD)工艺等而沉积的铜、钛、钽、氮化钛、氮化钽、铜和钛的组合(Ti/Cu)等或它们的组合。第二导电层42b形成在第二晶种层42a上。第二导电层42b也形成在第二介电层40的开口40a中。取决于开口尺寸和镀工艺控制，第二导电层42b可以部分地填充开口40a(如图6所示)或完全填充开口40a(未示出)。第二导电层42b可以是通过诸如化学镀、电镀等的镀工艺而形成的铜、铜合金、铝、铝合金、钨、钨合金或它们的组合。接下来，实施光刻和蚀刻工艺以图案化第二导电层42b和第二晶种层42a，从而显露出期望的第二金属化层42的图案。第二金属化层42包括电连接至第一通孔连接件34的第二通孔连接件44。第二金属化层42可以用作互连层、电源线、再分布线(RDL)、电感器、电容器或任何无源部件。虽然通孔连接件44示出为与通孔连接件34垂直对准，但是诸如通孔连接件44与通孔连接件34偏移的其他布置在本发明的预期范围内。
参照图7，凸块50形成在第二金属化层42上。在实施例中，凸块50是焊料凸块，例如，焊料凸块包括无铅焊料、SnAg或包括锡、铅、银、铜、镍、铋的合金的焊料材料或它们的组合。通过放置焊料球或镀焊料层，可以用回流工艺形成焊料凸块。在一些实施例中，凸块50是铜柱凸块、包括镍或金的金属凸块、或它们的组合。在实施例中，每个凸块50均具有大于约200μm的直径。然后，保护层52可选择地形成在第二金属化层42和第二介电层40上方以及凸块50的一部分周围。例如，凸块50的顶部50a暴露并且延伸在保护层52之上。在实施例中，保护层52是提供结构支撑的支撑材料，该材料为模塑料等。
接下来，如图8所示，载体衬底200与芯片10和模塑料18分离，然后将产生的结构锯成多个单独的封装件，也称为扇出型封装件。在实施例中，在覆盖芯片10的后侧10B和模塑料18的后侧的粘合膜202上提供胶带204。扇出型封装件包括一个或多于一个的芯片10和位于芯片10的前侧10F上方的两个金属化层32和42，其中，包括第二通孔连接件44和第一通孔连接件34的堆叠通孔结构54定位在芯片10的接触焊盘14上方并且电连接至芯片10的接触焊盘14。如图所示，第一通孔连接件34形成在第一介电层30的开口30a中。第一通孔连接件34包括作为开口30a的底部和侧壁的衬垫的第一晶种层32a和填充开口30a的第一导电层32b。根据实施例，第一通孔连接件34的顶面包括平坦的金属表面。第二通孔连接件44形成在第二介电层40的开口40a中。第二通孔连接件44包括作为开口40a的底部和侧壁的衬垫的第二晶种层42a和开口40a中的第二导电层42b。第二通孔连接件44形成在第一通孔连接件34上方，从而使得第二晶种层42a夹置在第一导电层32b和第二导电层42b之间。通过改变第一导电层32b的镀速以及形成第一导电层32b的W/H比率，在第一通孔连接件34上可以形成平坦的金属表面，并且可以最小化模塑料18和第一介电层30之间的厚度间隙，因此扩大第二介电层40的光刻窗口并实现细节距扇出型封装件。此外，使用一些实施例可以降低成本。
一个实施例是一种包括芯片和横向包封该芯片的模塑料的封装件，芯片具有衬底和位于衬底上的接触焊盘。第一介电层形成在模塑料和芯片上面，并且具有暴露接触焊盘的第一开口。第一金属化层形成在第一介电层上面，其中，第一金属化层填充第一开口。第二介电层形成在第一金属化层和第一介电层上面，并且具有位于第一开口上方的第二开口。第二金属化层形成在第二介电层上面并且形成在第二开口中。
另一实施例是包括芯片和横向包封该芯片的模塑料的封装件，芯片具有衬底和位于衬底上的接触焊盘。第一介电层形成在模塑料和芯片的上面，并且具有暴露接触焊盘的第一开口。第一晶种层形成在第一介电层上面并且用作第一开口的侧壁和底部的衬垫。第一导电层形成在第一晶种层上面并且填充第一开口。第二介电层形成在第一导电层上面并且具有直接位于第一开口上方的第二开口。第二晶种层形成在第二介电层上面并且用作第二开口的侧壁和底部的衬垫。第二导电层形成在第二晶种层上面。
又一实施例是一种方法，包括：提供具有接触焊盘的芯片；形成横向包封芯片的模塑料，透过模塑料暴露接触焊盘；在模塑料和芯片上方形成第一介电层；在第一介电层中形成暴露接触焊盘的第一开口；第一导电层形成在第一介电层上面并且填充第一开口，其中，第一开口中的第一导电层具有平坦的表面；在第一导电层和第一介电层上方形成第二介电层；在第二介电层中形成位于第一开口上方的第二开口从而露出第一导电层；以及在第二介电层上面形成第二导电层并且第二导电层通过第二开口与第一导电层物理接触。
虽然详细描述了本实施例及它们的优势，但应该理解，在不背离所附权利要求限定的本发明的精神和范围的情况下，在此可作出各种变化、替代和改变。此外，本申请的范围不旨在局限于说明书中所述的工艺、机器、制造、物质组成、工具、方法和步骤的特定实施例。根据本发明，作为本领域的一般技术人员将轻易地从本发明中理解，可以利用现有的或之后开发的执行与在此描述的相应实施例基本相同的功能或实现基本相同的结果的工艺、机器、制造、物质组成、工具、方法或步骤。因此，所附权利要求旨在将这样的工艺、机器、制造、物质组成、工具、方法或步骤包括在它们的范围内。

Claims (20)

1.一种封装件，包括：
芯片，包括衬底和位于所述衬底上的接触焊盘；
模塑料，横向包封所述芯片；
第一介电层，位于所述模塑料和所述芯片上面，并且具有暴露所述接触焊盘的第一开口；
第一金属化层，位于所述第一介电层上面，其中，所述第一金属化层填充所述第一开口以形成多个直接位于相应的接触焊盘上方的第一通孔连接件并且所述第一金属化层横向延伸在所述模塑料上方；
第二介电层，位于所述第一金属化层和所述第一介电层上面，并且具有位于所述第一开口上方的第二开口，所述第二开口暴露所述第一通孔连接件；
第二金属化层，位于所述第二介电层上面并且通过所述第二开口电连接至所述第一金属化层，并且横向延伸在所述模塑料上方。
2.根据权利要求1所述的封装件，其中，所述第二金属化层形成在所述第二开口中并且与所述第一金属化层物理接触。
3.根据权利要求1所述的封装件，其中，所述第二金属化层用作所述第二开口的侧壁和底部的衬垫。
4.根据权利要求1所述的封装件，其中，所述第一金属化层包括第一晶种层和在所述第一晶种层上形成的第一导电层。
5.根据权利要求4所述的封装件，其中，所述第一晶种层包括钛，而所述第一导电层包括铜。
6.根据权利要求1所述的封装件，其中，所述第二金属化层包括第二晶种层和在所述第二晶种层上形成的第二导电层。
7.根据权利要求6所述的封装件，其中，所述第二晶种层包括钛，而所述第二导电层包括铜。
8.根据权利要求1所述的封装件，还包括：位于所述第二金属化层上的凸块。
9.根据权利要求8所述的封装件，还包括：位于所述第二金属化层和所述第二介电层上面以及位于所述凸块的一部分周围的保护层。
10.根据权利要求1所述的封装件，其中，所述芯片包括位于所述衬底上并且覆盖所述接触焊盘的一部分的钝化层，并且所述第一介电层形成在所述钝化层上面。
11.一种封装件，包括：
芯片，包括衬底和位于所述衬底上的接触焊盘；
模塑料，横向包封所述芯片；
第一介电层，位于所述模塑料和所述芯片上面，并且具有暴露所述接触焊盘的第一开口；
第一晶种层，位于所述第一介电层上面并且用作所述第一开口的侧壁和底部的衬垫；
第一导电层，位于所述第一晶种层上面并且填充所述第一开口，其中，所述第一晶种层和所述第一导电层填充所述第一开口以形成多个直接位于相应的接触焊盘上方的第一通孔连接件；
第二介电层，位于所述第一导电层上面并且具有直接位于所述第一开口上方的第二开口，所述第二开口暴露所述第一通孔连接件；
第二晶种层，位于所述第二介电层上面并且用作所述第二开口的侧壁和底部的衬垫；以及
第二导电层，位于所述第二晶种层上面。
12.根据权利要求11所述的封装件，其中，所述第二导电层沿着所述第二开口的侧壁和底部形成。
13.根据权利要求11所述的封装件，其中，所述第一晶种层包括钛，而所述第一导电层包括铜。
14.根据权利要求11所述的封装件，其中，所述第二晶种层包括钛，而所述第二导电层包括铜。
15.根据权利要求11所述的封装件，还包括：位于所述第二导电层上的凸块。
16.根据权利要求15所述的封装件，还包括：位于所述第二导电层和所述第二介电层上面以及位于所述凸块的一部分周围的保护层。
17.一种形成封装件的方法，包括：
提供具有接触焊盘的芯片；
形成横向包封所述芯片的模塑料，透过所述模塑料暴露所述接触焊盘；
在所述模塑料和所述芯片上方形成第一介电层；
在所述第一介电层中形成暴露所述接触焊盘的第一开口；
第一导电层形成在所述第一介电层上面并且填充所述第一开口以形成多个直接位于相应的接触焊盘上方的第一通孔连接件，其中，所述第一开口中的第一导电层具有平坦的表面；
在所述第一导电层和所述第一介电层上方形成第二介电层；
在所述第二介电层中形成位于所述第一开口上方的第二开口，从而露出第一导电层的第一通孔连接件；以及
在所述第二介电层上面形成第二导电层，并且所述第二导电层通过所述第二开口与所述第一导电层物理接触。
18.根据权利要求17所述的方法，其中，通过镀速大于1μm/min的镀铜工艺而形成所述第一导电层。
19.根据权利要求17所述的方法，其中，在所述第一开口形成的所述第一导电层具有宽度(W)和高度(H)，并且W/H的比率小于20。
20.根据权利要求17所述的方法，其中，在所述第一开口形成的所述第一导电层具有宽度(W)和高度(H)，并且W/H的比率大于2。
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US9824989B2 (en) 2017-11-21
US20190355684A1 (en) 2019-11-21
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US10741511B2 (en) 2020-08-11
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