CN102856279A - 用于晶圆级封装的互连结构 - Google Patents

用于晶圆级封装的互连结构 Download PDF

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CN102856279A
CN102856279A CN2012100357594A CN201210035759A CN102856279A CN 102856279 A CN102856279 A CN 102856279A CN 2012100357594 A CN2012100357594 A CN 2012100357594A CN 201210035759 A CN201210035759 A CN 201210035759A CN 102856279 A CN102856279 A CN 102856279A
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layer
dielectric layer
face
metal pad
ppi
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CN102856279B (zh
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余振华
林俊成
刘乃玮
洪瑞斌
郑心圃
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

封装件包括具有衬底的器件管芯。模塑料接触该衬底的侧壁。金属焊盘位于该衬底上方。钝化层具有覆盖该金属焊盘的边部的部分。金属柱位于金属焊盘上方，并接触该金属焊盘。介电层位于钝化层上方。由模塑料或聚合物形成的封装材料位于该介电层上方。介电层包括在钝化层和封装材料之间的底部，和在金属柱的侧壁和封装材料的侧壁之间的侧壁部。聚合物层位于封装材料、模塑料和金属柱的上方。钝化后互连件(PPI)延伸至聚合物层内。焊球位于PPI上方，并通过PPI电连接至金属焊盘。本发明还提供用于晶圆级封装的互连结构。

Description

用于晶圆级封装的互连结构
技术领域
本发明涉及一种互连结构，具体地说涉及一种用于封装的互连结构。
背景技术
随着半导体技术的发展，半导体管芯变得越来越小。然而，需要将更多的功能集成在半导体管芯内。因此，半导体管芯需要将越来越多数量的I/O焊盘封装在较小的区域内，从而使I/O焊盘的密度迅速地升高。因此，半导体管芯的封装变得更困难，并对产量产生不利影响。
可以将封装技术分成两类。一类通常被称为晶圆级封装(WLP)，其中晶圆上的管芯在他们被切割之前进行封装。WLP技术具有一些有利的特征，诸如较大的生产量和较低的成本。而且，需要更少的底部填充或模塑料。然而，WLP技术也具有弊端。常规的WLP只能是扇入型封装，其中每个管芯的I/O焊盘被限定于各自管芯表面正上方的区域。管芯的面积有限，由于I/O焊盘的间距的限制，所以I/O焊盘的数量受到限制。如果要降低焊盘的间距，可能出现焊桥。此外，根据固定的球头尺寸(ball-size)要求，焊球必须具有一定的尺寸，这反过来限制能够在管芯的表面上聚集的焊球的数量。
在另一类封装中，管芯在其被封装在其他晶圆上之前从晶圆中切割下来，并且仅封装“已知良好的管芯”。这类封装技术的有利特征是可能形成扇出芯片封装，这意味着能够将管芯上的I/O焊盘重新分配到比管芯自身更大的区域中，并因此能够增加在管芯表面上聚集的I/O焊盘的数量。
扇出型WLP的形成面临挑战。例如，扇出型WLP的形成涉及其特性具有显著差异的各种材料。因此，需要改进这些材料界面处的粘附强度。需要改进扇出型WLP的防潮隔离。而且，还需要控制扇出型WLP中所涉及的材料之间的相互扩散和逸气。
发明内容
为了解决现有技术中存在的问题，根据本发明的一个方面，提供了一种封装件，包括：器件管芯，包括衬底；模塑料，接触所述衬底的侧壁；金属焊盘，位于所述衬底上方；钝化层，包括覆盖所述金属焊盘的边部的部分；金属柱，位于所述金属焊盘上方，并被电连接至所述金属焊盘；介电层，位于所述钝化层上方；封装材料，在所述介电层上方由其他模塑料或聚合物形成，其中所述介电层包括底部和侧壁部，所述底部位于所述钝化层和所述封装材料之间，所述侧壁部位于所述金属柱的侧壁和所述封装材料的侧壁之间，并接触所述金属柱的侧壁和所述封装材料的侧壁；聚合物层，位于所述封装材料、所述模塑料和所述金属柱上方；钝化后互连件(PPI)，延伸至所述聚合物层中的开口内并被电连接至所述金属柱，其中所述PPI进一步包括位于所述聚合物层正上方的部分；和焊球，位于所述PPI上方，并被电连接至所述PPI。
在该封装件中，其中所述介电层的底部的厚度接近所述介电层的侧壁部的厚度。
在该封装件中，其中所述封装材料包括聚酰亚胺。
在该封装件中，其中所述封装材料的顶面、所述介电层的顶边和所述金属柱的顶面彼此齐平。
在该封装件中，其中所述封装材料的顶面、所述介电层的顶边和所述金属柱的顶面彼此齐平，其中所述模塑料的顶面进一步与所述封装材料的顶面、所述介电层的顶边和所述金属柱的顶面齐平。
在该封装件中，其中所述介电层包含选自基本上由下列材料组成的组中的材料：氮化硅、碳化硅、氮碳化硅、碳氧化硅、四乙基原硅酸盐(TEOS)氧化物、氧化硅及其组合。
根据本发明的另一方面，还提供了一种封装件，包括：器件管芯，包括衬底；模塑料，接触所述衬底的侧壁；金属焊盘，位于所述衬底的上方；钝化层，包括覆盖所述金属焊盘的边部的部分；介电层，位于所述钝化层上方，其中所述介电层包括延伸至所述钝化层中的开口内的部分，所述介电层的所述部分包括接触所述金属焊盘的顶面的底面；第一聚合物层，位于所述介电层上方，其中所述第一聚合物层没有延伸至所述模塑料的正上方；第二聚合物层，位于所述第一聚合物层和所述模塑料上方，并垂直叠盖所述第一聚合物层和所述模塑料；钝化后互连件(PPI)，包括延伸至开口内的通孔，所述开口延伸至所述第一聚合物层和所述第二聚合物层内，其中所述通孔接触所述金属焊盘的顶面，并且其中所述介电层的边接触所述通孔的侧壁；和焊球，位于所述PPI和所述第二聚合物层的上方，其中所述焊球通过所述PPI被电连接至所述金属焊盘。
在该封装件中，其中所述第一聚合物层包括接触所述模塑料侧壁的侧壁，其中所述介电层包括接触所述模塑料侧壁的边，并且其中所述模塑料的顶面与所述第一聚合物层的顶面齐平。
在该封装件中，进一步包括介电硬掩模层，所述介电硬掩模层位于所述第二聚合物层上方和所述PPI的一部分的下方。
在该封装件中，进一步包括介电硬掩模层，所述介电硬掩模层位于所述第二聚合物层上方和所述PPI的一部分的下方，且其中所述介电硬掩模层包含氮化硅。
在该封装件中，其中所述模塑料包括顶面，所述顶面接触所述第二聚合物层的底面。
在该封装件中，其中所述介电层包含选自基本上由下列材料组成的组中的材料：氮化硅、碳化硅、氮碳化硅、碳氧化硅、四乙酸原硅酸盐(TEOS)氧化物、氧化硅、及其组合。
根据本发明的又一方面，还提供了一种方法，包括：提供器件晶圆，所述器件晶圆包括：器件管芯，包括衬底；金属焊盘，位于所述衬底上方；和钝化层，包括覆盖所述金属焊盘的边部的部分，其中所述金属焊盘的顶面的一部分没有被所述钝化层覆盖；该方法还包括在所述器件晶圆上方形成介电层，其中所述整个器件晶圆被所述介电层覆盖以及对所述器件晶圆实施管芯切割，从而在所述器件晶圆中使所述器件管芯与其他管芯分开，其中在覆盖形成所述介电层的步骤和管芯切割的步骤之间没有对所述介电层实施图案化，并且其中所述器件管芯包括所述介电层。
该方法进一步包括：将所述管芯接合在载具上；涂覆模塑料以接触所述衬底的边，其中所述模塑料包括位于所述管芯正上方的部分；实施研磨以移除所述模塑料的顶部；在所述管芯和所述模塑料上方形成第一聚酰亚胺层；形成钝化后互连件(PPI)，所述钝化后互连件包括位于所述第一聚酰亚胺层上方的第一部分和延伸至所述第一聚酰亚胺层中的第一开口内的第二部分；以及在所述PPI的第一部分上方形成焊球，其中所述焊球通过所述PPI被电连接至所述金属焊盘。
该方法进一步包括：将所述管芯接合在载具上；涂覆模塑料以接触所述衬底的边，其中所述模塑料包括位于所述管芯正上方的部分；实施研磨以移除所述模塑料的顶部；在所述管芯和所述模塑料上方形成第一聚酰亚胺层；形成钝化后互连件(PPI)，所述钝化后互连件包括位于所述第一聚酰亚胺层上方的第一部分和延伸至所述第一聚酰亚胺层中的第一开口内的第二部分；以及在所述PPI的第一部分上方形成焊球，其中所述焊球通过所述PPI被电连接至所述金属焊盘，且其中所述器件管芯包括位于金属焊盘上方并电连接金属焊盘的金属柱，其中所述介电层包括位于所述金属柱正上方的部分，以及其中在执行所述研磨步骤后，将所述介电层位于所述金属柱正上方的部分去除，从而将所述金属柱的顶面暴露出来。
在该方法中，其中当通过所述管芯切割步骤切割所述器件晶圆时，所述介电层暴露于空气中。
在该方法中，进一步包括，在执行所述管芯切割的步骤之前，在所述介电层上方形成第二聚酰亚胺层，其中当通过所述管芯切割步骤切割所述器件晶圆时，所述第二聚酰亚胺层暴露于空气中。
在该方法中，进一步包括，在执行所述管芯切割的步骤之前，在所述介电层上方形成第二聚酰亚胺层，其中当通过所述管芯切割步骤切割所述器件晶圆时，所述第二聚酰亚胺层暴露于空气中，且其中所述器件管芯进一步包括位于所述金属焊盘上方且被电连接至所述金属焊盘的金属柱，其中所述金属柱延伸至所述钝化层中的开口内，并且其中所述介电层和所述第二聚酰亚胺层延伸至所述金属柱上方。
在该方法中，进一步包括，在执行所述管芯切割的步骤之前，在所述介电层上方形成第二聚酰亚胺层，其中当通过所述管芯切割步骤切割所述器件晶圆时，所述第二聚酰亚胺层暴露于空气中，且其中所述器件管芯进一步包括位于所述金属焊盘上方且被电连接至所述金属焊盘的金属柱，其中所述金属柱延伸至所述钝化层中的开口内，并且其中所述介电层和所述第二聚酰亚胺层延伸至所述金属柱上方，而且该方法进一步包括，实施研磨以移除所述介电层的和所述第二聚酰亚胺层的位于所述金属柱正上方的部分，直到将所述金属柱的顶面暴露出来。
在该方法中，其中所述介电层包括接触所述金属焊盘的顶面的中心部分的底面，以及其中所述方法进一步包括，在实施所述管芯切割步骤之前，在所述介电层上方形成第二聚酰亚胺层。
附图说明
为了更充分地理解实施例及其优点，现在将结合附图所进行的以下描述作为参考，其中：
图1至图6是根据实施例的制造扇出型晶圆级封装件(WLP)的中间阶段的横截面视图，其中在器件晶圆被切割之前在器件晶圆中的金属焊盘上方形成介电层，并且其中使用先通孔(via-first)方法封装从器件晶圆中切割的管芯；
图7至图12是根据可选实施例的在制造扇出型晶圆级封装件(WLP)中的中间阶段的横截面视图，其中在器件晶圆被切割之前在器件晶圆的金属焊盘上方形成介电层和聚酰亚胺层，并且其中使用先通孔方法封装从器件晶圆中切割的管芯；和
图13至图19是根据可选实施例的在制造扇出型晶圆级封装件(WLP)中的中间阶段的横截面视图，其中在器件晶圆被切割之前在器件晶圆的金属焊盘上方形成介电层和聚酰亚胺层，并且其中使用后通孔方法(via-last)封装从器件晶圆中切割的管芯。
具体实施方式
在下面详细地讨论本公开的实施例的制造和应用。然而，应该理解，实施例提供了许多可以在各种具体环境中实现的可应用的发明概念。所讨论的具体实施例仅仅是示例性的，而不用于限制本公开的范围。
提供扇出型晶圆级封装(WLP)结构和形成该扇出型晶圆级封装结构的方法。根据各个实施例举例说明了制造WLP结构的中间阶段。在本发明全文的各个视图和示例性实施例中，相同的附图编号用于指示相同的元件。
参考图1，提供器件晶圆100。晶圆100包括衬底20，该衬底20可以是半导体衬底，诸如硅衬底，但是该衬底20也可以由诸如硅锗、硅碳、砷化镓等其他半导体材料形成。可以在衬底20的表面形成有源器件(未显示)，诸如晶体管。在衬底20上方形成互连结构22，其包括在其中形成的且电连接至半导体器件的金属线和通孔(未显示)。金属线和通孔可以由铜或铜合金形成，并可以采用镶嵌工艺形成。互连结构22可以包括层间电介质(ILD)和金属间电介质(IMD)。
在互连结构22上方形成金属焊盘28。金属焊盘28可以包含铝(Al)、铜(Cu)、银(Ag)、金(Au)、镍(Ni)、钨(W)、其合金、和/或其多层。在示例性实施例中，金属焊盘28由铝合金形成。可以将金属焊盘28例如通过下面的互连结构22电连接至半导体器件。可以形成钝化层30以覆盖金属焊盘28的边部。在示例性实施例中，钝化层30由氧化硅层和位于该氧化硅层上方的氮化硅层形成，但是也可以使用诸如未掺杂硅酸盐玻璃(USG)、氧氮化硅等其他介电材料。
在金属焊盘28上方形成金属柱34，并可以使其物理接触金属焊盘28。金属柱34延伸至钝化层30中的开口内，并且金属柱34的边可以接触钝化层30的边。在实施例中，金属柱34包含铜或铜合金，但是也可以使用其他金属或金属合金。金属柱34的顶面可以高于钝化层30的顶面，从而使金属柱34相对于钝化层30突出出来。
在钝化层30和金属柱34上方形成介电层32。介电层32可以具有接触钝化层30的顶面、金属柱34的顶面和金属柱34的侧壁的底面。介电层32的材料包括但不限于氮化硅、碳化硅、碳氮化硅、碳氧化硅、四乙基原硅酸盐(TEOS)氧化物、氧化硅、其多层、和/或其组合。介电层32的厚度可以小于约1μm，可以在例如约0.1μm和约1μm之间，但是也可以使用不同的厚度。介电层32可以是基本上共形的，例如，介电层32的垂直部分的厚度T1接近于水平部分的厚度T2。例如，厚度T1可以是在厚度T2的约70％和约100％之间。形成介电层32之后，并且在不对介电层32实施图案化的情况下，可以沿着切割道38切割器件晶圆100，并因此将器件管芯40与晶圆100分开。在实施管芯切割时，介电层32可能是覆盖整个晶圆100的最顶层，并可以暴露于空气中。因此，介电层32可以阻止湿气氧化和退化金属柱34。
接下来，如图2中所示，例如通过粘合剂44，在载具42上接合管芯40。参考图3，涂覆模塑料46填充管芯40之间的间隙，并覆盖管芯40。在实施例中，模塑料46接触衬底20的侧壁、介电层32的顶面和侧边以及钝化层30的侧边。模塑料46的顶面可以高于介电层32的顶面。然后固化模塑料46。
接下来，如图4中所示，实施研磨，直到将金属柱34的顶面暴露出来。因此，将介电层32和模塑料46的位于金属柱34的顶面上方的部分移除。作为研磨的结果，介电层32的顶边32A与模塑料46的顶面46A齐平，并且与金属柱34的顶面34A齐平。图5示出了聚合物层49和后钝化互连件(PPI)50的形成。聚合物层49可以是聚酰亚胺层，并因此在整个说明书中被称为聚酰亚胺层49。聚酰亚胺层49可以由感光材料形成，对该感光材料可以很容易地进行图案化以形成开口，通过该开口将下面的金属柱34暴露出来。在示例性实施例中，聚酰亚胺层49由低温聚苯并恶唑(PBO)形成。然后在聚酰亚胺层49上方形成掩模层48。掩模层48可以由光刻胶形成，并因此在整个说明书中可选地被称为光刻胶48，但是也可以使用其他材料。接着，实施电镀步骤以在光刻胶48的开口中形成PPI50。PPI50可以由铜或铜合金形成，并可以包括PPI线和PPI焊盘。PPI50可以延伸至聚酰亚胺层49的开口内，从而电连接至金属柱34。PPI50也可以与金属柱34相接触。
图6示出了聚合物层54(其可以是聚酰亚胺层)、底部凸块金属层(UBM)56和焊球60的形成。在实施例中，首先涂覆和图案化聚酰亚胺层54，从而将PPI50中的PPI焊盘通过聚酰亚胺层54中的开口暴露出来。然后可以形成UBM56。将焊球60置于UBM56上，并回流。从而形成扇出型晶圆200。晶圆200包括多个管芯40和各自的扇出互连件。晶圆200可以从载具42上卸下，并例如沿着切割道62，切割成多个管芯。在得到的扇出型WLP中，介电层32在金属柱34的侧壁上形成并使金属柱34与模塑料46隔离。这可能有助于减少铜扩散至模塑料46内，并降低模塑料46的逸气以免退化金属柱34。介电层32的侧边可以与模塑料46的侧壁70相接触。
图7至图12示出了根据可选实施例的制造扇出型WLP的中间阶段的横截面视图。除非另有规定，在下面提供的可选实施例中的参考数字表示与图1至图6中所示出的实施例中相同的元件。该实施例的初始步骤基本上与如图1中所示的相同，除了在将晶圆100切割成管芯40之前，在介电层32上方形成聚合物层(其可以是聚酰亚胺层)66。在实施例中，聚酰亚胺层66由高温PBO形成，但是也可以使用其他聚酰亚胺材料。在切割器件晶圆100时，聚酰亚胺层66可以是均厚(blanket)覆盖整个器件晶圆100的最顶层。在切割器件晶圆100时，聚酰亚胺层66可以暴露于空气中。在将晶圆100切割成管芯40后，每个管芯40包括介电层32和位于介电层32上方的聚酰亚胺层66。再次，在一些实施例中，在管芯切割之前对聚酰亚胺层66和介电层32未实施图案化。
接下来，如图8中所示，将管芯40置于载具42上方，并且例如通过粘合剂44，粘附于载具42。然后用模塑料46填充管芯44之间的间隙，并进一步将其涂覆在聚酰亚胺层66上方，如图9中所示。参考图10，模塑料46固化后，实施研磨以移除模塑料46的顶部，直至将金属柱34暴露出来。因此，介电层32的顶边32A与模塑料46的顶面46A、金属柱34的顶面34A和聚酰亚胺层66的顶面66A齐平。在随后的工艺步骤中，如图11和图12所示，形成聚合物层49、PPI50、UBM56、聚合物层54和焊球60。形成步骤可能与图5和图6中所示的基本上相同。得到的结构在图12中示出。从而完成扇出型晶圆200的形成。然后将晶圆200从载具42上卸下。可以实施管芯切割以将晶圆200沿着切割道62切割成管芯。
在得到的如图12中所示的扇出型WLP中，介电层32在金属柱34的侧壁上形成并使金属柱34与聚酰亚胺层66隔离。这可能有助于减少铜在金属柱34和聚酰亚胺层66之间的相互扩散和逸气。图12中所示的结构与图6中的结构的不同之处在于聚酰亚胺层66，而不是模塑料46(这两者都被称为封装材料)位于介电层32的正上方和聚酰亚胺层49的正下方。而且，聚酰亚胺层66位于金属柱34之间，并通过介电层32的位于金属柱34侧壁上的部分与金属柱34间隔开。聚酰亚胺层66的侧边、钝化层30的侧边和介电层32的侧边可以是垂直对齐的，并与模塑料46的侧壁70相接触。
采用先通孔方法实施图1至图12中所示的实施例，其中在管芯切割工艺之前形成金属柱34(其充当通孔，图1和图7)。图13至图19示出采用后通孔方法的可选实施例。参考图13，形成晶圆100。如图13中所示的结构除了不形成金属柱34以外，与图7中所示的结构相似。因此在钝化层30和金属焊盘28上方形成介电层32。介电层32的底面可以接触钝化层30和金属焊盘28的顶面。而且，介电层32可以延伸至钝化层30中的开口内，从而接触金属焊盘28。然后在介电层32上方形成聚合物层(其可以是聚酰亚胺层)66。在实施例中，聚酰亚胺层66接触介电层32。再次，与图1中的介电层32相似，图13中的介电层32可以是共形层。介电层32与金属焊盘28具有比聚酰亚胺层66更好的粘合性，并因此可以改进聚酰亚胺层66和金属焊盘28之间的粘合性。将晶圆100沿着切割道38切割成管芯40。
参考图14，将管芯40接合至载具42。接下来，如图15中所示，在管芯40之间的间隙内和在管芯40上方涂覆模塑料46。而且，可以在聚酰亚胺层66上方涂覆模塑料46。图16示出了模塑料46的研磨。研磨后，将聚酰亚胺层66暴露出来，并且聚酰亚胺层66的顶面与模塑料46的顶面齐平。参考图17，在聚酰亚胺层66和模塑料46上方形成聚酰亚胺层49，接着形成硬掩模层68。在实施例中，硬掩模层68由氮化硅形成，但是也可以使用诸如碳化硅、氮氧化硅等其他介电材料。对硬掩模层68进行图案化(例如，通过采用光刻胶(未显示))。然后采用经过图案化的硬掩模层68图案化聚酰亚胺层49和66，以形成开口71。在形成开口71的过程中，可以使用介电层32作为蚀刻停止层(ESL)。然后蚀刻介电层32的暴露部分，从而将金属焊盘28暴露出来。
在随后的工艺步骤中，如图18和图19中所示，形成PPI50、聚酰亚胺层54、UBM56和焊球60。形成步骤可以与图5和图6中所示的基本上相同。PPI50包括通孔51，通孔51接触金属焊盘28的顶面。得到的结构在图19中显示。从而完成了扇出型晶圆200的形成。然后可以将晶圆200从载具42上卸下。可以实施管芯切割，沿着切割道62将晶圆200切割成管芯。
在得到的如图19中所示的扇出型WLP中，介电层32包括延伸至金属焊盘28的顶面正上方且与金属焊盘28的顶面相接触的部分。位于金属焊盘28正上方的介电层32的部分具有可以接触PPI50的通孔51的边。在聚酰亚胺层49和介电层32之间形成聚酰亚胺层66。聚酰亚胺层66的侧边、钝化层30的侧边和介电层32的侧边可以是垂直对齐的，并与模塑料46的侧壁70相接触。
在实施例中，在器件晶圆的切割之前形成的介电层可以有助于减少铜的扩散，减少逸气的不良影响，并改进粘合性。
根据实施例，封装件包括具有衬底的器件管芯。模塑料接触该衬底的侧壁。金属焊盘位于该衬底上方。钝化层具有覆盖该金属焊盘边部的部分。金属柱位于该金属焊盘上方并接触该金属焊盘。介电层位于钝化层上方。由模塑料或聚合物形成的封装材料位于该介电层上方。该介电层包括钝化层和封装材料之间的底部和金属柱的侧壁和封装材料的侧壁之间的侧壁部。聚合物层位于封装材料、模塑料和金属柱的上方。PPI延伸至聚合物层内。焊球位于该PPI上方，并通过该PPI被电连接至金属焊盘。
根据其他实施例，封装件包括器件管芯，该器件管芯包括衬底；和模塑化合物，该模塑化合物接触该衬底的侧壁。金属焊盘位于该衬底上方。钝化层具有覆盖该金属焊盘边部的部分。介电层位于该钝化层上方，其中该介电层包括延伸至钝化层中的开口内的部分。该介电层的部分具有接触该金属焊盘的顶面的底面。第一聚合物层位于介电层上方，其中该第一聚合物层没有延伸至模塑料的正上方。第二聚合物层位于第一聚合物层上方，并垂直叠盖第一聚合物层和模塑料。PPI包括延伸至开口内的通孔，该开口延伸至第一聚合物层和第二聚合物层内，其中该通孔接触金属焊盘的顶面，并且其中介电层的边接触该通孔的侧壁。焊球位于PPI和第二聚合物层的上方，其中该焊球通过PPI被电连接至金属焊盘。
根据又一些实施例，方法包括提供器件晶圆，其中该器件晶圆包括具有衬底的器件管芯、位于该衬底上方的金属焊盘和具有覆盖该金属焊盘边部的部分的钝化层，其中该金属焊盘的顶面的中心部分没有被钝化层覆盖。在器件晶圆上方均厚形成介电层，其中该介电层基本上是共形的，并且其中整个该器件晶圆被介电层覆盖。对器件晶圆实施管芯切割以将器件管芯与晶圆中的其他管芯分开，其中在均厚形成介电层的步骤和管芯切割的步骤之间对该介电层未实施图案化。器件管芯包括该介电层。
尽管已经详细地描述了实施例及其优点，但应当理解，在本文中可以进行多种改变、替换和更改，而不脱离如附随的权利要求限定的实施例的主旨和范围。而且，本申请的范围并不是意在限制本说明书中所述的工艺、机器、制造、材料组分、装置、方法和步骤的具体实施例。因为本领域普通技术人员将从本公开中很容易地理解，根据本公开可以利用现在已存的或今后开发的工艺、机器、制造、材料组分、装置、方法或步骤，实施与本文中所述的相应实施例基本上相同的功能或实现基本上相同的结果。因此，附随的权利要求的意图是在他们的范围内包括这些工艺、机器、制造、材料组分、装置、方法或步骤。此外，每个权利要求构成单独的实施例，并且多个权利要求和实施例的组合也在本公开的范围内。

Claims (10)

1.一种封装件，包括：
器件管芯，包括衬底；
模塑料，接触所述衬底的侧壁；
金属焊盘，位于所述衬底上方；
钝化层，包括覆盖所述金属焊盘的边部的部分；
金属柱，位于所述金属焊盘上方，并被电连接至所述金属焊盘；
介电层，位于所述钝化层上方；
封装材料，在所述介电层上方由其他模塑料或聚合物形成，其中所述介电层包括底部和侧壁部，所述底部位于所述钝化层和所述封装材料之间，所述侧壁部位于所述金属柱的侧壁和所述封装材料的侧壁之间，并接触所述金属柱的侧壁和所述封装材料的侧壁；
聚合物层，位于所述封装材料、所述模塑料和所述金属柱上方；
钝化后互连件(PPI)，延伸至所述聚合物层中的开口内并被电连接至所述金属柱，其中所述PPI进一步包括位于所述聚合物层正上方的部分；和
焊球，位于所述PPI上方，并被电连接至所述PPI。
2.根据权利要求1所述的封装件，其中所述介电层的底部的厚度接近所述介电层的侧壁部的厚度；或者其中所述封装材料包括聚酰亚胺；或者其中所述封装材料的顶面、所述介电层的顶边和所述金属柱的顶面彼此齐平；或者
其中所述封装材料的顶面、所述介电层的顶边和所述金属柱的顶面彼此齐平，且其中所述模塑料的顶面进一步与所述封装材料的顶面、所述介电层的顶边和所述金属柱的顶面齐平；或者其中所述介电层包含选自基本上由下列材料组成的组中的材料：氮化硅、碳化硅、氮碳化硅、碳氧化硅、四乙基原硅酸盐(TEOS)氧化物、氧化硅及其组合。
3.一种封装件，包括：
器件管芯，包括衬底；
模塑料，接触所述衬底的侧壁；
金属焊盘，位于所述衬底的上方；
钝化层，包括覆盖所述金属焊盘的边部的部分；
介电层，位于所述钝化层上方，其中所述介电层包括延伸至所述钝化层中的开口内的部分，所述介电层的所述部分包括接触所述金属焊盘的顶面的底面；
第一聚合物层，位于所述介电层上方，其中所述第一聚合物层没有延伸至所述模塑料的正上方；
第二聚合物层，位于所述第一聚合物层和所述模塑料上方，并垂直叠盖所述第一聚合物层和所述模塑料；
钝化后互连件(PPI)，包括延伸至开口内的通孔，所述开口延伸至所述第一聚合物层和所述第二聚合物层内，其中所述通孔接触所述金属焊盘的顶面，并且其中所述介电层的边接触所述通孔的侧壁；和
焊球，位于所述PPI和所述第二聚合物层的上方，其中所述焊球通过所述PPI被电连接至所述金属焊盘。
4.根据权利要求3所述的封装件，其中所述第一聚合物层包括接触所述模塑料侧壁的侧壁，其中所述介电层包括接触所述模塑料侧壁的边，并且其中所述模塑料的顶面与所述第一聚合物层的顶面齐平；或者
所述封装件进一步包括介电硬掩模层，所述介电硬掩模层位于所述第二聚合物层上方和所述PPI的一部分的下方；或者
所述封装件进一步包括介电硬掩模层，所述介电硬掩模层位于所述第二聚合物层上方和所述PPI的一部分的下方，且其中所述介电硬掩模层包含氮化硅；或者
其中所述模塑料包括顶面，所述顶面接触所述第二聚合物层的底面；或者
其中所述介电层包含选自基本上由下列材料组成的组中的材料：氮化硅、碳化硅、氮碳化硅、碳氧化硅、四乙酸原硅酸盐(TEOS)氧化物、氧化硅、及其组合。
5.一种方法，包括：
提供器件晶圆，所述器件晶圆包括：
器件管芯，包括衬底；
金属焊盘，位于所述衬底上方；和
钝化层，包括覆盖所述金属焊盘的边部的部分，其中所述金属焊盘的顶面的一部分没有被所述钝化层覆盖；
在所述器件晶圆上方形成介电层，其中所述整个器件晶圆被所述介电层覆盖；以及
对所述器件晶圆实施管芯切割，从而在所述器件晶圆中使所述器件管芯与其他管芯分开，其中在覆盖形成所述介电层的步骤和管芯切割的步骤之间没有对所述介电层实施图案化，并且其中所述器件管芯包括所述介电层。
6.根据权利要求5所述的方法，进一步包括：
将所述管芯接合在载具上；
涂覆模塑料以接触所述衬底的边，其中所述模塑料包括位于所述管芯正上方的部分；
实施研磨以移除所述模塑料的顶部；
在所述管芯和所述模塑料上方形成第一聚酰亚胺层；
形成钝化后互连件(PPI)，所述钝化后互连件包括位于所述第一聚酰亚胺层上方的第一部分和延伸至所述第一聚酰亚胺层中的第一开口内的第二部分；以及
在所述PPI的第一部分上方形成焊球，其中所述焊球通过所述PPI被电连接至所述金属焊盘。
7.根据权利要求6所述的方法，其中所述器件管芯包括位于金属焊盘上方并电连接金属焊盘的金属柱，其中所述介电层包括位于所述金属柱正上方的部分，以及其中在执行所述研磨步骤后，将所述介电层位于所述金属柱正上方的部分去除，从而将所述金属柱的顶面暴露出来。
8.根据权利要求5所述的方法，其中当通过所述管芯切割步骤切割所述器件晶圆时，所述介电层暴露于空气中；或者
其中所述介电层包括接触所述金属焊盘的顶面的中心部分的底面，以及其中所述方法进一步包括，在实施所述管芯切割步骤之前，在所述介电层上方形成第二聚酰亚胺层。
9.根据权利要求5所述的方法，进一步包括，在执行所述管芯切割的步骤之前，在所述介电层上方形成第二聚酰亚胺层，其中当通过所述管芯切割步骤切割所述器件晶圆时，所述第二聚酰亚胺层暴露于空气中。
10.根据权利要求9所述的方法，其中所述器件管芯进一步包括位于所述金属焊盘上方且被电连接至所述金属焊盘的金属柱，其中所述金属柱延伸至所述钝化层中的开口内，并且其中所述介电层和所述第二聚酰亚胺层延伸至所述金属柱上方，且所述方法进一步包括，实施研磨以移除所述介电层的和所述第二聚酰亚胺层的位于所述金属柱正上方的部分，直到将所述金属柱的顶面暴露出来。
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Cited By (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681371A (zh) * 2013-12-26 2014-03-26 江阴长电先进封装有限公司 一种硅基圆片级扇出封装方法及其封装结构
CN104576424A (zh) * 2014-12-10 2015-04-29 华进半导体封装先导技术研发中心有限公司 通过预先在芯片上制备凸点实现扇出型晶圆封装的方法
CN104617050A (zh) * 2014-12-11 2015-05-13 南通富士通微电子股份有限公司 晶圆级封装方法
CN104795371A (zh) * 2014-01-17 2015-07-22 台湾积体电路制造股份有限公司 扇出型封装件及其形成方法
CN105097566A (zh) * 2015-07-01 2015-11-25 华进半导体封装先导技术研发中心有限公司 一种晶圆级扇出封装的制作方法
CN105990291A (zh) * 2015-03-16 2016-10-05 台湾积体电路制造股份有限公司 用于管芯探测的结构
CN106571343A (zh) * 2016-11-18 2017-04-19 三星半导体(中国)研究开发有限公司 集成被动元件的晶圆级扇出型封装件及其制造方法
CN107068574A (zh) * 2015-10-20 2017-08-18 台湾积体电路制造股份有限公司 半导体器件和方法
CN107346761A (zh) * 2016-05-05 2017-11-14 台湾积体电路制造股份有限公司 封装体及其形成方法
CN107833837A (zh) * 2016-09-16 2018-03-23 台湾积体电路制造股份有限公司 具有反向轮廓的铜柱的信息结构
CN108231535A (zh) * 2016-12-14 2018-06-29 台湾积体电路制造股份有限公司 具有钝化层的半导体装置的制造方法
CN110379767A (zh) * 2019-07-16 2019-10-25 中芯集成电路（宁波）有限公司 晶圆级封装芯片通孔互连的方法以及芯片的测试方法
CN110504174A (zh) * 2019-07-25 2019-11-26 南通通富微电子有限公司 封装结构的形成方法
CN110517959A (zh) * 2019-07-25 2019-11-29 南通通富微电子有限公司 封装结构的形成方法
CN110534441A (zh) * 2019-07-25 2019-12-03 南通通富微电子有限公司 封装结构及其形成方法
CN110534483A (zh) * 2019-07-25 2019-12-03 南通通富微电子有限公司 封装结构
CN110534484A (zh) * 2019-07-25 2019-12-03 南通通富微电子有限公司 封装结构
CN110534440A (zh) * 2019-07-25 2019-12-03 南通通富微电子有限公司 封装结构及其形成方法
CN111883521A (zh) * 2020-07-13 2020-11-03 矽磐微电子(重庆)有限公司 多芯片3d封装结构及其制作方法
WO2021013097A1 (en) * 2019-07-25 2021-01-28 Nantong Tongfu Microelectronics Co., Ltd. Packaging structure and formation method thereof
WO2021181181A1 (en) * 2020-03-10 2021-09-16 International Business Machines Corporation High bandwidth module
US12094728B2 (en) 2015-10-20 2024-09-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device

Families Citing this family (272)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9385095B2 (en) 2010-02-26 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US8832283B1 (en) 2010-09-16 2014-09-09 Google Inc. Content provided DNS resolution validation and use
TWI575684B (zh) * 2011-06-13 2017-03-21 矽品精密工業股份有限公司 晶片尺寸封裝件
US8586408B2 (en) * 2011-11-08 2013-11-19 Taiwan Semiconductor Manufacturing Company, Ltd. Contact and method of formation
US9000584B2 (en) * 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US9691706B2 (en) 2012-01-23 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip fan out package and methods of forming the same
US20130341780A1 (en) * 2012-06-20 2013-12-26 Infineon Technologies Ag Chip arrangements and a method for forming a chip arrangement
US9099420B2 (en) * 2012-11-30 2015-08-04 Taiwan Semiconductor Manufacturing Company, Ltd. Test structures for post-passivation interconnect
US8816500B2 (en) * 2012-12-14 2014-08-26 Infineon Technologies Ag Semiconductor device having peripheral polymer structures
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9368460B2 (en) * 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9583424B2 (en) 2013-05-23 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure and method for reducing polymer layer delamination
US9466581B2 (en) 2013-10-18 2016-10-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device and manufacturing method thereof
US9299688B2 (en) * 2013-12-10 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and methods of packaging semiconductor devices
US9379041B2 (en) * 2013-12-11 2016-06-28 Taiwan Semiconductor Manufacturing Company, Ltd. Fan out package structure
US9698121B2 (en) * 2014-01-27 2017-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and structures for packaging semiconductor dies
US9583420B2 (en) 2015-01-23 2017-02-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufactures
US10026671B2 (en) 2014-02-14 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US10056267B2 (en) 2014-02-14 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9768090B2 (en) 2014-02-14 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9935090B2 (en) 2014-02-14 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
US9653443B2 (en) 2014-02-14 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Thermal performance structure for semiconductor packages and method of forming same
US9263302B2 (en) * 2014-02-21 2016-02-16 Taiwan Semiconductor Manufacturing Company, Ltd. Via structure for packaging and a method of forming
US9293442B2 (en) 2014-03-07 2016-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US9281297B2 (en) 2014-03-07 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Solution for reducing poor contact in info packages
US9852998B2 (en) 2014-05-30 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Ring structures in device die
US9824990B2 (en) 2014-06-12 2017-11-21 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
US9881857B2 (en) 2014-06-12 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Pad design for reliability enhancement in packages
US9449947B2 (en) 2014-07-01 2016-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package for thermal dissipation
US9613910B2 (en) 2014-07-17 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Anti-fuse on and/or in package
US9754928B2 (en) 2014-07-17 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. SMD, IPD, and/or wire mount in a package
US9786631B2 (en) * 2014-11-26 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Device package with reduced thickness and method for forming same
US20160155723A1 (en) * 2014-11-27 2016-06-02 Chengwei Wu Semiconductor package
US9812337B2 (en) 2014-12-03 2017-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package pad and methods of forming
US10475764B2 (en) 2014-12-26 2019-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Die bonder and methods of using the same
US10032651B2 (en) 2015-02-12 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and method of forming the same
US10032704B2 (en) 2015-02-13 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing cracking by adjusting opening size in pop packages
US9564416B2 (en) 2015-02-13 2017-02-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and methods of forming the same
US10497660B2 (en) 2015-02-26 2019-12-03 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
US9589903B2 (en) * 2015-03-16 2017-03-07 Taiwan Semiconductor Manufacturing Company, Ltd. Eliminate sawing-induced peeling through forming trenches
US10115647B2 (en) 2015-03-16 2018-10-30 Taiwan Semiconductor Manufacturing Company, Ltd. Non-vertical through-via in package
US10368442B2 (en) 2015-03-30 2019-07-30 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit structure and method of forming
US9786519B2 (en) 2015-04-13 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and methods of packaging semiconductor devices
US9653406B2 (en) 2015-04-16 2017-05-16 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive traces in semiconductor devices and methods of forming same
US9461018B1 (en) 2015-04-17 2016-10-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out PoP structure with inconsecutive polymer layer
US9666502B2 (en) 2015-04-17 2017-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Discrete polymer in fan-out packages
US9659805B2 (en) 2015-04-17 2017-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and methods forming the same
US10340258B2 (en) * 2015-04-30 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices
US9613931B2 (en) 2015-04-30 2017-04-04 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out stacked system in package (SIP) having dummy dies and methods of making the same
US9748212B2 (en) 2015-04-30 2017-08-29 Taiwan Semiconductor Manufacturing Company, Ltd. Shadow pad for post-passivation interconnect structures
US9786574B2 (en) 2015-05-21 2017-10-10 Globalfoundries Inc. Thin film based fan out and multi die package platform
CN104916599B (zh) 2015-05-28 2017-03-29 矽力杰半导体技术(杭州)有限公司 芯片封装方法和芯片封装结构
US9627288B2 (en) * 2015-05-29 2017-04-18 Taiwan Semiconductor Manufacturing Co., Ltd. Package structures and methods of forming the same
US9484227B1 (en) 2015-06-22 2016-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Dicing in wafer level package
US9818711B2 (en) 2015-06-30 2017-11-14 Taiwan Semiconductor Manufacturing Company, Ltd. Post-passivation interconnect structure and methods thereof
US9793231B2 (en) 2015-06-30 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Under bump metallurgy (UBM) and methods of forming same
US9741586B2 (en) 2015-06-30 2017-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating package structures
US10170444B2 (en) 2015-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices
US10276541B2 (en) 2015-06-30 2019-04-30 Taiwan Semiconductor Manufacturing Company, Ltd. 3D package structure and methods of forming same
US9842826B2 (en) 2015-07-15 2017-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US9391028B1 (en) 2015-07-31 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit dies having alignment marks and methods of forming same
US9570410B1 (en) 2015-07-31 2017-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming connector pad structures, interconnect structures, and structures thereof
US10269767B2 (en) 2015-07-31 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-chip packages with multi-fan-out scheme and methods of manufacturing the same
US11018025B2 (en) * 2015-07-31 2021-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution lines having stacking vias
US10141288B2 (en) 2015-07-31 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Surface mount device/integrated passive device on package or device structure and methods of forming
US9847269B2 (en) * 2015-07-31 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out packages and methods of forming same
US9564345B1 (en) 2015-08-18 2017-02-07 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
US9768145B2 (en) 2015-08-31 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming multi-die package structures including redistribution layers
US9685411B2 (en) 2015-09-18 2017-06-20 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit dies having alignment marks and methods of forming same
US9881850B2 (en) 2015-09-18 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures and method of forming the same
US9917072B2 (en) 2015-09-21 2018-03-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated stacked package with a fan-out redistribution layer (RDL) and a same encapsulating process
US10049953B2 (en) 2015-09-21 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
US9929112B2 (en) 2015-09-25 2018-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10068844B2 (en) 2015-09-30 2018-09-04 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure and method of forming
US9704825B2 (en) 2015-09-30 2017-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Chip packages and methods of manufacture thereof
US10720788B2 (en) 2015-10-09 2020-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Wireless charging devices having wireless charging coils and methods of manufacture thereof
US9640498B1 (en) 2015-10-20 2017-05-02 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out (InFO) package structures and methods of forming same
US9691723B2 (en) 2015-10-30 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Connector formation methods and packaged semiconductor devices
US9524959B1 (en) 2015-11-04 2016-12-20 Taiwan Semiconductor Manufacturing Company, Ltd. System on integrated chips and methods of forming same
US9953892B2 (en) 2015-11-04 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Polymer based-semiconductor structure with cavity
US9953963B2 (en) 2015-11-06 2018-04-24 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit process having alignment marks for underfill
US9735131B2 (en) 2015-11-10 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US9711458B2 (en) 2015-11-13 2017-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and formation method for chip package
US9793245B2 (en) 2015-11-16 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US9786614B2 (en) 2015-11-16 2017-10-10 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure and method of forming
US9898645B2 (en) 2015-11-17 2018-02-20 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor device and method
US9627365B1 (en) 2015-11-30 2017-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Tri-layer CoWoS structure
US9892962B2 (en) 2015-11-30 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level chip scale package interconnects and methods of manufacture thereof
US9735118B2 (en) 2015-12-04 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Antennas and waveguides in InFO structures
US9893042B2 (en) 2015-12-14 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10074472B2 (en) 2015-12-15 2018-09-11 Taiwan Semiconductor Manufacturing Company, Ltd. InFO coil on metal plate with slot
US10165682B2 (en) 2015-12-28 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Opening in the pad for bonding integrated passive device in InFO package
US10050013B2 (en) 2015-12-29 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor devices and packaging methods
US9850126B2 (en) 2015-12-31 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method of forming same
US9984998B2 (en) 2016-01-06 2018-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Devices employing thermal and mechanical enhanced layers and methods of forming same
US10600759B2 (en) 2016-01-12 2020-03-24 Advanced Semiconductor Engineering, Inc. Power and ground design for through-silicon via structure
US9917043B2 (en) 2016-01-12 2018-03-13 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
US9881908B2 (en) 2016-01-15 2018-01-30 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package on package structure and methods of forming same
US9773757B2 (en) 2016-01-19 2017-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Devices, packaged semiconductor devices, and semiconductor device packaging methods
CN105489516A (zh) * 2016-01-22 2016-04-13 中芯长电半导体（江阴）有限公司 一种扇出型芯片的封装方法及封装结构
US9620465B1 (en) 2016-01-25 2017-04-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dual-sided integrated fan-out package
US9768303B2 (en) 2016-01-27 2017-09-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method and structure for FinFET device
DE102016118802B4 (de) 2016-01-29 2022-12-08 Taiwan Semiconductor Manufacturing Co. Ltd. Drahtloses Ladepaket mit in Spulenmitte integriertem Chip und Herstellungsverfahren dafür
US9761522B2 (en) 2016-01-29 2017-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Wireless charging package with chip integrated in coil center
US10269702B2 (en) 2016-01-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Info coil structure and methods of manufacturing same
US9904776B2 (en) 2016-02-10 2018-02-27 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor pixel array and methods of forming same
US9911629B2 (en) 2016-02-10 2018-03-06 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated passive device package and methods of forming same
US10797038B2 (en) 2016-02-25 2020-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and rework process for the same
US9754805B1 (en) 2016-02-25 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging method and structure
US9842815B2 (en) 2016-02-26 2017-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10062648B2 (en) 2016-02-26 2018-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
US9847320B2 (en) 2016-03-09 2017-12-19 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method of fabricating the same
US9831148B2 (en) 2016-03-11 2017-11-28 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out package including voltage regulators and methods forming same
US9859229B2 (en) 2016-04-28 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US9935024B2 (en) 2016-04-28 2018-04-03 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming semiconductor structure
US9935080B2 (en) 2016-04-29 2018-04-03 Taiwan Semiconductor Manufacturing Company, Ltd. Three-layer Package-on-Package structure and method forming same
US9997464B2 (en) 2016-04-29 2018-06-12 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy features in redistribution layers (RDLS) and methods of forming same
US9947552B2 (en) 2016-04-29 2018-04-17 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out structure
US9806059B1 (en) 2016-05-12 2017-10-31 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-stack package-on-package structures
US10797025B2 (en) 2016-05-17 2020-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Advanced INFO POP and method of forming thereof
US9870997B2 (en) 2016-05-24 2018-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10157807B2 (en) 2016-05-26 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Sensor packages and manufacturing mehtods thereof
US10269481B2 (en) 2016-05-27 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked coil for wireless charging structure on InFO package
US9852957B2 (en) 2016-05-27 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Testing, manufacturing, and packaging methods for semiconductor devices
US9941248B2 (en) 2016-05-30 2018-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. Package structures, pop devices and methods of forming the same
US9941216B2 (en) 2016-05-30 2018-04-10 Taiwan Semiconductor Manufacturing Co., Ltd. Conductive pattern and integrated fan-out package having the same
US9793246B1 (en) 2016-05-31 2017-10-17 Taiwan Semiconductor Manufacturing Co., Ltd. Pop devices and methods of forming the same
US10032722B2 (en) 2016-05-31 2018-07-24 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package structure having am antenna pattern and manufacturing method thereof
US9812381B1 (en) * 2016-05-31 2017-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US9985006B2 (en) 2016-05-31 2018-05-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10504827B2 (en) * 2016-06-03 2019-12-10 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US11056436B2 (en) 2016-06-07 2021-07-06 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out structure with rugged interconnect
US10354114B2 (en) 2016-06-13 2019-07-16 Taiwan Semiconductor Manufacturing Company, Ltd. Fingerprint sensor in InFO structure and formation method
US10276403B2 (en) * 2016-06-15 2019-04-30 Avago Technologies International Sales Pe. Limited High density redistribution layer (RDL) interconnect bridge using a reconstituted wafer
US10050024B2 (en) 2016-06-17 2018-08-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US10475769B2 (en) 2016-06-23 2019-11-12 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package and manufacturing method of the same
US10431738B2 (en) 2016-06-24 2019-10-01 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method for fabricating the same
US10229901B2 (en) 2016-06-27 2019-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Immersion interconnections for semiconductor devices and methods of manufacture thereof
US9812426B1 (en) 2016-06-29 2017-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package, semiconductor device, and method of fabricating the same
US9653391B1 (en) 2016-06-30 2017-05-16 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor packaging structure and manufacturing method thereof
US9859254B1 (en) 2016-06-30 2018-01-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and a manufacturing method thereof
US9966360B2 (en) 2016-07-05 2018-05-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US9793230B1 (en) 2016-07-08 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of forming
US10163800B2 (en) 2016-07-08 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with dummy feature in passivation layer
US9824902B1 (en) 2016-07-12 2017-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US11469215B2 (en) 2016-07-13 2022-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
US9825007B1 (en) * 2016-07-13 2017-11-21 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with molding layer and method for forming the same
US9661794B1 (en) 2016-07-13 2017-05-23 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing package structure
US9691708B1 (en) 2016-07-20 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
US10062654B2 (en) 2016-07-20 2018-08-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor structure and semiconductor manufacturing process thereof
US9799615B1 (en) 2016-07-20 2017-10-24 Taiwan Semiconductor Manufacturing Co., Ltd. Package structures having height-adjusted molding members and methods of forming the same
US10276542B2 (en) 2016-07-21 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and manufacturing method thereof
US10276506B2 (en) 2016-07-21 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package
US9984960B2 (en) 2016-07-21 2018-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10163860B2 (en) 2016-07-29 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure
US10083949B2 (en) 2016-07-29 2018-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Using metal-containing layer to reduce carrier shock in package formation
US10340206B2 (en) 2016-08-05 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Dense redistribution layers in semiconductor packages and methods of forming the same
US10134708B2 (en) 2016-08-05 2018-11-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package with thinned substrate
US10297551B2 (en) 2016-08-12 2019-05-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing redistribution circuit structure and method of manufacturing integrated fan-out package
US10672741B2 (en) 2016-08-18 2020-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages with thermal-electrical-mechanical chips and methods of forming the same
US10658334B2 (en) 2016-08-18 2020-05-19 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming a package structure including a package layer surrounding first connectors beside an integrated circuit die and second connectors below the integrated circuit die
US10120971B2 (en) 2016-08-30 2018-11-06 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and layout method thereof
US9741690B1 (en) 2016-09-09 2017-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution layers in semiconductor packages and methods of forming same
US10128182B2 (en) 2016-09-14 2018-11-13 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package structure and manufacturing method thereof
US10529697B2 (en) 2016-09-16 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
US9859245B1 (en) 2016-09-19 2018-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure with bump and method for forming the same
US9922964B1 (en) 2016-09-19 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with dummy die
US9911672B1 (en) 2016-09-30 2018-03-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices, method for fabricating integrated fan-out packages, and method for fabricating semiconductor devices
US9837359B1 (en) 2016-09-30 2017-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US10515899B2 (en) 2016-10-03 2019-12-24 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure with bump
US10157846B2 (en) 2016-10-13 2018-12-18 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming chip package involving cutting process
US10163801B2 (en) 2016-10-14 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and formation method of chip package with fan-out structure
TWI594382B (zh) * 2016-11-07 2017-08-01 矽品精密工業股份有限公司 電子封裝件及其製法
US10014260B2 (en) 2016-11-10 2018-07-03 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US10163813B2 (en) 2016-11-17 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure including redistribution structure and conductive shielding film
US9837366B1 (en) 2016-11-28 2017-12-05 Taiwan Semiconductor Manufacturing Co., Ltd. Semicondcutor structure and semiconductor manufacturing process thereof
US10103125B2 (en) 2016-11-28 2018-10-16 Taiwan Semiconductor Manufacturing Co., Ltd. Chip package structure and method for forming the same
US10177078B2 (en) 2016-11-28 2019-01-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method for forming chip package structure
US10692813B2 (en) 2016-11-28 2020-06-23 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package with dummy bumps connected to non-solder mask defined pads
US10037963B2 (en) 2016-11-29 2018-07-31 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of forming the same
US10304793B2 (en) 2016-11-29 2019-05-28 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US10128193B2 (en) 2016-11-29 2018-11-13 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
US10163824B2 (en) 2016-12-02 2018-12-25 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US9972581B1 (en) 2017-02-07 2018-05-15 Taiwan Semiconductor Manufacturing Company, Ltd. Routing design of dummy metal cap and redistribution line
US10854568B2 (en) 2017-04-07 2020-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
DE102017124104A1 (de) 2017-04-07 2018-10-11 Taiwan Semiconductor Manufacturing Co., Ltd. Packages mit si-substrat-freiem interposer und verfahren zum bilden derselben
US10522449B2 (en) 2017-04-10 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with Si-substrate-free interposer and method forming same
DE102017123449B4 (de) 2017-04-10 2023-12-28 Taiwan Semiconductor Manufacturing Co. Ltd. Gehäuse mit Si-substratfreiem Zwischenstück und Ausbildungsverfahren
IT201700055983A1 (it) 2017-05-23 2018-11-23 St Microelectronics Srl Procedimento per produrre dispositivi a semiconduttore, dispositivo a semiconduttore e circuito corrispondenti
US10170341B1 (en) 2017-06-30 2019-01-01 Taiwan Semiconductor Manufacturing Company, Ltd. Release film as isolation film in package
DE102017126028B4 (de) 2017-06-30 2020-12-10 Taiwan Semiconductor Manufacturing Co., Ltd. Gehäuse und Herstellungsverfahren mit einem Trennfilm als Isolierfilm
US10269589B2 (en) 2017-06-30 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a release film as isolation film in package
US10867924B2 (en) 2017-07-06 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package with redistribution structure and pre-made substrate on opposing sides for dual-side metal routing
US10134685B1 (en) * 2017-07-27 2018-11-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method of fabricating the same
US10522526B2 (en) 2017-07-28 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. LTHC as charging barrier in InFO package formation
US10636757B2 (en) * 2017-08-29 2020-04-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit component package and method of fabricating the same
US10290571B2 (en) 2017-09-18 2019-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with si-substrate-free interposer and method forming same
US10629540B2 (en) 2017-09-27 2020-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10727217B2 (en) 2017-09-29 2020-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device that uses bonding layer to join semiconductor substrates together
US10790244B2 (en) 2017-09-29 2020-09-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10269773B1 (en) 2017-09-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor packages and methods of forming the same
US10665582B2 (en) * 2017-11-01 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor package structure
US10861814B2 (en) * 2017-11-02 2020-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out packages and methods of forming the same
US10957672B2 (en) * 2017-11-13 2021-03-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of manufacturing the same
US11031342B2 (en) 2017-11-15 2021-06-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US10784203B2 (en) 2017-11-15 2020-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US10529650B2 (en) 2017-11-15 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US10522501B2 (en) 2017-11-17 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of forming the same
US10510634B2 (en) * 2017-11-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method
US10546817B2 (en) * 2017-12-28 2020-01-28 Intel IP Corporation Face-up fan-out electronic package with passive components using a support
US10468339B2 (en) 2018-01-19 2019-11-05 Taiwan Semiconductor Manufacturing Company, Ltd. Heterogeneous fan-out structure and method of manufacture
US10510650B2 (en) 2018-02-02 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias
US11488881B2 (en) 2018-03-26 2022-11-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11062915B2 (en) 2018-03-29 2021-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution structures for semiconductor packages and methods of forming the same
US10631392B2 (en) 2018-04-30 2020-04-21 Taiwan Semiconductor Manufacturing Company, Ltd. EUV collector contamination prevention
US10510595B2 (en) * 2018-04-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out packages and methods of forming the same
US10340249B1 (en) 2018-06-25 2019-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
US10886231B2 (en) 2018-06-29 2021-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming RDLS and structure formed thereof
US11049805B2 (en) 2018-06-29 2021-06-29 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US10825696B2 (en) 2018-07-02 2020-11-03 Taiwan Semiconductor Manufacturing Company, Ltd. Cross-wafer RDLs in constructed wafers
US11004803B2 (en) 2018-07-02 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy dies for reducing warpage in packages
US10515848B1 (en) 2018-08-01 2019-12-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method
US10832985B2 (en) 2018-09-27 2020-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Sensor package and method
US10658348B2 (en) 2018-09-27 2020-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices having a plurality of first and second conductive strips
DE102019101999B4 (de) 2018-09-28 2021-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleitervorrichtung mit mehreren polaritätsgruppen
US11164754B2 (en) 2018-09-28 2021-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out packages and methods of forming the same
US10861841B2 (en) 2018-09-28 2020-12-08 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device with multiple polarity groups
US10665520B2 (en) 2018-10-29 2020-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11217538B2 (en) 2018-11-30 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11121089B2 (en) 2018-11-30 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11011451B2 (en) 2018-12-05 2021-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11217546B2 (en) 2018-12-14 2022-01-04 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded voltage regulator structure and method forming same
US11538735B2 (en) 2018-12-26 2022-12-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming integrated circuit packages with mechanical braces
US10978382B2 (en) 2019-01-30 2021-04-13 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11018030B2 (en) 2019-03-20 2021-05-25 Semiconductor Components Industries, Llc Fan-out wafer level chip-scale packages and methods of manufacture
US11600590B2 (en) * 2019-03-22 2023-03-07 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package
US11145560B2 (en) 2019-04-30 2021-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and methods of manufacturing
US10950519B2 (en) 2019-05-31 2021-03-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11088094B2 (en) 2019-05-31 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Air channel formation in packaging process
US11133282B2 (en) 2019-05-31 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. COWOS structures and methods forming same
US11380620B2 (en) 2019-06-14 2022-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package including cavity-mounted device
US11004758B2 (en) 2019-06-17 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11133258B2 (en) 2019-07-17 2021-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. Package with bridge die for interconnection and method forming same
US11387191B2 (en) 2019-07-18 2022-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11176995B2 (en) * 2019-07-18 2021-11-16 International Business Machines Corporation Cross-point array of polymer junctions with individually-programmed conductances
US10879114B1 (en) 2019-08-23 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive fill
US11387222B2 (en) 2019-10-18 2022-07-12 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11532533B2 (en) 2019-10-18 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
DE102020114141B4 (de) 2019-10-18 2024-03-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integriertes schaltungspackage und verfahren
US11211371B2 (en) 2019-10-18 2021-12-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
US11227837B2 (en) 2019-12-23 2022-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11515224B2 (en) 2020-01-17 2022-11-29 Taiwan Semiconductor Manufacturing Co., Ltd. Packages with enlarged through-vias in encapsulant
US11227795B2 (en) 2020-01-17 2022-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11682626B2 (en) 2020-01-29 2023-06-20 Taiwan Semiconductor Manufacturing Co., Ltd. Chamfered die of semiconductor package and method for forming the same
US11393746B2 (en) 2020-03-19 2022-07-19 Taiwan Semiconductor Manufacturing Company, Ltd. Reinforcing package using reinforcing patches
US11264359B2 (en) 2020-04-27 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Chip bonded to a redistribution structure with curved conductive lines
US11948930B2 (en) 2020-04-29 2024-04-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of manufacturing the same
US11929261B2 (en) 2020-05-01 2024-03-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of manufacturing the same
US11942417B2 (en) 2020-05-04 2024-03-26 Taiwan Semiconductor Manufacturing Co., Ltd. Sensor package and method
US11670601B2 (en) 2020-07-17 2023-06-06 Taiwan Semiconductor Manufacturing Co., Ltd. Stacking via structures for stress reduction
US12094828B2 (en) 2020-07-17 2024-09-17 Taiwan Semiconductor Manufacturing Co., Ltd. Eccentric via structures for stress reduction
US11532524B2 (en) 2020-07-27 2022-12-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit test method and structure thereof
US11652037B2 (en) 2020-07-31 2023-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method of manufacture
US11454888B2 (en) 2020-09-15 2022-09-27 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of manufacture
US11868047B2 (en) 2020-09-21 2024-01-09 Taiwan Semiconductor Manufacturing Co., Ltd. Polymer layer in semiconductor device and method of manufacture
US11545406B2 (en) * 2020-10-08 2023-01-03 Advanced Semiconductor Engineering, Inc. Substrate structure, semiconductor package structure and method for manufacturing a substrate structure
US11830821B2 (en) 2020-10-19 2023-11-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacture
US12119235B2 (en) 2020-11-04 2024-10-15 Taiwan Semiconductor Manufacturing Co., Ltd. Methods of manufacture of semiconductor devices having redistribution layer using dielectric material having photoactive component
US20230106976A1 (en) * 2021-09-29 2023-04-06 Texas Instruments Incorporated Semiconductor die with solder restraining wall
US11749534B1 (en) 2022-07-21 2023-09-05 Deca Technologies Usa, Inc. Quad flat no-lead (QFN) package without leadframe and direct contact interconnect build-up structure and method for making the same
US12062550B2 (en) 2022-05-31 2024-08-13 Deca Technologies Usa, Inc. Molded direct contact interconnect substrate and methods of making same
US20230411333A1 (en) 2022-05-31 2023-12-21 Deca Technologies Usa, Inc. Molded direct contact interconnect structure without capture pads and method for the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6268642B1 (en) * 1999-04-26 2001-07-31 United Microelectronics Corp. Wafer level package
US20060189143A1 (en) * 2005-02-18 2006-08-24 Minghsing Tsai Metal structure with sidewall passivation and method
CN1926681A (zh) * 2004-01-06 2007-03-07 国际商业机器公司 用于低－k的互连结构的柔顺的钝化边缘密封
CN101110401A (zh) * 2006-07-19 2008-01-23 台湾积体电路制造股份有限公司 半导体装置及半导体封装结构
US20080277785A1 (en) * 2007-05-08 2008-11-13 Mutual-Pak Technology Co., Ltd. Package structure for integrated circuit device and method of the same

Family Cites Families (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08167630A (ja) * 1994-12-15 1996-06-25 Hitachi Ltd チップ接続構造
US5902686A (en) 1996-11-21 1999-05-11 Mcnc Methods for forming an intermetallic region between a solder bump and an under bump metallurgy layer and related structures
US6441487B2 (en) 1997-10-20 2002-08-27 Flip Chip Technologies, L.L.C. Chip scale package using large ductile solder balls
KR100327123B1 (ko) 1998-03-30 2002-08-24 삼성전자 주식회사 디램셀캐패시터의제조방법
US6303423B1 (en) * 1998-12-21 2001-10-16 Megic Corporation Method for forming high performance system-on-chip using post passivation process
US8178435B2 (en) * 1998-12-21 2012-05-15 Megica Corporation High performance system-on-chip inductor using post passivation process
US6528349B1 (en) * 1999-10-26 2003-03-04 Georgia Tech Research Corporation Monolithically-fabricated compliant wafer-level package with wafer level reliability and functionality testability
US6433427B1 (en) * 2001-01-16 2002-08-13 Industrial Technology Research Institute Wafer level package incorporating dual stress buffer layers for I/O redistribution and method for fabrication
US7498196B2 (en) * 2001-03-30 2009-03-03 Megica Corporation Structure and manufacturing method of chip scale package
KR100394808B1 (ko) * 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
DE10137184B4 (de) * 2001-07-31 2007-09-06 Infineon Technologies Ag Verfahren zur Herstellung eines elektronischen Bauteils mit einem Kuststoffgehäuse und elektronisches Bauteil
US6489656B1 (en) * 2001-10-03 2002-12-03 Megic Corporation Resistor for high performance system-on-chip using post passivation process
DE10156054C2 (de) * 2001-11-15 2003-11-13 Infineon Technologies Ag Herstellungsverfahren für eine Leiterbahn auf einem Substrat
TW503496B (en) * 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
US7579681B2 (en) * 2002-06-11 2009-08-25 Micron Technology, Inc. Super high density module with integrated wafer level packages
US6972964B2 (en) * 2002-06-27 2005-12-06 Via Technologies Inc. Module board having embedded chips and components and method of forming the same
US7470997B2 (en) * 2003-07-23 2008-12-30 Megica Corporation Wirebond pad for semiconductor chip or wafer
TWI237883B (en) * 2004-05-11 2005-08-11 Via Tech Inc Chip embedded package structure and process thereof
JP4108643B2 (ja) * 2004-05-12 2008-06-25 日本電気株式会社 配線基板及びそれを用いた半導体パッケージ
US7485956B2 (en) * 2005-08-16 2009-02-03 Tessera, Inc. Microelectronic package optionally having differing cover and device thermal expansivities
KR100653089B1 (ko) * 2005-10-31 2006-12-04 삼성전자주식회사 탄성 표면파 디바이스 웨이퍼 레벨 패키지 및 그 패키징방법
DE102006003931B3 (de) * 2006-01-26 2007-08-02 Infineon Technologies Ag Halbleiterbauteil mit oberflächenmontierbaren Außenkontakten und Verfahren zur Herstellung desselben
US20070236859A1 (en) * 2006-04-10 2007-10-11 Borland William J Organic encapsulant compositions for protection of electronic components
JP4193897B2 (ja) * 2006-05-19 2008-12-10 カシオ計算機株式会社 半導体装置およびその製造方法
US20070291440A1 (en) * 2006-06-15 2007-12-20 Dueber Thomas E Organic encapsulant compositions based on heterocyclic polymers for protection of electronic components
US20070290379A1 (en) * 2006-06-15 2007-12-20 Dueber Thomas E Hydrophobic compositions for electronic applications
US7749886B2 (en) 2006-12-20 2010-07-06 Tessera, Inc. Microelectronic assemblies having compliancy and methods therefor
US8759964B2 (en) * 2007-07-17 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level package structure and fabrication methods
US8258624B2 (en) * 2007-08-10 2012-09-04 Intel Mobile Communications GmbH Method for fabricating a semiconductor and semiconductor package
US7772691B2 (en) * 2007-10-12 2010-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Thermally enhanced wafer level package
US7906860B2 (en) * 2007-10-26 2011-03-15 Infineon Technologies Ag Semiconductor device
US7952187B2 (en) * 2008-03-31 2011-05-31 General Electric Company System and method of forming a wafer scale package
US7964450B2 (en) * 2008-05-23 2011-06-21 Stats Chippac, Ltd. Wirebondless wafer level package with plated bumps and interconnects
US7863721B2 (en) * 2008-06-11 2011-01-04 Stats Chippac, Ltd. Method and apparatus for wafer level integration using tapered vias
US8114708B2 (en) * 2008-09-30 2012-02-14 General Electric Company System and method for pre-patterned embedded chip build-up
MY149251A (en) * 2008-10-23 2013-07-31 Carsem M Sdn Bhd Wafer-level package using stud bump coated with solder
KR20100047540A (ko) 2008-10-29 2010-05-10 삼성전자주식회사 팬 아웃 웨이퍼 레벨 패키지 및 그 제조방법
US8003512B2 (en) * 2009-02-03 2011-08-23 International Business Machines Corporation Structure of UBM and solder bumps and methods of fabrication
US7851269B2 (en) 2009-02-19 2010-12-14 Intel Corporation Method of stiffening coreless package substrate
US8008125B2 (en) * 2009-03-06 2011-08-30 General Electric Company System and method for stacked die embedded chip build-up
US8163596B2 (en) 2009-03-24 2012-04-24 General Electric Company Stackable electronic package and method of making same
CN101996993A (zh) * 2009-08-13 2011-03-30 中芯国际集成电路制造(上海)有限公司 利用单一金属化的焊盘下的器件
KR101111425B1 (ko) 2009-12-30 2012-02-16 앰코 테크놀로지 코리아 주식회사 팬아웃 타입의 반도체 패키지
US20110198762A1 (en) 2010-02-16 2011-08-18 Deca Technologies Inc. Panelized packaging with transferred dielectric
US7883991B1 (en) 2010-02-18 2011-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Temporary carrier bonding and detaching processes
WO2011136403A1 (ko) * 2010-04-28 2011-11-03 주식회사 웨이브닉스이에스피 비어구조를 갖는 금속베이스 패키지 제조방법
US8361842B2 (en) 2010-07-30 2013-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Embedded wafer-level bonding approaches
US8546254B2 (en) * 2010-08-19 2013-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming copper pillar bumps using patterned anodes
US9064879B2 (en) 2010-10-14 2015-06-23 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging methods and structures using a die attach film
KR101390628B1 (ko) 2010-11-15 2014-04-29 유나이티드 테스트 엔드 어셈블리 센터 엘티디 반도체 패키지 및 반도체 소자 패키징 방법
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6268642B1 (en) * 1999-04-26 2001-07-31 United Microelectronics Corp. Wafer level package
CN1926681A (zh) * 2004-01-06 2007-03-07 国际商业机器公司 用于低－k的互连结构的柔顺的钝化边缘密封
US20060189143A1 (en) * 2005-02-18 2006-08-24 Minghsing Tsai Metal structure with sidewall passivation and method
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US20080277785A1 (en) * 2007-05-08 2008-11-13 Mutual-Pak Technology Co., Ltd. Package structure for integrated circuit device and method of the same

Cited By (47)

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Publication number Priority date Publication date Assignee Title
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US11699598B2 (en) 2015-10-20 2023-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device
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US12094728B2 (en) 2015-10-20 2024-09-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device
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US11322419B2 (en) 2016-05-05 2022-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Package with tilted interface between device die and encapsulating material
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US11018100B2 (en) 2016-12-14 2021-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a passivation layer
US12002771B2 (en) 2016-12-14 2024-06-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device having a passivation layer and method of making
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