CN104617050B - 晶圆级封装方法 - Google Patents

晶圆级封装方法 Download PDF

Info

Publication number
CN104617050B
CN104617050B CN201410762885.9A CN201410762885A CN104617050B CN 104617050 B CN104617050 B CN 104617050B CN 201410762885 A CN201410762885 A CN 201410762885A CN 104617050 B CN104617050 B CN 104617050B
Authority
CN
China
Prior art keywords
wafer
protective layer
layer
passivation layer
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201410762885.9A
Other languages
English (en)
Other versions
CN104617050A (zh
Inventor
施建根
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tongfu Microelectronics Co Ltd
Original Assignee
Tongfu Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tongfu Microelectronics Co Ltd filed Critical Tongfu Microelectronics Co Ltd
Priority to CN201410762885.9A priority Critical patent/CN104617050B/zh
Publication of CN104617050A publication Critical patent/CN104617050A/zh
Priority to US14/964,869 priority patent/US9437511B2/en
Application granted granted Critical
Publication of CN104617050B publication Critical patent/CN104617050B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • H01L2224/05008Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05567Disposition the external layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05569Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/117Manufacturing methods involving monitoring, e.g. feedback loop
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13023Disposition the whole bump connector protruding from the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13075Plural core members
    • H01L2224/1308Plural core members being stacked
    • H01L2224/13082Two-layer arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3192Multilayer coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Dicing (AREA)

Abstract

本发明涉及一种晶圆级封装方法,在晶圆上各晶片之间的连接梗上形成通孔;在所述晶圆上形成保护层,并露出用于植焊球的植球点,所述保护层包括形成在所述晶圆顶面的上保护层、形成在所述晶圆底面的下保护层、以及在各所述通孔之间的中间保护层,所述中间保护层连接所述上保护层和所述下保护层;在露出的所述植球点上植焊球;其中,所述连接梗是各晶片之间划线槽下方的连接部分。不需要形成第三钝化层,避免第三钝化层底部与晶圆之间分层,中间保护层连接上保护层和下保护层,避免保护层与晶圆之间发生分层,提高了产品的良率。

Description

晶圆级封装方法
技术领域
本发明涉及半导体封装技术领域,尤其涉及晶圆级封装方法。
背景技术
半导体器件在成本降低和前道晶圆制造工艺的提升的共同促进下,实现了同样功能的半导体器件的单体芯片尺寸越来越小的目标,可以在半导体晶圆上形成可以直接应用在印刷电路板上安装的焊球。由于半导体晶圆制造工艺局限性或者设计者出于同一款集成电路多种用途的考虑,在半导体晶圆级封装时需要对传输电信号的输入输入端子重新定义位置设置焊球。
参见图1,是有技术中重新定义焊球位置的方式晶圆结构,半导体晶圆101’主动面形成电路后表面有电极102’和第一钝化层103’,半导体晶圆上有多个半导体晶片100’,多个半导体晶片100’之间通过划线槽104a’连接;在第一钝化层上形成第二钝化层110’,第二钝化层在电极102附近形成开口;在第二造钝化层110’上形成再布线金属层210’;再形成第三造钝化层310’,第三钝化层在再布线210’上形成开口;在第三钝化层开口上形成凸点下金属层410’;通过植球回流的方法形成球形凸点510’;在半导体晶圆101’的背面贴一层背胶膜610’并固化;切割后形成全包封晶圆级封装的单体100’。
这种方式容易形成第三钝化层310’底部与再布线金属层210’顶部之间的分层,这种产品容易造成后续的电性能失效。
发明内容
在下文中给出关于本发明的简要概述,以便提供关于本发明的某些方面的基本理解。应当理解,这个概述并不是关于本发明的穷举性概述。它并不是意图确定本发明的关键或重要部分,也不是意图限定本发明的范围。其目的仅仅是以简化的形式给出某些概念,以此作为稍后论述的更详细描述的前序。
本发明还提供一种晶圆级封装方法,在晶圆上各晶片之间的连接梗上形成通孔;在所述晶圆上形成保护层,并露出用于植焊球的植球点,所述保护层包括形成在所述晶圆顶面的上保护层、形成在所述晶圆底面的下保护层、以及在各所述通孔之间的中间保护层,所述中间保护层连接所述上保护层和所述下保护层;在露出的所述植球点上植焊球;其中,所述连接梗是各晶片之间划线槽下方的连接部分。
本发明至少具备如下有益效果:不需要形成第三钝化层,避免第三钝化层底部与晶圆之间分层,中间保护层连接上保护层和下保护层,避免保护层与晶圆之间发生分层,提高了产品的良率。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为现有技术中的晶圆结构的示意图;
图2为本发明晶圆级封装方法的流程图;
图3为本发明晶圆级封装结构(芯片结构)的示意图;
图4-图8为本发明晶圆级封装方法各步骤的示意图。
附图标记:
103-第一钝化层;110-第二钝化层;210-布线金属层;105-边缘部;100a-晶片;102-电极;104a-划线槽;104b-连接梗;104c-残余的连接梗;420-铜柱;321-盲孔;321a-通孔;320-保护层;320a-上保护层;320b-下保护层;320c-中间保护层;200-芯片结构;510-焊球。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。在本发明的一个附图或一种实施方式中描述的元素和特征可以与一个或更多个其它附图或实施方式中示出的元素和特征相结合。应当注意,为了清楚的目的,附图和说明中省略了与本发明无关的、本领域普通技术人员已知的部件和处理的表示和描述。基于本发明中的实施例,本领域普通技术人员在没有付出创造性劳动的前提下所获得的所有其他实施例,都属于本发明保护的范围。
在本发明以下各实施例中,实施例的序号和/或先后顺序仅仅便于描述,不代表实施例的优劣。对各个实施例的描述都各有侧重,某个实施例中没有详述的部分,可以参见其他实施例的相关描述。
本发明涉及一种晶圆级封装方法,参见图2和3,包括步骤10,在晶圆上各晶片100a之间的连接梗上形成通孔321a(参见图6b);步骤20,在所述晶圆上形成保护层320,并露出用于植焊球510的植球点(参见图7),所述保护层包括形成在所述晶圆顶面的上保护层320a、形成在所述晶圆底面的下保护层320b、以及在各所述通孔之间的中间保护层320c,所述中间保护层连接所述上保护层和所述下保护层;步骤30,在露出的所述植球点上植焊球(参见图8)。
需要理解,所述连接梗是各晶片之间划线槽下方的连接部分。可选的保护层为树脂。采用树脂作为保护层不仅能够节约成本,还能够形成全包封的结构,能够更好的抵挡外部环境如湿气、静电对器件的损伤。同时,因为由同一种材料包裹,热膨胀系数相同,因此不会引起应力释放造成的翘曲。
当然,在植球后,需要切割连接梗,使晶圆上的各晶片成多个芯片结构200。可以理解,除了切割连接梗,保护层也需要被相应的切割,例如中间保护层可能被切割成两份,分别属于两个独立的晶片。
晶圆上包括电极以及第一钝化层,第一钝化层具有开口部,电极从所述开口部露出;在包裹所述保护层之前,在所述第一钝化层上形成布线金属层,通过所述开口部与所述电极连通。当然,电极是形成在晶圆上的,或者说是形成在晶圆上各晶片上的。
在形成上述保护层前,在布线金属层上形成铜柱,铜柱的上表面为所述植球点。
在一种可选的实施方式中,布线金属层直接形成于第一钝化层上(图中未示出)。或者也可以是在第一钝化层上先形成第二钝化层,布线金属层形成于所述第二钝化层上(图4-图8均为这种方式,并且图3示出的结构也是这种方式做成的)。
在步骤10中,在连接梗上形成通孔的可以为直接贯通连接梗形成通孔,也可以如图6a和6b所示,先从所述连接梗正面形成预定深度的盲孔321(如图6a),再研磨各晶片底面和所述连接梗的底面,直至将盲孔研磨成通孔321a(如图6b)。
为了方便理解,先说明一下在执行步骤10之前的晶圆结构及该晶圆的形成方法。
晶圆包括多个晶片100a,每个晶片上都有:电极102以及第一钝化层103,第一钝化层具有开口部,电极从开口部露出,还包括:布线金属层210,形成于第一钝化层上,通过开口部与所述电极连通;铜柱420,形成于布线金属层上;焊球510形成于所述铜柱上;保护层320,完全包裹所述晶片、电极、第一钝化层、布线金属层和所述铜柱形成的结构,焊点从所述保护层中露出。在一种可选的实施方式中,在第一钝化层和所述布线金属层之间,还形成有第二钝化层110,图3中表示的为这种形式,即在第一钝化层上形成第二钝化层,在第二钝化层上形成布线金属层。
结合本发明晶圆级封装方法和上述的晶圆,其最终制成的结构参见图3所示。
可以理解,这是单独一个晶片及其上形成的机构,即是单个的晶片结构200,当然在制造时,多个晶片100a是组成一个完整的晶圆的,在晶圆的每个晶片上都独立形成上述电极、第一钝化层、布线金属层、铜柱和焊球。每个晶片之间通过连接梗连接。另外,需要注意的是,可以将晶圆理解为是对多个晶片的统称,下文提及到的对晶圆的处理方法,相应的也表示对单个晶片同样处理。同样的,在提及晶圆时,自然的包括各晶片和连接梗,例如上述研磨晶圆底面,即研磨各晶片的底面和连接梗的底面。
另外,如上述,在制造时,多个晶片100a是组成一个完整的晶圆的,在晶圆的每个晶片上都独立形成上述电极、第一钝化层、布线金属层、铜柱和焊球等结构。每个晶片之间通过连接梗104b连接,当然,在最后会破坏连接梗的连接,使各个晶片独立。如图所示,在组成晶圆的晶片中,位于最外围的晶片外侧具有边缘部105,边缘部外侧不再连接另外的晶片。图中仅仅完整的表示了两个晶片及其上的结构,其余的晶片在图中已经简化,但已经用附图标记标出。另外,需要注意的是,在简化的部分,连接梗和晶片的尺寸都相应的进行了减小,但是对这些简化部分的处理方式是不变的,例如在简化部分的连接梗上同样有盲孔或者通孔,只是在图中所显示的较小或者不明显(如图6a至图8),而实质上与未简化示出的部分是相同的。从图6a到图8中可以看出,简化部分的盲孔或者通孔的直径与连接梗的宽度是相同的,这可以是一种实施方式,即,在连接梗上形成通孔时,该通孔直径可以与连接梗相同,最终形成芯片结构时,可能晶片结构内就不包括残余的连接梗。图3所示的晶片结构就包括残余的连接梗104c,当然如上述,在一种实施方式中,晶片结构可以没有该残余的连接梗。
在进行步骤10之前,形成上述晶圆的方法可以为:步骤1,在第一钝化层103之上,形成布线金属层210,并使布线金属层与所述电极102连接(如图4所示);步骤2,在布线金属层上形成铜柱420(参见图5)。
最后应说明的是:虽然以上已经详细说明了本发明及其优点,但是应当理解在不超出由所附的权利要求所限定的本发明的精神和范围的情况下可以进行各种改变、替代和变换。而且,本发明的范围不仅限于说明书所描述的过程、设备、手段、方法和步骤的具体实施例。本领域内的普通技术人员从本发明的公开内容将容易理解,根据本发明可以使用执行与在此所述的相应实施例基本相同的功能或者获得与其基本相同的结果的、现有和将来要被开发的过程、设备、手段、方法或者步骤。因此,所附的权利要求旨在在它们的范围内包括这样的过程、设备、手段、方法或者步骤。

Claims (7)

1.一种晶圆级封装方法,其特征在于,
在晶圆上各晶片之间的连接梗上形成通孔;
在所述晶圆上形成保护层,并露出用于植焊球的植球点,所述保护层包括形成在所述晶圆顶面的上保护层、形成在所述晶圆底面的下保护层、以及在各所述通孔之间的中间保护层,所述中间保护层连接所述上保护层和所述下保护层,形成所述保护层时,先软化所述保护层材料,使所述保护层材料从所述晶圆的一侧沿所述通孔流至另一侧,以包裹所述晶圆;
在露出的所述植球点上植焊球;
沿所述连接梗所在位置分割所述晶圆,形成多个独立的芯片结构;其中,
所述连接梗是各晶片之间划线槽下方的连接部分。
2.根据权利要求1所述的方法,其特征在于,
所述保护层的材料为树脂。
3.根据权利要求1所述的方法,其特征在于,
所述晶圆上包括电极以及钝化层,所述钝化层具有开口部,电极从所述开口部露出;
在形成所述保护层之前,在所述钝化层上形成布线金属层,所述布线金属层通过所述开口部与所述电极连通;
所述晶圆上包括电极以及第一钝化层,所述第一钝化层具有开口部,电极从所述开口部露出;
在包裹所述保护层之前,在所述第一钝化层上形成布线金属层,通过所述开口部与所述电极连通。
4.根据权利要求1所述的方法,其特征在于,
在包裹所述保护层前,在布线金属层上形成铜柱,所述铜柱的上表面为所述植球点。
5.根据权利要求3所述的方法,其特征在于,
所述布线金属层直接形成于第一钝化层上。
6.根据权利要求3所述的方法,其特征在于,
在第一钝化层上先形成第二钝化层,所述布线金属层形成于所述第二钝化层上。
7.根据权利要求1所述的方法,其特征在于,
先从所述连接梗正面形成预定深度的盲孔,再研磨晶圆底面,直至将盲孔研磨成通孔。
CN201410762885.9A 2014-12-11 2014-12-11 晶圆级封装方法 Active CN104617050B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN201410762885.9A CN104617050B (zh) 2014-12-11 2014-12-11 晶圆级封装方法
US14/964,869 US9437511B2 (en) 2014-12-11 2015-12-10 Method and structure for wafer-level packaging

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201410762885.9A CN104617050B (zh) 2014-12-11 2014-12-11 晶圆级封装方法

Publications (2)

Publication Number Publication Date
CN104617050A CN104617050A (zh) 2015-05-13
CN104617050B true CN104617050B (zh) 2017-08-11

Family

ID=53151438

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201410762885.9A Active CN104617050B (zh) 2014-12-11 2014-12-11 晶圆级封装方法

Country Status (2)

Country Link
US (1) US9437511B2 (zh)
CN (1) CN104617050B (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107910307B (zh) * 2017-12-28 2020-01-31 江阴长电先进封装有限公司 一种半导体芯片的封装结构及其封装方法
DE102019006294B3 (de) * 2019-09-05 2020-11-19 PatForce GmbH Multi-Die-Chip

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101552248A (zh) * 2008-03-31 2009-10-07 卡西欧计算机株式会社 半导体装置及其制造方法
CN102856279A (zh) * 2011-06-28 2013-01-02 台湾积体电路制造股份有限公司 用于晶圆级封装的互连结构
CN102903642A (zh) * 2011-07-29 2013-01-30 万国半导体(开曼)股份有限公司 一种将芯片底部和周边包封的芯片级封装方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8500344B2 (en) * 2011-07-25 2013-08-06 Visera Technologies Co., Ltd. Compact camera module and method for fabricating the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101552248A (zh) * 2008-03-31 2009-10-07 卡西欧计算机株式会社 半导体装置及其制造方法
CN102856279A (zh) * 2011-06-28 2013-01-02 台湾积体电路制造股份有限公司 用于晶圆级封装的互连结构
CN102903642A (zh) * 2011-07-29 2013-01-30 万国半导体(开曼)股份有限公司 一种将芯片底部和周边包封的芯片级封装方法

Also Published As

Publication number Publication date
US20160172263A1 (en) 2016-06-16
CN104617050A (zh) 2015-05-13
US9437511B2 (en) 2016-09-06

Similar Documents

Publication Publication Date Title
CN206657808U (zh) 电子装置
US9496249B2 (en) 3DIC package and methods of forming the same
TWI437682B (zh) 切割道上之穿通孔
US8957524B2 (en) Pillar structure for use in packaging integrated circuit products and methods of making such a pillar structure
US7811858B2 (en) Package and the method for making the same, and a stacked package
US8772058B2 (en) Method for making a redistributed wafer using transferrable redistribution layers
DE102012104761B4 (de) Verfahren zur Herstellung eines Halbleiter-Bauelements
US20180130768A1 (en) Substrate Based Fan-Out Wafer Level Packaging
US9806059B1 (en) Multi-stack package-on-package structures
US20120326288A1 (en) Method of assembling semiconductor device
KR101495014B1 (ko) 이동가능한 재배치층을 이용하여 재배치된 전자 디바이스의 제조방법
CN104600039B (zh) 双面互联扇出工艺
TWI518852B (zh) 半導體封裝件及其製法
TWI267172B (en) IC chip solder bump structure and method of manufacturing same
CN104617050B (zh) 晶圆级封装方法
CN106298683B (zh) 半导体器件
US20150214192A1 (en) Structure and formation method of chip package structure
CN106024749A (zh) 具有柱和凸块结构的半导体封装体
CN106611713B (zh) 半导体封装体及其制作方法
CN104599985B (zh) 全包封半导体芯片的制作方法
US20160141217A1 (en) Electronic package and fabrication method thereof
CN105006458A (zh) 一种带包封的芯片封装结构与实现工艺
US20130026605A1 (en) WLCSP for Small, High Volume Die
CN103839911A (zh) 偏置集成电路封装互连
CN107611095A (zh) 晶圆级芯片封装结构及其制备方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288

Applicant after: Tongfu Microelectronics Co., Ltd.

Address before: 226006 Jiangsu Province, Nantong City Chongchuan District Chongchuan Road No. 288

Applicant before: Fujitsu Microelectronics Co., Ltd., Nantong

COR Change of bibliographic data
GR01 Patent grant
GR01 Patent grant