CN106024749A - 具有柱和凸块结构的半导体封装体 - Google Patents

具有柱和凸块结构的半导体封装体 Download PDF

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CN106024749A
CN106024749A CN201610182620.0A CN201610182620A CN106024749A CN 106024749 A CN106024749 A CN 106024749A CN 201610182620 A CN201610182620 A CN 201610182620A CN 106024749 A CN106024749 A CN 106024749A
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layer
encapsulated layer
redistribution
contact pad
post
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J·泰伊塞伊瑞
靳永钢
刘云
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STMicroelectronics Asia Pacific Pte Ltd
STMicroelectronics Pte Ltd
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STMicroelectronics Pte Ltd
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Publication of CN106024749A publication Critical patent/CN106024749A/zh
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Abstract

一个或多个实施例涉及半导体封装体，这些半导体封装体包括柱和凸块结构。这些半导体封装体包括裸片，该裸片在该半导体裸片的周边处具有凹陷。该半导体封装体包括包封层，该包封层位于该半导体裸片之上，从而填充该凹陷并且包围这些柱的多个侧表面。该封装体可以形成在具有多个裸片的晶圆上并且可以被分割成多个封装体。

Description

具有柱和凸块结构的半导体封装体
技术领域
本披露的多个实施例涉及半导体裸片封装体以及用于组装半导体裸片封装体的工艺。
背景技术
芯片级封装体(CSP)具有非常接近半导体裸片的实际面积的占地面积并且在倒装芯片构型中通常涉及到通过多个导电凸块将封装体安装到衬底或其他器件上。晶圆级封装(WLP)涉及在切割晶圆之前使用后端晶圆加工来加工在晶圆上的裸片以便封装的工艺。
晶圆级芯片级封装(WLCSP)通常涉及到凸块工艺，该凸块工艺包括将多个导电凸块或导电球添加到晶圆上的每个半导体裸片上。典型地，首先在半导体裸片的上表面上形成多个凸块。然后，将晶圆分割以使裸片彼此分隔开。然后，可以将裸片面朝下地放置到另一个衬底上，从而使得这些导电凸块与衬底的多个焊区对齐。可以在裸片与衬底之间设置底部填充材料来包围这些凸块，由此提供进一步的结构支撑。
在晶圆级加工中，分割工艺可能造成裸片缺陷。例如，使用锯片的分割可能会压碎裸片的多个部分或者在裸片中的一个或多个层中造成豁口。即使被压碎的部分和有豁口的层不在裸片的有源区域中，其也可能会引起结构弱点，这些结构弱点引起裂纹延伸穿过裸片，由此引起可靠性问题。
发明内容
一个或多个实施例涉及半导体结构，这些半导体结构包括柱和凸块结构。这些半导体结构包括包封层，该包封层包围这些柱的多个侧表面。该结构可以是被分割成多个裸片或封装体的晶圆。
在一个实施例中，提供了具有多个半导体裸片的晶圆。在半导体裸片的上表面之上形成了多个导电柱和多个重分布层(RDL)。在一个实施例中，导电柱位于重分布层的多个导电焊盘之上。包封层(如模制化合物)形成在裸片的上表面之上并且包围导电柱和重分布层。在一些实施例中，该包封层延伸到形成在晶圆的上表面中的多个凹陷中。这些凹陷位于裸片之间的锯切或划片轨道中。这些导电柱的上表面是外露的并且在这些导电柱的外露的上部分上形成了多个导电凸块。可以将晶圆分割以形成多个单独的封装体。
在另一个实施例中，这些导电柱位于半导体裸片的多个接触焊盘上。包封层被形成在裸片的上表面之上并且包围这些导电柱。重分布层形成在包封层之上并且重分布用于封装体的输入/输出(i/o)焊盘。这些导电柱的上表面是外露的，并且在这些导电柱的外露的上部分上形成了多个导电凸块。
附图说明
在这些附图中，相同的参考号标识相似的元件。附图中元件的大小和相对位置不一定成比例地绘制。
图1是根据本披露的一个实施例的具有导电凸块的封装体的一部分的示意性横截面视图。
图2A至图2G是用于图1的裸片的凸块工艺的不同阶段的局部示意性横截面视图。
图3是根据本披露的另一个实施例的封装体的一部分的示意性横截面视图。
图4A至图4F是用于图3的裸片的凸块工艺的不同阶段的局部示意性横截面视图。
具体实施方式
在以下描述中，列举了某些具体细节以便提供对本披露的各种方面的透彻理解。然而，在本披露中所描述的本发明可以在没有这些具体细节的情况下实施。在一些实例中，没有详细描述公知结构和形成与半导体裸片相关联的结构的方法以避免使对本披露的这些实施例和方面的描述变得模糊。
根据本发明的一个实施例，图1是封装体10的示意性侧视图，该封装体包括半导体裸片和至少一个凸块12。该半导体裸片包括半导体衬底11(如硅)并且包括一个或多个电部件，该一个或多个电部件包括现有技术中众所周知的无源部件和有源部件，如集成电路。该半导体衬底可能已经被打薄到具有在约200微米至400微米范围内的厚度。
裸片的上表面包括一个或多个接触焊盘14，该一个或多个接触焊盘电耦接至集成电路。在那方面，这些接触焊盘14为该集成电路外部通向裸片12提供了电连通。这些接触焊盘14可以是任何合适的导电材料，并且在一个实施例中包括铝。
在裸片14的上表面之上是第一电介质层16，又被称为第一钝化层。第一电介质层16可以是为裸片14的这些电部件提供保护的任何电介质材料。在一些实施例中是氮化硅的第一电介质层16包括在这些接触焊盘14之上的多个开口，由此使每个接触焊盘14的至少一部分外露。
在第一电介质层16之上的是重分布层(RDL)18，该重分布层用于重分布这些接触焊盘14，如在现有技术中众所周知的。这些接触焊盘14的重分布不仅使接触焊盘重分布，而且还可以增大被重分布的接触焊盘的大小并且在相邻的重分布的接触焊盘或i/o焊盘之间提供合适的间距。
RDL 18包括第二电介质层20，又被称为第二钝化层或再钝化层。第二电介质层18可以比第一电介质层16更厚。第二电介质层20包括在这些接触焊盘14之上的多个开口。在所展示的实施例中，第二电介质层20完全覆盖包括在这些接触焊盘14之上的第一电介质层16。第二电介质层20可以是任何电介质层，并且在一些实施例中是聚酰亚胺或聚对苯撑苯并双恶唑(PBO)。
RDL 18进一步包括一个或多个导电层22，该一个或多个导电层重分布接触焊盘14。导电层22可以包括延伸到第一和第二电介质层16和20的开口中的一种或多种导电材料，从而与相应的接触焊盘14接触。导电层22进一步包括迹线，该迹线沿第二电介质层20的上表面以及重分布焊盘或i/o焊盘延伸。在那方面，导电层22在这些接触焊盘14与这些i/o焊盘之间提供了电路径。该一个或多个导电层22可以包括任何导电材料，并且在一个实施例中为铜。
在这些i/o焊盘之上是多个导电柱30。这些导电柱30通过RDL18的导电层22与这些接触焊盘14电连通。导电柱30可以是任何导电材料，并且在一个实施例中为铜。导电柱30可以以任何形状(包括圆形、椭圆形、方形、六边形、八边形等)从这些i/o焊盘的表面向上延伸。导电柱30具有的高度足以将导电柱30与导电层22间隔开，从而使得导电层22可以被电介质材料覆盖，如以下将讨论的。在一些实施例中，导电柱在20-100微米之间并且在一个实施例中在30-80微米之间。
在裸片的半导体衬底11的上表面处是凹陷34。凹陷34位于半导体裸片的周边处并且延伸到半导体衬底11中。凹陷34可以包围裸片的整个周边或者可以沿该裸片的一个或多个侧表面延伸。在所展示的实施例中，凹陷34形成了两个垂直表面，但是凹陷34可以是任何形状，包括致使凹陷中的半导体衬底11在拐角处倾斜或修圆的一种形状。
在所展示的实施例中，凹陷34具有的深度小于半导体衬底11的厚度的约20％。凹陷34可以具有任何深度使得半导体衬底11在凹陷34下方的剩余部分具有合适的长度，从而经受住包括组装在内的下游加工。在一个实施例中，凹陷34具有小于半导体衬底11的厚度的50％的任何深度。
包封层40位于凹陷34中、在裸片的上表面之上、并且沿柱30的多个侧表面。凹陷34填充有包封层40。柱30具有上表面，该上表面与包封层40的上表面共面。在那方面，包封层40的厚度的至少一部分基本上类似于柱30的厚度。
包封材料40可以是模制化合物，如聚合物树脂。包封层40可以为半导体裸片的电特征提供改善的保护。例如，包封层40可以提供改善的粘合特性，由此为封装体10提供改善的保护。由于包封层40位于凹陷34中，在后续加工过程中(如划切)，包封层40为半导体裸片的侧表面和周边提供改善的保护。
此外，包封层40保护裸片的各个部分不受外部环境源的损坏，如腐蚀、物理损坏、潮湿损坏或对电子器件的其他损坏原因。例如，在一些情况下，包封层40可以防止第一和/或第二电介质层分层，由此减少在半导体裸片中由于钝化分层而引起的电故障。在一些实施例中，包封层可以减少在分割(如锯切、激光切割)过程中引起的豁口和压碎。
多个导电凸块12位于这些导电柱30上。如本领域众所周知的，这些导电凸块12被配置成将封装体10的裸片的多个电部件电耦接至另一个衬底或器件的焊区以用于倒装芯片封装。这些导电凸块12可以是能够在裸片与其随后耦接至的衬底或器件之间提供电连通和机械耦接的任何材料。在一些实施例中，导电凸块12是铜、铅、锡、银、或其任意组合。
尽管仅示出了一个凸块12和柱30，但应理解的是，封装体10包括多个接触焊盘14，各自具有耦接到其上的相应的导电凸块12和导电柱30。示出一个凸块、柱和接触焊盘，从而使得可以在附图中更加清楚地示出本发明的细节。
图2A至图2F展示了晶圆60在用于形成图1的封装体10的各个制造阶段的多个横截面视图。如在图2A中所示，提供了包括多个裸片的晶圆60。这些电特征(如与裸片关联的键合焊盘和集成电路)已经被形成了。在那方面，晶圆的前端加工已经完成。应理解的是，前端加工的最后步骤之一包括形成第一电介质层16，使用标准半导体加工技术将该第一电介质层沉积在晶圆60上。可以使用在每个裸片的接触焊盘14之上的掩模层来沉积第一电介质层16，如在现有技术中众所周知的。替代地，如在现有技术中众所周知的，第一电介质层16被均厚沉积在整个晶圆60之上，并且如通过在这些接触焊盘14之上的掩模刻蚀来去除第一电介质层16的多个部分。
如图2B中所示，重分布层18形成在第一电介质层16之上。重分布层18包括沉积第二电介质层。如上所述，第二电介质层20可以是与第一电介质层16相同材料的或不同材料的。
如图2B中所示，重分布层的导电层22形成在第二电介质层之上。导电层22可以是通过标准加工技术来沉积的。导电层22可以包括相继沉积的多个导电层。此外，可以从迹线在单独的步骤中形成导电层22的通孔。
如图2C中所示，在导电层22上形成多个柱30。在一些实施例中，可以在导电层22的i/o焊盘与柱30之间沉积导电材料，从而改善柱30与导电层22之间的粘合。可以使用标准半导体加工技术来沉积该柱。
如图2D中所示，在裸片之间的轨道中形成了多个凹陷34。可以使用半导体加工技术、通过用于形成凹陷的任何方法(包括刻蚀、激光切割、和锯切)来形成这些凹陷34。在一个实施例中，使用了激光器。激光步骤可以包括多步骤过程，其中，在晶圆的裸片之间的轨道处引导两条窄光束。以网格图形使晶圆和激光器相对于彼此移动，从而使得激光器以网格图形切入半导体衬底的轨道中。在晶圆的网格之上的第一遍中，光束彼此间隔开第一距离，由此以希望的深度去除半导体衬底11的一部分。在第二遍中，窄光束在一起被放置地更近，从而进一步以相同的深度来去除半导体衬底11。在第三遍中，宽束激光可以被引导在凹陷处，从而去除半导体衬底在凹陷中的任何剩余部分。
如图2E中所示，包封层40形成在晶圆60之上，覆盖晶圆60的上表面并且填充轨道中的凹陷34。可以通过模制加工来形成包封层40，其中，可流动的材料被提供到模具中以固持住晶圆60并且被允许随时间来沉落或硬化。可流动材料的沉落或硬化可以包括一个或多个固化步骤。在一个实施例中，包封层40可以是模制化合物，如聚合物树脂。
如图2E中所示，包封层40可以完全包围这些柱。如图2F中所示，可以使晶圆60变薄，从而去除包封层40的一部分，由此使柱30外露。在那方面，包封层40的上表面42与柱30的上表面共面。在研磨步骤中可以使晶圆变薄，其可以包括研磨液。打薄工艺可以是被配置成去除包封层40以使柱30的上表面外露的任何工艺，包括化学机械抛光(CMP)。
如图2G中所示，在柱30的外露表面上形成了导电凸块12。导电凸块12是由标准半导体加工技术形成的，包括如现有技术中众所周知的焊料凸块滴。
如图2G中所示，在轨道中分割晶圆60，从而将裸片分成单独的封装体，如箭头所指示的。可以由任何合适的半导体加工技术来执行分割步骤，如锯切或激光切割。在填充有包封层40的凹陷34处的轨道中分割晶圆。由于凹陷34，半导体衬底11在轨道中比在晶圆的其余部分上更薄。由于半导体衬底11和包封层40在凹陷34中的厚度减小，晶圆基本上比现有技术更易于分割。包封材料是比半导体衬底11更柔软的材料，使其易于切透。因此，改善了锯片的寿命并且减少了分割加工时间。此外，包封层40具有良好的粘合特性，由此为封装体10上的电特征提供了更好的保护。此外，填充有包封层40的凹陷34在到达这些电特征之前为覆盖有包封材料的裸片提供了更多的表面面积，由此较现有技术提供了更好的保护和改善的可靠性。
由于锯片的厚度或激光束的厚度，分割晶圆可以去除填充有包封层40的凹陷34。替代地，凹陷34的填充有包封层40的部分可以被保留在裸片的周边处，如图1中所示。应理解的是，在一些实施例中，保留在裸片上的凹陷34可以具有任何大小，并且在一些实施例中，在分割步骤过程中完全去除了凹陷34。
图3展示了根据第二实施例的封装体10a。图3的封装体10a的许多特征类似于图1的封装体10。图3的封装体10a的与图1的封装体10具有相同结构和作用的特征为了简洁起见将不再描述，而以下将讨论不同之处。
如图3中所示，柱30a位于键合焊盘14上。柱30a与图1的柱30类似；然而，图3的柱30a在大小上可以更小，如所示。在所展示的实施例中，柱30a与键合焊盘14直接接触，但是还可以在其之间具有导电层。
裸片在半导体衬底11的周边处包括凹陷34a。尽管凹陷34a具有比图1的凹陷34的深度更大的深度，但应理解的是，凹陷34a的深度可以是比半导体衬底11的厚度的50％更小的任何深度。
包封层40位于裸片之上、在凹陷34a中、并且沿柱30a的多个侧表面。在包封层40的上表面之上的是对裸片的接触焊盘14进行重分布的RDL 18a。RDL 18a包括一个或多个导电层22a以及上电介质层44。导电层22a包括第一接触焊盘、迹线、和i/o焊盘。上电介质层44保护导电层22a。上电介质层44可以是被配置成粘附至导电层22a和包封层40的任何电介质层。
导电凸块12a位于导电层22a的i/o焊盘之上。如在半导体行业中众所周知的，可以在i/o焊盘上、导电凸块12a下设置底部凸块材料(UBM)46。UBM 46可以是改善导电层22a与导电凸块12a之间的粘合的任何材料。
图4A至图4F展示了晶圆60a在用于形成图3的封装体10a的各个制造阶段的横截面视图。许多制造步骤类似于参照图3A至图3G中行的那些步骤，然而，其顺序可能不同。为了简洁起见，将不再重复那些步骤的细节。
如图4A中所示，在晶圆60a的键合焊盘14上形成了多个柱30a。如图4B中所示，在晶圆60a的介于各个裸片之间的轨道中形成了多个凹陷34a。如图4C中所示，包封层40形成在晶圆60a的表面之上、填充这些凹陷34a并且至少覆盖这些柱30的多个侧表面。如图4D中所示，可以去除包封层40的上表面的一部分以使柱30a外露。如图4E中所示，重分布层18a形成在包封层和这些柱之上。如图4F中所示，在重分布层18a的i/o焊盘上形成了多个导电凸块12a。如由箭头所指示的，在裸片之间的轨道中分割晶圆60a以形成多个单独的封装体。
上述各实施例可以被组合以提供进一步的实施例。在本说明书中所提及的和/或在申请资料表中所列出的所有美国专利、美国专利申请出版物、美国专利申请、国外专利、国外专利申请和非专利出版物都以其全文通过引用并入本文。如果有必要，可以对实施例的各方面进行修改，以采用各专利、申请和公开的概念来提供更进一步的实施例。
鉴于以上详细说明，可以对实施例做出这些和其他变化。总之，在以下权利要求书中，所使用的术语不应当被解释为将权利要求书局限于本说明书和权利要求书中所披露的特定实施例，而是应当被解释为包括所有可能的实施例、连同这些权利要求有权获得的等效物的整个范围。相应地，权利要求书并不受本披露的限制。

Claims (16)

1.一种半导体结构，包括：
上表面；
第一接触焊盘，所述第一接触焊盘位于所述上表面上；
重分布层，所述重分布层包括迹线和重分布的接触焊盘，所述重分布的接触焊盘与所述第一接触焊盘电连通；
导电柱，所述导电柱位于所述第一接触焊盘上或所述重分布的接触焊盘上；
包封层，所述包封层位于所述上表面之上并且围绕着所述导电柱；以及
在所述导电柱上的导电凸块，所述导电凸块位于所述包封层上方。
2.如权利要求1所述的半导体结构，其中，所述导电柱位于所述第一接触焊盘上。
3.如权利要求1所述的半导体结构，其中，所述重分布层位于所述导电柱之上。
4.如权利要求1所述的半导体结构，其中，所述导电柱位于所述重分布的接触焊盘上。
5.如权利要求1所述的半导体结构，其中，所述包封层位于所述重分布层的至少一部分之上。
6.如权利要求1所述的半导体结构，其中，所述导电柱具有第一表面并且所述包封层具有第二表面，其中，所述第一表面与所述第二表面齐平。
7.如权利要求1所述的半导体结构，其中，所述包封层是模制化合物。
8.如权利要求7所述的半导体结构，其中，所述模制化合物是树脂。
9.如权利要求1所述的半导体结构，进一步包括半导体裸片，其中，所述上表面是所述裸片的上表面，其中，所述半导体裸片具有周边并且在所述裸片的所述周边处包括凹陷。
10.一种方法，包括：
在被安排在晶圆上的多个半导体裸片之上形成多个重分布层，从而重分布所述多个半导体裸片的多个接触焊盘，所述多个重分布层各自包括至少一个重分布的接触焊盘；
在所述多个半导体裸片之上形成多根柱，所述多根柱分别被电耦接至所述多个半导体裸片的所述多个接触焊盘；
在所述多个半导体裸片之上并且至少沿所述多根柱的多个侧表面形成包封层，其中，所述包封层的表面与所述多根柱的表面基本上齐平；并且
在所述多根柱上形成多个导电凸块。
11.如权利要求10所述的方法，其中，形成所述柱包括直接在所述半导体裸片的所述接触焊盘上形成所述柱，并且其中，形成所述重分布层包括在所述柱之上形成所述重分布层。
12.如权利要求10所述的方法，其中，形成所述柱包括直接在所述重分布的裸片上形成所述柱。
13.如权利要求10所述的方法，其中，形成所述多个柱和形成所述包封层在形成所述多个重分布层之前发生。
14.如权利要求10所述的方法，进一步包括在所述晶圆中在所述多个半导体裸片之间形成多个凹陷，其中，形成所述包封层包括用所述包封层填充所述多个凹陷。
15.如权利要求10所述的方法，其中，形成所述包封层包括将所述包封层形成为包围所述柱，所述方法进一步包括：去除所述包封层的一部分并且致使所述包封层的表面与所述柱的表面基本上齐平。
16.如权利要求10所述的方法，其中，形成所述包封层包括使用模具来注入模制化合物。
CN201610182620.0A 2015-03-31 2016-03-28 具有柱和凸块结构的半导体封装体 Pending CN106024749A (zh)

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