CN108695169B - 制作多个封装半导体器件的方法 - Google Patents

制作多个封装半导体器件的方法 Download PDF

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CN108695169B
CN108695169B CN201810328308.7A CN201810328308A CN108695169B CN 108695169 B CN108695169 B CN 108695169B CN 201810328308 A CN201810328308 A CN 201810328308A CN 108695169 B CN108695169 B CN 108695169B
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die
encapsulant
receiving surface
carrier
sawing
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CN108695169A (zh
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耶斯特·德威特
安托尼斯·亨德里库斯·尤立夫·坎菲斯
简·古利潘
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NXP BV
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Abstract

一种制作多个封装半导体器件的方法。所述方法包括：提供载体坯料，所述载体坯料具有管芯接纳表面和底面。所述方法还包括：将多个半导体管芯安装到所述管芯接纳表面上，其中所述管芯延伸到在所述管芯接纳表面以上的第一高度。所述方法进一步包括：将封料布置在所述管芯接纳表面，其中所述封料的上表面位于所述第一高度以上。所述方法还包括：通过锯切到所述底面中穿过所述载体坯料且部分地穿过所述坯料到在所述第一高度与所述上表面中间的深度来进行单体化以形成所述多个封装半导体器件，其中所述锯切将所述载体坯料分为多个载体；以及从所述封料的所述上表面移除封料，至少直到达到所述锯切深度。

Description

制作多个封装半导体器件的方法
技术领域
本说明书涉及一种制造多个封装半导体器件的方法。本说明书还涉及根据所述方法制作的多个封装半导体器件。
背景技术
由于半导体器件的封装体变得越来越小，对单独产品的测试变得更加困难。产品的测试需要良好的稳定性和刚性，因为测试中所使用的探针需要保持与引线良好地接触。此外，共面性非常重要，并且应当一次处理一个产品的事实使得单独测试的成本效益低。
除了关于测试的问题之外，封装体厚度也是当前模制技术所关注的问题。薄模制帽盖的模制必须用昂贵的模制设备(如压缩模制设备)来执行。就封料的厚度而言，此工艺具有大的公差。由于这一情况，如上文中所提及的对单独产品的测试可能存在造成封装体裂缝的风险。
发明内容
在所附的独立权利要求和从属权利要求中阐述了本公开的方面。来自从属权利要求的特征的组合可以酌情且不仅仅如权利要求书中清楚阐述的那样与独立权利要求的特征组合。
根据本公开的方面，提供了一种制作多个封装半导体器件的方法，所述方法包括：
提供载体坯料，所述载体坯料具有管芯接纳表面和底面；
将多个半导体管芯安装到所述载体坯料的所述管芯接纳表面上，其中所述管芯延伸到在所述管芯接纳表面以上的第一高度；
将封料布置在所述管芯接纳表面上，其中所述封料的上表面位于所述第一高度以上，由此所述封料覆盖所述多个半导体管芯；以及
通过以下方式使所述载体坯料和封料单体化以形成所述多个封装半导体器件：
锯切到所述载体的所述底面中以便锯切穿过所述载体坯料且部分地锯切穿过所述封料到在所述第一高度与所述封料的所述上表面中间的锯切深度，其中所述锯切将所述载体坯料分为多个载体，每个载体具有与所述载体坯料的所述底面相对应的底面以及与所述载体坯料的所述管芯接纳表面相对应的管芯接纳表面，其中每个载体的所述管芯接纳表面将所述半导体管芯中的至少一个半导体管芯安装在其上；以及
从所述封料的上表面移除封料，至少直到达到所述锯切深度。
通过根据包括锯切到载体坯料的底面中和从封料的上表面移除封料的两阶段工艺进行单体化，封料可用于在一个或多个其它制造步骤(例如，测试步骤和/或焊料回流)期间将半导体封装体保持在一起。例如，这些其它步骤可以在载体已通过锯切彼此分离之后、但在封料从上表面移除之前执行。这意味着可以在封料仍然相对较厚(与最终封装器件相比)的同时执行这些其它制造步骤。由于这样，因此可以降低与对器件造成的潜在损害(例如，在测试期间通过探针使器件发生裂缝)相关联的风险。此外，通过选择锯切深度和从封料的上表面移除的封料的量，可以便利地选择最终封装体中封料的厚度。
所述方法可以包括：使电探头(例如，(多个)探针)接触到所述载体中的至少一些载体的所述底面以便测试所述封装半导体器件。所述使电探头接触到所述载体中的至少一些载体的所述底面可以在所述锯切之后且在所述从所述封料的上表面移除封料之前执行。以此方式，可以在封料仍将封装体保持在一起的同时执行测试，从而在测试期间便利地提供封装体的机械稳定性。
所述方法可以包括：执行焊料回流。焊料回流可以在封料从其上表面移除之前执行，使得封料可以在焊料回流工艺期间将封装体保持在一起。
所述焊料回流可以在所述测试所述封装半导体器件之后执行。所述方法可以进一步包括：使电探头接触到所述载体中的至少一些载体的所述底面以便在执行所述焊料回流之后再测试所述封装半导体器件。再测试所述封装半导体器件可以在从封料的上表面移除封料之前执行，从而再次便利地允许封装体保持在位，同时执行再测试。
所述方法可以包括：在将所述封料布置在所述管芯接纳表面上之前，电力地使用引线键合来将每个半导体管芯连接到所述载体坯料。
在所述封料布置在所述管芯接纳表面上之后，相比于所述键合线，所述封料可以在所述管芯接纳表面上方延伸到更大的高度，使得所述封料覆盖所述键合线。
在所述从所述封料的上表面移除封料之后，相比于所述键合线，所述封料仍在所述管芯接纳表面上方延伸到更大的高度，使得所述封料仍覆盖所述键合线。
每个半导体管芯可以具有其上提供有一个或多个电连接的主表面。将所述半导体管芯安装到所述管芯接纳表面上可以包括：通过将每个管芯的所述主表面上的所述电连接电连接到所述管芯接纳表面来将每个管芯的所述主表面附接到所述管芯接纳表面。以此方式，本公开的实施例可以与倒装芯片制造工艺兼容。
在所述从所述封料的上表面移除封料之前，所述方法可以包括：将所述载体的所述底面安装到研磨带上。这可以允许在所述从所述封料的上表面移除所述封料期间且之后将所述半导体封装体保持在位。
如本文中所使用的，术语锯切可以包括以下各项中的任何项：刀片锯切、等离子体锯切、消融锯切或激光锯切。
根据本公开的另一方面，提供了一种通过上文中所阐述的方法制造的封装半导体器件。
附图说明
此后将仅通过举例的方式参考附图来描述本公开的实施例，在附图中，类似的附图标记涉及类似的元件，并且在附图中：
图1至图4示出了根据本公开的实施例的制造多个封装半导体器件的多个初始步骤，每个封装半导体器件包括引线键合的封装体；
图5至图7示出了根据本公开的另一实施例的制造多个封装半导体器件的多个初始步骤，每个封装半导体器件包括倒装芯片封装体；并且
图8至图10示出了根据本公开的实施例的制造多个封装半导体器件的多个进一步步骤-图8至图10中的步骤可以用于例如制造引线键合的封装体(根据图1至图4)或倒装芯片封装体(根据图5至图7)。
具体实施方式
下面参考附图描述了本公开的实施例。
图1至图4示出了根据本公开的实施例的制造多个封装半导体器件的多个初始步骤，每个封装半导体器件包括引线键合的封装体。
在图1所示的第一步骤中，所述方法包括提供载体坯料2。如随后将关于图7至图9所描述的，可以使载体坯料2单体化以形成多个封装半导体器件。在图1至图4(以及还有图5至图7)中，仅示出了载体坯料2的在单体化之后随后将形成封装体中的一个封装体中的载体的部分，使得可以提供每个随后形成的封装体的特征的详细视图。将了解，图1至图4(以及还有图5至图7)所示的安排可以跨更大的载体坯料2重复并且随后被单体化，以用于形成更多个封装体，从而允许容易地缩放制造方法。
成品封装器件的载体可以例如包括如半导体封装领域中所已知的引线框。引线框可以包括用于将半导体管芯安装到其上并用于制作到半导体管芯的适当的电连接的金属件。在另一个示例中，成品封装器件的载体可以包括电介质部分(例如，衬底)，所述电介质部分包括用于形成到半导体管芯的连接且用于形成最终封装体器件的外部连接的一个或多个金属表面层。在一些示例中，金属填充的过孔可以延伸穿过电介质部分，以用于将封装体的外部连接与位于半导体管芯的主表面上的任何电连接连接在一起。将了解，在如下文所描述的使封装体单体化之前，载体坯料2可以包括单片式工作件，所述单片式工作件包括安排成阵列(例如，线性条或以网格形式)的多个部分，每个部分与封装器件的最终载体相对应。
载体坯料2包括管芯接纳表面3和底面5。管芯接纳表面3和/或底面5可以是基本上平面的。载体坯料2的底面5是载体坯料2的与管芯接纳表面3相反的表面。在一些示例中，载体坯料2包括被一个或多个开口9彼此隔离开的单独部分。开口9可以例如填充有电介质，如待在下文中更加详细地描述的封料20。开口9可用于使载体坯料2的不同部分彼此电隔离，以便允许从待安装到坯料2上的半导体管芯的电连接和最终封装体器件的外部接触的正确路由。
在图2所示的下一步骤中，可以将多个半导体管芯4安装到载体坯料2上。具体地，可以将管芯4安装到管芯接纳表面3上。如上文中所指出的，图1至图4仅示出了整个载体坯料2的与最终封装体半导体器件中的单个最终封装体半导体器件相对应的部分，并且因此，在图2中仅示出了单个管芯4。注意，虽然还设想在一些示例中，单个最终封装体器件中可以提供多于一个管芯4。在这样的情况下，每个封装体的管芯可以并排提供在载体的管芯接纳表面上和/或可以堆叠在管芯接纳表面上。
半导体管芯4可以例如包括硅。将每个封装体的(多个)半导体管芯安装到载体上可以用多种方式实现。例如，这可以包括管芯键合和引线键合(其示例示出在图1至图4中)或通过使用凸起管芯和倒装芯片法(其示例示出在图5至图7中)。
在本示例中，半导体管芯4具有主表面，所述主表面在本示例中包括一个或多个电接触，如键合焊盘6。在此实施例中，包括键合焊盘6的主表面背离管芯接纳表面3，并且管芯4的底面用例如粘合剂8附接至管芯接纳表面3。
在图3所示的下一阶段中，用键合线12将半导体管芯4的键合焊盘6附接到载体坯料2的一个或多个电连接。具体地，设想的是，键合线12可以将键合焊盘6连接到位于载体坯料2的管芯接纳表面3上的电连接。
在下一步骤中，将封料20布置在载体坯料2的管芯接纳表面3上。出于已在上文中提及的原因，图4中仅示出了封料20的与最终封装体器件中的一个最终封装体器件相对应的部分。如图4中可见，在此示例中，封料20完全覆盖半导体管芯4、管芯接纳表面3和键合线12。具体地，在本示例中，封料20延伸到在载体坯料2的管芯接纳表面3以上的高度h2，半导体管芯4延伸到在管芯接纳表面3以上的高度h1，并且键合线延伸到在管芯接纳表面3以上的高度h3，其中h2高于h3和h1。
图1至图4与引线键合被用于将半导体4连接到载体的示例实施例相对应。然而，本公开的实施例还与倒装芯片技术兼容。现在关于图5至图7来描述其示例。
图5至图7示出了根据本公开的另一实施例的制造多个封装半导体器件的多个初始步骤，每个封装半导体器件包括倒装芯片封装体。
在图5中，提供了载体坯料2，载体坯料2可以类似于上文中关于图1所描述的所述载体坯料。
在图6所示的下一步骤中，将封料4安装到载体坯料2的管芯接纳表面3上。再次，半导体管芯4可以例如包括硅。半导体管芯4包括位于其主表面上的电连接6。为了将半导体管芯4安装到载体坯料2上，可以翻转半导体管芯4，使得主表面向下面向载体坯料2的管芯接纳表面3。然后，形成在半导体管芯4的主表面上的电连接6可被电连接到提供在管芯接纳表面3上的相应接触。在一些示例中，管芯4与载体坯料2之间的连接可以包括一个或多个焊球，虽然也可以使用其它类型的连接。注意，在半导体管芯4被安装到载体坯料2上(如图6所示)时，半导体管芯4的底面背离管芯接纳表面3。如图6所示，在一些示例中，半导体管芯4的底面可以提供有保护层7。
在下一步骤(图7)中，可以将封料20布置在管芯接纳表面3上。与上文中关于图4所描述的示例一样，封料20的上表面位于在管芯接纳表面3以上的高度h2，而管芯4延伸到在管芯接纳表面3以上的高度h1，其中h2大于h1，使得封料20覆盖管芯接纳表面3并且还覆盖半导体管芯4。注意，在图4和图7所示的两个示例中，封料20的一部分延伸到上文中关于图1所描述的开口9中。因此，封料20还可以用于在如待在下文中描述的单体化发生之后将封装器件的载体的各个部分固定在一起。
图8至图10示出了根据本公开的实施例的制造多个封装半导体器件的多个进一步步骤。关于制造引线键合的封装体(例如，根据图1至图4)描述了图8至图10的实施例。然而，将了解，图8至图10中的步骤还适用于倒装封装体(例如，根据图5至图7)。
图8至图10示出了，在布置了封料20之后，可以使载体坯料2和封料20单体化以形成多个封装半导体器件。在本示例中，每个封装半导体器件将会包括安装在载体上的单个半导体管芯4，然而，如上文中所指出的，将了解，可以在每个封装体中的单个单体化的载体上提供多于一个管芯4。
将了解，封装体的载体可以以行的形式提供在坯料2中(例如，根据图8)。然而，还将了解，在一些示例中，载体坯料2可被提供为待单体化的载体网格，并且载体坯料2和封料20的锯切可以发生在两个维度中(其中锯切巷道采取网格等形式)。
载体坯料2和封料20的单体化可被实施为具有至少两个步骤的工艺。第一步骤示出在图8中并且第二步骤示出在图10中。可以有一个或多个中间步骤，所述一个或多个中间步骤的示例将会在下文中关于图9进行描述。
在图8所示的步骤中，用例如锯片30来锯切成载体坯料2的底面5。在本示例中，使用了刀片锯切。然而，还设想的是，反而可以使用替代性方法，如等离子体锯切、消融锯切或激光锯切。
在图8(以及还有图9)中，载体坯料2、封料20和管芯以及键合线12的安排被示出为是倒置的以用于锯切步骤。这一倒置并不被认为是必要的。
如图8中可见，锯切巷道22完全延伸穿过载体坯料2，从而将载体坯料2单体化为多个单独的载体。锯切巷道22还延伸穿过载体坯料2并且延伸到封料20中到距载体坯料2的底面5的深度d。如图8所示，每个锯切巷道的深度d为使得锯切巷道22在半导体管芯4的在管芯接纳表面3以上的高度h1与封料20的上表面的在管芯接纳表面3以上的高度h2的中间的位置处终止。在键合线12用于制作半导体管芯4与载体之间的连接的情况下，锯切巷道22的深度d可以是使得锯切巷道22在键合线12的在管芯接纳表面3以上的高度h3与在封料20的在管芯接纳表面3以上的高度h2的中间的位置处终止。
注意，每个锯切巷道22的深度d为使得锯切巷道22不完全延伸通过封料20、而是仅部分地延伸到封料20的在管芯接纳表面3以上的上表面。
如图8所示，锯切22将载体从载体坯料2中分离出来。锯切22可以例如隔离载体坯料中的相邻载体，使得测试成为可能。如将在下文中关于图9所描述的，这个测试可以在待在下文中关于图10所描述的封装器件的最终单体化之前执行。
如图9中可见，在锯切发生之后，虽然载体已分离开，但每个封装体仍被封料20的干预剩余部分21保持在一起。便利地，封料20的这些剩余部分21可以提供机械稳定性以将封装体保持在位，同时多个步骤可以在如待在下文中关于图10所描述的最终单体化之前执行。这些步骤可以例如包括测试每个封装体。为了执行这个测试，包括例如一个或多个探针42的一个或多个探头40可以与每个封装体的载体的底面5接触。因为封装体被封料20的剩余部分21保持在位，因此探头40为了测试给定的封装体而需要被定位的位置是可预测且稳定的。
在一些示例中，测试可以例如在不同温度下重复一次或多次。
在一个示例中，第一测试阶段可以在锯切了锯切巷道22之后执行。然后，可选地，可以执行焊料回流。在倒装芯片型封装体的情况下，所述焊料回流可以涉及加热载体及其相关联的半导体管芯4的安排以便熔化例如在键合线尾部的任何焊料连接和/或涉及位于半导体管芯4的主表面与每个载体的管芯接纳表面3之间的焊球。
然后，可以在焊料回流步骤之后重复上述使用探头40和探针42的测试步骤，以便验证半导体管芯4与每个载体之间的连接。注意，封料20的剩余部分21还可以在焊料回流工艺期间保持各个封装体固定在一起，使得在如上文中所描述的那样执行再测试时，探头40的探针42需要放置的位置仍是可预测且稳定的。
在执行了上文中关于图9所描述的可选步骤之后，可以如图10所示的那样完成封装半导体器件的单体化。在这个步骤中，将封料从封料20的上表面移除，至少直到达到锯切巷道22的上述位置(在如从底面5测得的深度d处)。以此方式，可以完全移除封料20的上述剩余部分21，从而将每个封装器件与其在阵列中相邻的封装器件最终分离开。
将封料20从封料20的顶部移除可以通过研磨来实现。例如，如图10所示，研磨带50可以附接到载体的底面，并且然后，研磨工具(如图10所示的可旋转研磨器60)可以用于跨封料20的顶部进行扫描，从而将封料20从顶表面移除到给定深度。
设想的是，从封料20的顶表面移除的封料20的量可以恰好与上述锯切巷道22的深度d相对应，使得相比于严格需要的封料，不再需要移除更多封料。然而，为了提供公差度和/或为了允许根据设计要求来选择成品器件中封料20的整体高度，可以移除更多封料，使得封料20的移除在到达锯切巷道22的底部之后继续到某个深度。无论如何，设想成品封装半导体器件中的封料20的最终高度在每个载体的管芯接纳表面3以上、高于半导体管芯4的高度，使得甚至在单体化期间移除封料之后，半导体管芯4仍被封料20覆盖。而且，如图10所示，在使用键合线12的情况下，设想的是，封料20的最终高度应该也覆盖键合线12。
在从封料20的顶表面移除封料(如图10所示)之后，可以移除研磨带50。还设想此后可以执行诸如激光标记和带绕以及卷取等步骤。设想封装器件的阵列可以再带绕到切割带上以便执行这些步骤(例如，以避免需要在带绕和卷取期间翻转每个封装管芯)。还设想图10所示的研磨带50可用于实现这一情况。
因此，已经描述了一种制作多个封装半导体器件的方法。所述方法包括：提供载体坯料，所述载体坯料具有管芯接纳表面和底面。所述方法还包括：将多个半导体管芯安装到所述管芯接纳表面上，其中所述管芯延伸到在所述管芯接纳表面以上的第一高度。所述方法进一步包括：将封料布置在所述管芯接纳表面，其中所述封料的上表面位于所述第一高度以上。所述方法还包括：通过锯切到所述底面中穿过所述载体坯料且部分地穿过所述坯料到在所述第一高度与所述上表面中间的深度来进行单体化以形成所述多个封装半导体器件，其中所述锯切将所述载体坯料分为多个载体；以及从所述封料的所述上表面移除封料，至少直到达到所述锯切深度。
虽然已经描述了本公开的特定实施例，但是将了解，可以在权利要求书的范围内做出多个修改/添加和/或替代。

Claims (6)

1.一种制造多个封装半导体器件的方法，所述方法包括：
提供载体坯料，所述载体坯料具有管芯接纳表面和底面；
将多个半导体管芯安装到所述载体坯料的所述管芯接纳表面上，其中所述管芯延伸到在所述管芯接纳表面以上的第一高度；
将封料布置在所述管芯接纳表面上，其中所述封料的上表面位于所述第一高度以上，由此所述封料覆盖所述多个半导体管芯；以及
通过以下方式使所述载体坯料和封料单体化以形成所述多个封装半导体器件：
锯切到所述载体的所述底面中，以便锯切穿过所述载体坯料且部分地锯切穿过所述封料到在所述第一高度与所述封料的所述上表面中间的锯切深度，其中所述锯切将所述载体坯料分为多个载体，每个载体具有与所述载体坯料的所述底面相对应的底面以及与所述载体坯料的所述管芯接纳表面相对应的管芯接纳表面，其中每个载体的所述管芯接纳表面将所述半导体管芯中的至少一个半导体管芯安装在其上；以及
从所述封料的上表面移除封料，至少直到达到所述锯切深度；
使电探头接触到所述载体中的至少一些载体的所述底面以便在执行焊料回流之后再测试所述封装半导体器件。
2.根据权利要求1所述的方法，其中所述使电探头接触到所述载体中的至少一些载体的所述底面在所述锯切之后且在所述从所述封料的上表面移除封料之前执行。
3.根据权利要求1所述的方法，其中所述再测试所述封装半导体器件在所述从所述封料的上表面移除封料之前执行。
4.根据任一前述权利要求所述的方法，包括在将所述封料布置在所述管芯接纳表面上之前，电力地使用引线键合来将每个半导体管芯连接到所述载体坯料。
5.根据权利要求1至3中任一项所述的方法，其中每个半导体管芯具有其上提供有一个或多个电连接的主表面，并且其中将所述半导体管芯安装到所述管芯接纳表面上包括通过将每个管芯的所述主表面上的所述电连接电连接到所述管芯接纳表面来将每个管芯的所述主表面附接到所述管芯接纳表面。
6.一种通过任一前述权利要求所述的方法制造的封装半导体器件。
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