CN203707108U - 一种硅基圆片级扇出封装结构 - Google Patents

一种硅基圆片级扇出封装结构 Download PDF

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CN203707108U
CN203707108U CN201320864641.2U CN201320864641U CN203707108U CN 203707108 U CN203707108 U CN 203707108U CN 201320864641 U CN201320864641 U CN 201320864641U CN 203707108 U CN203707108 U CN 203707108U
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metal
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陈海杰
陈栋
张黎
陈锦辉
赖志明
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Jiangyin Changdian Advanced Packaging Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20Structure, shape, material or disposition of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors

Abstract

本实用新型涉及一种硅基圆片级扇出封装结构,属于半导体芯片封装技术领域。其包括硅基本体(110)和带有若干个电极(210)的IC芯片(200),每一电极(210)上设置若干个金属柱/金属块(300),IC芯片(200)的另一面通过贴片胶(700)与硅基本体(110)连接;塑封层将IC芯片(200)、金属柱/金属块(300)和贴片胶(700)封装于其内,金属柱/金属块(300)的端面露出塑封层,并在其端面设置布线走向独立的再布线金属层(500),相邻的再布线金属层(500)向电极(210)外侧延伸,并在再布线金属层(500)的终端的表面设置焊球凸点(600)。本实用新型的封装结构能够与后段工艺的引脚节距相匹配,同时能够使晶圆厂发挥其先进的制程工艺将IC芯片的尺寸做得更小。

Description

一种硅基圆片级扇出封装结构
技术领域
本实用新型涉及一种硅基圆片级扇出封装结构,属于半导体芯片封装技术领域。 
背景技术
电子封装已经成为半导体行业极其重要的一个组成部分。近几十年封装技术的发展,各个封装工厂均将封装的小型化和高密度作为主要的研发方向,一大批先进的封装方法和封装结构被应用于量产。 
作为广泛应用的单颗芯片封装技术,传统封装目前已经逐渐呈现出封装效率低下和成本持续攀升的弊端。圆片级封装作为一种新型的封装方式,因能够较大地减少芯片封装尺寸,而被业界广泛采用。但是,任何封装工艺都必须与后续的SMT和PCB工艺相对应,而圆片级WLCSP封装的引脚节距一般为0.4mm或0.5mm,这就使得晶圆厂必须考虑与后段工艺的匹配问题。圆片级WLCSP封装的引脚节距的限制,不利于晶圆厂利用其先进的制程工艺将芯片的尺寸做得更小。 
发明内容
本实用新型的目的在于克服上述不足,提供一种能够与后段工艺的引脚节距相匹配、同时能够使晶圆厂发挥其先进的制程工艺将芯片的尺寸做得更小的硅基圆片级扇出封装结构。 
本实用新型的目的是这样实现的: 
本实用新型一种硅基圆片级扇出封装结构,包括硅基本体和带有若干个电极的IC芯片,每一所述电极上设置若干个金属柱/金属块,所述IC芯片的另一面通过贴片胶与硅基本体连接;还包括塑封层,所述塑封层将IC芯片、IC芯片上的金属柱/金属块和贴片胶封装于其内,所述金属柱/金属块的端面露出塑封层,并在其端面设置布线走向独立的再布线金属层,相邻的所述再布线金属层向电极外侧延伸,并在所述再布线金属层的终端的表面设置焊球凸点,所述IC芯片的电极的节距L2小于焊球凸点的节距L1。
可选地,所述焊球凸点呈阵列排布。 
可选地,所述焊球凸点的节距L1为0.4mm或0.5mm。 
可选地,所述再布线金属层的布线间距不小于20μm。 
可选地,所述再布线金属层的布线间距为25~30μm。 
可选地,所述硅基本体呈平板状。 
可选地,所述金属柱/金属块的横截面呈圆形或多边形。 
可选地,所述封装结构内设置两颗或两颗以上的所述IC芯片,所述IC芯片的型号相同或不同。 
本实用新型一种硅基圆片级扇出封装结构,所述IC芯片设置于硅基本体的单侧,所述塑封层将硅基本体上的IC芯片、金属柱/金属块和贴片胶封装于其内。 
或者所述IC芯片设置于硅基本体的上下两侧,所述塑封层分别将IC芯片、金属柱/金属块和贴片胶封装于其内,所述塑封层材质相同或不同。 
本实用新型的IC芯片通过贴片胶与平板状的硅基本体连接,并将IC芯片、金属柱/金属块以及贴片胶塑封于塑封层内,通过再布线金属层的向电极外侧延伸的走向,扩展IC芯片的电极的节距,形成硅基圆片级扇出封装结构。IC芯片通过再布线金属层及焊球凸点与外界连接,硅基本体和塑封层给予IC芯片足够的强度、硬度保护。 
本实用新型的有益效果是:
1、本实用新型通过IC芯片的电极、金属柱/金属块和再布线金属层构成的圆片级扇出结构可以使更小尺寸的芯片实现与后段工艺的引脚节距相匹配,以使晶圆厂发挥其先进的制程工艺将芯片的尺寸做得更小;
2、本实用新型将引脚(即IC芯片的电极)间距更小的数个芯片整合在一个封装体中,通过IC芯片的电极、金属柱/金属块和再布线金属层构成的圆片级扇出结构可以实现现有0.4mm和0.5mm的常规节距进行封装,实现系统级封装,满足高密度和小尺寸封装的要求,符合集成电路的封装趋势。
附图说明
图1为本实用新型一种硅基圆片级扇出封装结构的实施例一的示意图; 
图2为图1中IC芯片的电极与焊球凸点的扇出位置关系的示意图;
图3为本实用新型一种硅基圆片级扇出封装结构的实施例二的示意图;
图4为本实用新型一种硅基圆片级扇出封装结构的实施例三的示意图。
图中: 
硅基本体110
IC芯片200
电极210
金属柱/金属块300
塑封层410、420
再布线金属层500
介电层510
金属层520
焊球凸点600
贴片胶700
金属保护层800。
具体实施方式
参见图1和图2,本实用新型一种硅基圆片级扇出封装结构,包括呈平板状的硅基本体110和带有若干个电极210的IC芯片200,电极210的节距为L2,节距L2因IC芯片200的大小或电极210的个数而异。IC芯片200的非电极面通过贴片胶700与硅基本体110连接,贴片胶700为一种改性的高分子材料的键合胶,同时起绝缘作用,可根据工艺需求进行灵活的调配,满足点胶、喷胶等设备需求。IC芯片200的每个电极210上设置若干个金属柱/金属块300,金属柱/金属块300的横截面呈圆形或矩形、六边形等多边形,其材质为铜、铜/镍复合层等导电性能良好的金属。采用塑封工艺,将IC芯片200、IC芯片200上的金属柱/金属块300和贴片胶700塑封起来,形成塑封层410,金属柱/金属块300的端面露出塑封层410,并在其端面设置布线走向独立的再布线金属层500。相邻的再布线金属层500向电极210外侧延伸,在再布线金属层500的终端的表面设置焊球凸点600,焊球凸点600呈阵列排布,并且焊球凸点600的节距L1为固定值,L1一般为0.4mm或0.5mm。晶圆厂利用其先进的制程工艺可以将IC芯片200的尺寸做得越来越小,电极210的节距L2越来越小,同时再布线金属层500的布线间距可以做到不小于20μm,优选地,再布线金属层500的布线间距可以为25μm~30μm,从而实现在IC芯片200很小的情况下,IC芯片200的电极210的节距L2小于焊球凸点600的节距L1时同样完成与后段SMT或PCB工艺的匹配。再布线金属层500由介电层和单层金属层构成或者由多层介电层和多层叠加且相邻层之间彼此电性连接的金属层构成。图中以一层介电层510和一层金属层520为例。多层金属层的材质为金属铜或钛/铜、钛钨/铜、铝/镍/金、铝/镍/钯/金等多层金属结构。介电层的材质为具有光刻特征的树脂,根据各层的树脂成分以及工艺的实际需要调整UV系数。该封装结构可以通过焊球凸点600与外部基板或者PCB等电路板实现连接。 
实施例二,参见图3 
该实施例二与实施例一具有类似的封装结构,两者的区别在于:设置于硅基本体110的IC芯片200的个数为两颗或两颗以上。IC芯片200设置于硅基本体110的一侧,呈二维平面排布,IC芯片200型号可以相同,也可以是不同,以实现封装结构的功能的多样化。该封装结构可以通过焊球凸点600与外部基板或者PCB等电路板实现连接。
实施例三,参见图4 
该实施例中,设置于硅基本体110的IC芯片200的个数为两颗或两颗以上,IC芯片200型号相同,也可以是不同。其与实施例二的封装结构区别在于: IC芯片200可以设置于硅基本体110的上下两侧,实现多芯片的三维空间排布,以提高封装的集成度。IC芯片200对称分布或交错分布,塑封层410、420分别将IC芯片200、IC芯片200上的金属柱/金属块300和贴片胶700封装于其内,金属柱/金属块300露出塑封层420,并设置镍、金等金属保护层800,在需要与外界连接时,可以打开金属保护层800。该封装结构通过焊球凸点600或金属柱/金属块300与外部基板或者PCB等电路板实现连接。
在实施例二和实施例三中,IC芯片200的面阵分布使得实现的封装结构可以多信号输入/输出;连接IC芯片200与再布线金属层500的金属柱/金属块300有效地提高了封装结构的整体散热效率,保证了多个IC芯片200能够同时正常工作,适于应用在对信号和导热要求较高的封装领域。而电极210、金属柱/金属块300和再布线金属层500构成的扇出封装结构,可以使晶圆厂利用其先进的制程工艺将IC芯片200的尺寸做得更小,有助于提高封装的集成度。 
本实用新型的硅基圆片级扇出封装方法形成的硅基圆片级扇出封装结构不限于上述实施例,任何本领域技术人员在不脱离本实用新型的精神和范围内,依据本实用新型的技术实质对以上实施例所作的任何修改、等同变化及修饰,均落入本实用新型权利要求所界定的保护范围内。 

Claims (10)

1.一种硅基圆片级扇出封装结构,包括硅基本体(110)和带有若干个电极(210)的IC芯片(200), 
其特征在于:每一所述电极(210)上设置若干个金属柱/金属块(300),所述IC芯片(200)的另一面通过贴片胶(700)与硅基本体(110)连接;还包括塑封层,所述塑封层将IC芯片(200)、IC芯片(200)上的金属柱/金属块(300)和贴片胶(700)封装于其内,所述金属柱/金属块(300)的端面露出塑封层,并在其端面设置布线走向独立的再布线金属层(500),相邻的所述再布线金属层(500)向电极(210)外侧延伸,并在所述再布线金属层(500)的终端的表面设置焊球凸点(600),所述IC芯片(200)的电极(210)的节距L2小于焊球凸点(600)的节距L1。
2.根据权利要求1所述的硅基圆片级扇出封装结构,其特征在于:所述焊球凸点(600)呈阵列排布。
3.根据权利要求2所述的硅基圆片级扇出封装结构,其特征在于:所述焊球凸点(600)的节距L1为0.4mm或0.5mm。
4.根据权利要求1所述的硅基圆片级扇出封装结构,其特征在于:所述再布线金属层(500)的布线间距不小于20μm。
5.根据权利要求4所述的硅基圆片级扇出封装结构,其特征在于:所述再布线金属层(500)的布线间距为25~30μm。
6.根据权利要求1所述的硅基圆片级扇出封装结构,其特征在于:所述硅基本体(110)呈平板状。
7.根据权利要求1所述的硅基圆片级扇出封装结构,其特征在于:所述金属柱/金属块(300)的横截面呈圆形或多边形。
8.根据权利要求1至7中任一项所述的硅基圆片级扇出封装结构,其特征在于:所述封装结构内设置两颗或两颗以上的所述IC芯片(200),所述IC芯片(200)的型号相同或不同。
9.根据权利要求8所述的硅基圆片级扇出封装结构,其特征在于:所述IC芯片(200)设置于硅基本体(110)的单侧,所述塑封层(410)将硅基本体(110)上的IC芯片(200)、金属柱/金属块(300)和贴片胶(700)封装于其内。
10.根据权利要求8所述的硅基圆片级扇出封装结构,其特征在于:所述IC芯片(200)设置于硅基本体(110)的上下两侧,所述塑封层(410、420)分别将IC芯片(200)、金属柱/金属块(300)和贴片胶(700)封装于其内,所述塑封层(410、420)材质相同或不同。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681371A (zh) * 2013-12-26 2014-03-26 江阴长电先进封装有限公司 一种硅基圆片级扇出封装方法及其封装结构
CN106024749A (zh) * 2015-03-31 2016-10-12 意法半导体有限公司 具有柱和凸块结构的半导体封装体
CN114649286A (zh) * 2022-05-19 2022-06-21 甬矽电子(宁波)股份有限公司 扇出型封装结构和扇出型封装方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103681371A (zh) * 2013-12-26 2014-03-26 江阴长电先进封装有限公司 一种硅基圆片级扇出封装方法及其封装结构
CN106024749A (zh) * 2015-03-31 2016-10-12 意法半导体有限公司 具有柱和凸块结构的半导体封装体
CN114649286A (zh) * 2022-05-19 2022-06-21 甬矽电子(宁波)股份有限公司 扇出型封装结构和扇出型封装方法

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