KR101111425B1 - 팬아웃 타입의 반도체 패키지 - Google Patents
팬아웃 타입의 반도체 패키지 Download PDFInfo
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- KR101111425B1 KR101111425B1 KR1020090133711A KR20090133711A KR101111425B1 KR 101111425 B1 KR101111425 B1 KR 101111425B1 KR 1020090133711 A KR1020090133711 A KR 1020090133711A KR 20090133711 A KR20090133711 A KR 20090133711A KR 101111425 B1 KR101111425 B1 KR 101111425B1
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- interposer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73209—Bump and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
Claims (9)
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- 상부가 개방된 다수의 포켓(12)이 형성된 몰드 인터포져(10)와;상기 몰드 인터포져(10)의 포켓(12)내에 부착되는 하부칩(29)과;상기 하부칩(29)상에 플립칩(34)을 매개로 도전 가능하게 적층되는 상부칩(28)과;상기 하부칩(29)을 포함하는 몰드 인터포져(10)의 상면에 걸쳐 몰딩되어 상부칩(28)의 상면과 동일선상을 이루는 절연체(16)와;상기 하부칩(29)의 저면 테두리에 형성된 본딩패드에서 절연체(16)의 상면까지 관통 형성되는 전도성 비아홀(36)과;상기 전도성 비아홀(36)로부터 연장되어, 상기 상부칩(28)의 상면 및 절연체(16)의 상면에 걸쳐 소정의 배열을 이루는 재배선층(20)과;상기 재배선층(20)의 외부접속패드(26)에 융착되는 입출력단자(18);를 포함하여 구성된 것을 특징으로 하는 팬아웃 타입의 반도체 패키지.
- 청구항 8에 있어서,상기 재배선층(20)을 포함하는 절연체(16) 및 상부칩(28)의 상면에 도포되는 동시에 입출력단자(18)의 절반 높이 이상을 감싸주는 에폭시층(40)를 더 포함하는 것을 특징으로 하는 팬아웃 타입의 반도체 패키지.
Priority Applications (1)
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KR1020090133711A KR101111425B1 (ko) | 2009-12-30 | 2009-12-30 | 팬아웃 타입의 반도체 패키지 |
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KR1020090133711A KR101111425B1 (ko) | 2009-12-30 | 2009-12-30 | 팬아웃 타입의 반도체 패키지 |
Publications (2)
Publication Number | Publication Date |
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KR20110077213A KR20110077213A (ko) | 2011-07-07 |
KR101111425B1 true KR101111425B1 (ko) | 2012-02-16 |
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KR1020090133711A KR101111425B1 (ko) | 2009-12-30 | 2009-12-30 | 팬아웃 타입의 반도체 패키지 |
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Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8829676B2 (en) | 2011-06-28 | 2014-09-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure for wafer level package |
KR101469799B1 (ko) * | 2012-03-30 | 2014-12-05 | 주식회사 네패스 | 반도체 패키지의 제조 방법 |
KR101478508B1 (ko) * | 2012-08-09 | 2015-01-02 | 앰코 테크놀로지 코리아 주식회사 | 웨이퍼 레벨의 팬 아웃 패키지 및 그 제조 방법 |
KR101445766B1 (ko) * | 2012-10-30 | 2014-10-01 | 주식회사 네패스 | 반도체 패키지 및 그 제조 방법 |
US9368460B2 (en) | 2013-03-15 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out interconnect structure and method for forming same |
KR101605600B1 (ko) | 2014-02-04 | 2016-03-22 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스 |
KR20160083385A (ko) | 2014-12-30 | 2016-07-12 | 주식회사 네패스 | 반도체 패키지 및 그 제조방법 |
US11024604B2 (en) | 2019-08-10 | 2021-06-01 | Amkor Technology Singapore Holding Pte. Ltd. | Semiconductor devices and methods of manufacturing semiconductor devices |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US20050224968A1 (en) * | 2004-03-31 | 2005-10-13 | Aptos Corporation | Wafer level mounting frame for ball grid array packaging, and method of making and using the same |
US7011988B2 (en) * | 2002-11-08 | 2006-03-14 | Flipchip International, Llc | Build-up structures with multi-angle vias for Chip to Chip interconnects and optical bussing |
KR20090089579A (ko) * | 2008-02-19 | 2009-08-24 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 그 제조 방법 |
KR20090120215A (ko) * | 2008-05-19 | 2009-11-24 | 삼성전기주식회사 | 웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법 |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7011988B2 (en) * | 2002-11-08 | 2006-03-14 | Flipchip International, Llc | Build-up structures with multi-angle vias for Chip to Chip interconnects and optical bussing |
US20050224968A1 (en) * | 2004-03-31 | 2005-10-13 | Aptos Corporation | Wafer level mounting frame for ball grid array packaging, and method of making and using the same |
KR20090089579A (ko) * | 2008-02-19 | 2009-08-24 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 그 제조 방법 |
KR20090120215A (ko) * | 2008-05-19 | 2009-11-24 | 삼성전기주식회사 | 웨이퍼 레벨 칩 스케일 패키지 및 그 제조방법 |
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