CN104576424A - 通过预先在芯片上制备凸点实现扇出型晶圆封装的方法 - Google Patents

通过预先在芯片上制备凸点实现扇出型晶圆封装的方法 Download PDF

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CN104576424A
CN104576424A CN201410759030.0A CN201410759030A CN104576424A CN 104576424 A CN104576424 A CN 104576424A CN 201410759030 A CN201410759030 A CN 201410759030A CN 104576424 A CN104576424 A CN 104576424A
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汪民
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National Center for Advanced Packaging Co Ltd
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Abstract

本发明公开了一种通过预先在芯片上制备凸点实现扇出型晶圆封装的方法，该方法在芯片上预先制备凸点，方法可以是电镀金属（比如Cu）,也可以采用更简易和高效率的晶圆芯片焊盘引线键合制备凸点方法实现（材料可以是Cu,Ag合金等金属）；通过芯片凸点快速和简易的实现芯片电路外延；在已通过凸点实现外延电路的基础上结合基板图形化方法实现芯片输出电路的再布局，最后植球从而得到FOWLP封装结构。再布局的过程省去了半导体工艺中影印工艺，该实现方案在封装效率及最终成本方面具有一定优势。

Description

通过预先在芯片上制备凸点实现扇出型晶圆封装的方法
技术领域
本发明涉及一种通过预先在芯片上制备凸点实现扇出型晶圆封装（FOWLP）的方法，属于集成电路芯片封装技术领域。
背景技术
1）    Infineon eWLP封装。如图1所示，芯片1正面朝下（Face Down）方式通过胶膜贴到载体上，然后进行塑封（见塑封体10），塑封完成后将胶膜及载体去除漏出芯片1正面。后续通过RDL (Redistribution Line：再布线)工艺（见再布线层11）完成如图1所示的FOWLP（扇出型晶圆封装）封装结构。从工艺过程看，其主要的不足之处在于需要使用到半导体Photolithography(影印工艺)，相应设备及工艺成本比较高。
2) Freescale RCP封装结构。实现过程参见
http://www.freescale.com/webapp/sps/site/overview.jsp?code=ASIC_LV3_PACKAGING_RCP。其主要的不足之处在于需要完成在基板预留孔中实现电镀并引出电路焊盘，电镀成本及工艺过程比较困难。
3) TSMC FOWLP封装结构。参见CN102856279A专利的TSMC封装结构图6。其实现方法为在芯片上通过电镀方法得到凸点，然后将芯片正面朝上贴到载体上，并进行塑封；塑封完成后通过打磨漏出凸点；后续进行RDL工艺完成焊盘布局并植球得到图示结构。从工艺过程看，即使用到了芯片上凸点，但还是部分工序需要使用影印工艺，相对成本比较高。
发明内容
本发明的目的是克服现有技术中存在的不足，提供一种通过预先在芯片上制备凸点实现扇出型晶圆封装的方法，高效低成本的实现FOWLP封装结构。
按照本发明提供的技术方案，所述的通过预先在芯片上制备凸点实现扇出型晶圆封装的方法包括以下步骤：
（1）在芯片焊盘上制备导电凸点；
（2）将芯片按照设计好的位置以正面朝上的方式通过胶带贴到下方载体上；
（3）使用引线上流体材料包封芯片及引线，根据芯片凸点高度控制引线上流体材料的厚度，使得凸点只能露出少许头部；
（4）在引线上流体材料表面采用电镀工艺沉积导电金属层，在导电金属层表面通过磨平工艺进行磨平处理；或者预先切除凸点头部后磨平，再电镀沉积导电金属层；
（5）采用刻蚀方法，进行相应于芯片电路的导电图案制备，并通过线路再布局得到相应于整个表面的分布；
（6）在导电图案表面凃覆保护层材料，再通过显影刻蚀方法得到对应焊盘的保护层开口；
（7）最后在保护层开口位置的焊盘上进行植球，制作出焊球，得到整个扇出型晶圆封装结构。
其中，步骤（1）所述制作导电凸点的方法可以采用电镀金属或采用引线键合工艺制备bump凸点方法。导电凸点的材料可以是Cu，或Ag合金等金属。
步骤（2）所述载体可以是金属或硅等材质，形状可以为圆片或平板形式。
步骤（6）所述保护层材料可以使用光敏树脂，或基板表面使用的油墨。
步骤（7）所述植球前，可以先在焊盘表面电镀底层材料，增加焊球在焊盘上结合的牢靠度。
在步骤（7）的基础上，根据需求可以去除底部的胶带和载体的部分或全部，以达到更薄的封装厚度。
本发明的优点是：本发明在芯片上预先制备凸点，方法可以是电镀金属（比如Cu）,也可以采用更简易和高效率的晶圆芯片焊盘引线键合制备凸点方法实现（材料可以是Cu, Ag alloy等金属）；通过芯片凸点快速和简易的实现芯片电路外延；在已通过凸点实现外延电路的基础上结合基板图形化方法实现芯片输出电路的再布局，最后植球从而得到FOWLP 封装结构。再布局的过程省去了半导体工艺中影印工艺，实现方案在封装效率及最终成本方面具有一定优势。
附图说明
图1是现有技术结构图。
图2是在芯片上制作凸点的示意图。
图3是将芯片正面朝上贴到载体上的示意图。
图4是用FOW材料包封芯片及引线只露出凸点头部的示意图。
图5是在FOW材料表面制作平整的导电金属层的示意图。
图6是制作基板表面导电图案的示意图。
图7是涂覆保护层材料并制作开口的示意图。
图8是在焊盘处完成植球得到的FOWLP封装结构。
具体实施方式
下面结合附图和实施例对本发明作进一步说明。
整个 FOWLP 封装的实现过程如下：
（1）如图2所示，在芯片1焊盘上制备导电凸点2，方法可以电镀金属或采用Wire Bond（引线键合）工艺制备Bump凸点方法，材料可以是Cu, Ag合金等金属。
（2）如图3所示，将芯片1按照设计好的位置以正面朝上（Face up）的方式，通过胶带（tape）3贴到载体4上。载体4可以是金属或硅（Silicon）等材质，形状可以圆片或平板（Panel）形式。
（3）如图4所示，使用FOW (Flow on Wire，引线上流体)特性膜直接进行压合包封芯片及引线（wire）；也可以采用FOW Paste（胶）进行涂敷填充；工艺过程根据芯片凸点2高度控制FOW材料5的厚度，使得凸点2只能露出少许高度的头部（如10um ），如图4所示。
（4）在FOW材料5表面采用电镀工艺沉积导电金属层6，比如Cu，在导电金属层6表面通过磨平工艺进行磨平处理，也可以预先切除凸点2头部后磨平，再电镀沉积导电金属层6，最后得到图5所示结构。
（5）采用刻蚀方法，如基板图形（Substrate Pattern）刻蚀工艺进行相应于芯片电路的导电图案7制备，并通过线路再布局得到相应于整个表面的分布，如图6所示。
（6）在导电图案7表面凃覆保护层8材料，材料可以使用光敏树脂，或基板表面使用的油墨，通过显影刻蚀方法得到对应焊盘的保护层开口，如图7所示。
（7）最后在保护层8开口位置进行植球，得到图8所示的FOWLP封装结构。为增加焊球9在焊盘上结合的牢靠度，可以在焊盘表面电镀底层材料，如Ni/Au层。在图8基础上，根据需求可以去除底部的胶带（Tape）和载体（Carrier）,以确保更薄的FOWLP封装厚度。
本发明实现了一种FOWLP封装结构；通过预先在芯片上制备的凸点实现电路I/O引出，方法简易，效率高，成本低；引出的芯片电路I/O应用基板图形制备工艺方法进行再布局，最后在再布局的焊盘上进行植球从而得到 FOWLP 封装结构，具有低成本的优势。

Claims (8)

1.通过预先在芯片上制备凸点实现扇出型晶圆封装的方法，其特征是，包括以下步骤：
（1）在芯片（1）焊盘上制备导电凸点（2）；
（2）将芯片（1）按照设计好的位置以正面朝上的方式通过胶带（3）贴到下方载体（4）上；
（3）使用引线上流体材料（5）包封芯片（1）及引线，根据芯片凸点（2）高度控制引线上流体材料（5）的厚度，使得凸点（2）只能露出少许头部；
（4）在引线上流体材料（5）表面采用电镀工艺沉积导电金属层（6），在导电金属层（6）表面通过磨平工艺进行磨平处理；或者预先切除凸点（2）头部后磨平，再电镀沉积导电金属层（6）；
（5）采用刻蚀方法，进行相应于芯片电路的导电图案（7）制备，并通过线路再布局得到相应于整个表面的分布；
（6）在导电图案（7）表面凃覆保护层（8）材料，再通过显影刻蚀方法得到对应焊盘的保护层开口；
（7）最后在保护层（8）开口位置的焊盘上进行植球，制作出焊球（9），得到整个扇出型晶圆封装结构。
2.如权利要求1所述的通过预先在芯片上制备凸点实现扇出型晶圆封装的方法，其特征是，步骤（1）所述制作导电凸点（2）的方法采用电镀金属或采用引线键合工艺制备凸点方法。
3.如权利要求1，2所述的通过预先在芯片上制备凸点实现扇出型晶圆封装的方法，其特征是，所述导电凸点（2）的材料为Cu，或Ag合金。
4.如权利要求1所述的通过预先在芯片上制备凸点实现扇出型晶圆封装的方法，其特征是，步骤（2）所述载体（4）是金属或硅材质，形状为圆片或平板形式。
5.如权利要求1所述的通过预先在芯片上制备凸点实现扇出型晶圆封装的方法，其特征是，步骤（3）所述凸点（2）头部露出引线上流体材料（5）的高度为  ～  。
6.如权利要求1所述的通过预先在芯片上制备凸点实现扇出型晶圆封装的方法，其特征是，步骤（6）所述保护层（8）材料使用光敏树脂，或基板表面使用的油墨。
7.如权利要求1所述的通过预先在芯片上制备凸点实现扇出型晶圆封装的方法，其特征是，步骤（7）所述植球前，先在焊盘表面电镀底层材料，增加焊球（9）在焊盘上结合的牢靠度。
8.如权利要求1所述的通过预先在芯片上制备凸点实现扇出型晶圆封装的方法，其特征是，在步骤（7）的基础上，去除底部的胶带（3）和载体（4）的部分或全部，以达到更薄的封装厚度。
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