CN107644848A - 封装结构及其制造方法 - Google Patents

封装结构及其制造方法 Download PDF

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Publication number
CN107644848A
CN107644848A CN201610894159.1A CN201610894159A CN107644848A CN 107644848 A CN107644848 A CN 107644848A CN 201610894159 A CN201610894159 A CN 201610894159A CN 107644848 A CN107644848 A CN 107644848A
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China
Prior art keywords
chip
interlayer hole
wiring layer
layer
moulding bodies
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CN201610894159.1A
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Inventor
黄立贤
苏安治
陈宪伟
曾华伟
王若梅
杨天中
卢贯中
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Publication of CN107644848A publication Critical patent/CN107644848A/zh
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Abstract

本发明实施例提供一种封装结构及其制造方法。封装结构包括第一芯片、第二芯片、封装模塑体、第一布线层、第一贯穿介层孔、第二贯穿介层孔、电磁干扰屏蔽层及导电部件。第一芯片包覆在封装模塑体内。第二芯片设置在封装模塑体上。第一布线层位在封装模塑体和导电部件之间并电性连接第一芯片及第二芯片。封装模塑体位于第二芯片和第一布线层之间。第一贯穿介层孔及第二贯穿介层孔包覆在封装模塑体内并电性连接第一布线层。第二贯穿介层孔位于第一芯片和第一贯穿介层孔之间。电磁干扰屏蔽层设置在第二芯片上并与第一贯穿介层孔接触。导电部件连接第一布线层。

Description

封装结构及其制造方法
技术领域
本发明实施例是有关于一种封装结构及其制造方法。
背景技术
通常可以在整片半导体芯片上制造半导体组件和集成电路。在芯片层级工艺中，针对芯片中的芯片进行加工处理，并且可以将芯片与其他的半导体组件一起封装。目前各方正努力开发适用于芯片级封装的不同技术。
发明内容
本发明实施例提供封装结构，能有效地改善半导体封装结构电性性能。
根据本发明实施例，封装结构包括至少一第一芯片、至少一第二芯片、封装模塑体、第一布线层、至少一第一贯穿介层孔、第二贯穿介层孔、电磁干扰屏蔽层及导电部件。第一芯片被包覆在封装模塑体内。第二芯片设置在封装模塑体上。第一布线层设置在封装模塑体上并电性连接至第一芯片以及第二芯片，其中封装模塑体位于第二芯片和第一布线层之间。第一贯穿介层孔被包覆在封装模塑体内并电性连接至第一布线层。第二贯穿介层孔被包覆在封装模塑体内并电性连接至第一布线层，且第二贯穿介层孔位于第一芯片和第一贯穿介层孔之间。电磁干扰屏蔽层设置在第二芯片上并与第一贯穿介层孔接触。导电部件连接第一布线层，其中第一布线层位于导电部件和封装模塑体之间。
根据本发明实施例，封装结构包括第一芯片、封装模塑体、第一布线层、至少一贯穿孔、第二芯片、封装材料、电磁干扰屏蔽层及导电部件。第一芯片被包覆在封装模塑体内。第一布线层设置在封装模塑体上并电性连接至第一芯片。贯穿孔被包覆在封装模塑体内并电性连接至第一布线层。第二芯片设置在封装模塑体上并电性连接至第一布线层，其中封装模塑体位于第二芯片和第一布线层之间。封装材料设置在封装模塑体上并且位于第二芯片和封装模塑体之间，其中封装材料具有暴露出贯穿孔的至少一接触窗。电磁干扰屏蔽层设置在第二芯片上并通过接触窗与贯穿孔接触。导电部件连接第一布线层，其中第一布线层位于导电部件和封装模塑体之间。
根据本发明实施例，封装结构的制造方法包括设置第一芯片于载体上。形成至少一第一贯穿介层孔于载体上。密封第一芯片以及第一贯穿介层孔于封装模塑体内。形成第一布线层于封装模塑体上，其中第一布线层电性连结至第一芯片以及第一贯穿介层孔。设置导电部件于第一布线层上，其中第一布线层位于封装模塑体和导电部件之间。从第一芯片以及第一贯穿介层孔移除载体。设置第二芯片于封装模塑体上，其中第二芯片电性连结至第一布线层，且封装模塑体位于第二芯片和第一布线层之间。设置封装材料于第二芯片以及封装模塑体上。对封装材料进行激光钻孔，以形成暴露出贯穿孔的至少一接触窗。形成电磁干扰屏蔽层于第二芯片上，其中电磁干扰屏蔽层通过接触窗与第一贯穿介层孔接触。
为让本发明的上述揭露特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1到图12为依据一些本发明实施例的封装结构的制造方法的各种阶段所形成之封装结构之剖面示意图。
图13到图17为依据一些本发明实施例的封装结构的局部放大的俯视示意图，以说明第一贯穿介层孔的各种设置态样。
附图标号说明
10：(半导体)封装结构、封装结构；
112：载体；
114：脱黏层；
116：图案化介电层；
116a：开口；
121：第一贯穿介层孔；
122：第二贯穿介层孔；
130：第一芯片；
130a：有源面；
130b：接垫；
130c：钝化层；
130d：导电柱；
130e：保护层；
140：封装模塑体；
150：第一布线层；
152：聚合物介电层；
154：金属层；
160：导电部件；
180：第二芯片；
190：连接结构；
200：封装材料；
202：接触窗；
210：电磁干扰屏蔽层；
AK：校准标记；
CL：切割线；
DA：芯片附着膜；
SE：密封结构。
具体实施方式
以下揭露内容提供用于实施所提供的目标的不同特征的许多不同实施例或实例。以下所描述的构件及设置的具体实例是为了以简化的方式传达本发明实施例为目的。当然，这些仅仅为实例而非用以限制。举例来说，于以下描述中，在第一特征上方或在第一特征上形成第二特征可包括第二特征与第一特征形成为直接接触的实施例，且亦可包括第二特征与第一特征之间可形成有额外特征使得第二特征与第一特征可不直接接触的实施例。此外，本发明实施例中可使用相同的组件符号及/或字母来指代相同或类似的部件。组件符号的重复使用是为了简单及清楚起见，且并不表示所欲讨论的各个实施例及/或设置本身之间的关系。
另外，为了易于描述附图中所绘示的一个构件或特征与另一组件或特征的关系，本文中可使用例如“在...下”、“在...下方”、“下部”、“在…上”、“在…上方”、“上部”及类似术语的空间相对术语。除了附图中所绘示的定向之外，所述空间相对术语意欲涵盖组件在使用或操作时的不同定向。设备可被另外定向(旋转90度或在其他定向)，而本文所用的空间相对术语相应地作出解释。
此外，文中所述用语诸如“第一”、“第二”等，其在文中的使用主要是便于描述图中所示相似或不同的组件或特征，并且可以根据叙述出现的顺序或上下文的描述而相互调换使用。
图1到图12为依据一些本发明实施例的封装结构的制造方法的各种阶段所形成之封装结构之剖面示意图。在实施例中所描述的制造方法为晶片级封装工艺的一部分。在一些实施例中，图示绘出两个芯片以代表该晶片的多个芯片，并且绘示出一个或多个(半导体)封装结构10来代表依照所述封装结构的制造方法而获得的多个封装结构。在一些实施例中，如图1至图11所示，虚线表示两个(半导体)封装结构10之间的切割线CL。
请参照图1，在一些实施例中，提供一载体112，而载体112可以是玻璃载体或可适用于封装结构的制造方法之任何合适的载体。在一些实施例中，载体112其上设置涂覆有一个脱黏层114，脱黏层114的材质可以是能够使载体112与位于其上的各层或芯片轻易脱离的任意材质。接着，形成一图案化介电层116于载体112上。在一些实施例中，形成图案化介电层116的方法例如是先在载体112上方形成一层介电材料层(未绘示)后，对图案化上述介电材料层以形成具有多个开口116a的图案化介电层116，其中开口116a暴露出脱黏层114。图案化介电层116可由适当的制作技术所形成，例如旋涂法、叠层法、沉积法或类似方法。在一些实施例中，图案化介电层116例如是聚合物层，其中聚合物层可以包括聚醯亚胺(polyimide)、聚苯并恶唑(polybenzoxazole；PBO)、苯环丁烯(benzocyclobutene；BCB)、味之素堆积膜(Ajinomoto Buildup film；ABF)、阻焊(Solder Resist；SR)膜或类似物。
参照图2，在一些实施例中，形成一个或多个第一贯穿介层孔(throughinterlayer vias)121于载体112上，且第一贯穿介层孔121与被开口116a暴露出的脱黏层114直接接触。在一些实施例中，第一贯穿介层孔121例如是贯穿整合扇出通孔(throughintegrated fan-out(InFO)vias)。在某些实施例中，于形成第一贯穿介层孔121的步骤中，同时形成一个或多个第二贯穿介层孔122于载体112上，且第二贯穿介层孔122与被开口116a暴露出的脱黏层114直接接触。在一些实施例中，二贯穿介层孔122例如是贯穿整合扇出通孔(through integrated fan-out(InFO)vias)。在某些实施例中，部分的第一贯穿介层孔121以及部分的第二贯穿介层孔122对应地位于图案化介电层116的开口116a内。在一些实施例中，第二贯穿介层孔122位于第一芯片(未绘示)和第一贯穿介层孔121之间，且第一贯穿介层孔121设置成靠近切割线CL但非直接位于切割线CL上并位于第二贯穿介层孔122和切割线CL之间。在一些实施例中，第一贯穿介层孔121与第二贯穿介层孔122可以是通过光刻蚀刻、电镀、去光刻胶工艺(photoresist stripping processes)或其他合适的方法来形成。依据一个实施例，第一贯穿介层孔121与第二贯穿介层孔122的形成可以通过形成一光掩模图案(未绘示)覆盖在具有开口的图案化介电层上方，且所述开口暴露未被图案化介电层覆盖的脱黏层114；以电镀或沉积法形成金属材料来填充所述开口而形成第一贯穿介层孔121与第二贯穿介层孔122；然后移除所述光掩模图案。然，本发明实施例不限于此。在某些实施例中，第二贯穿介层孔122可以在第一贯穿介层孔121的形成之后或之前；且第一贯穿介层孔121与第二贯穿介层孔122的材质可以是相同或不同，例如包括金属材料(如铜、铜合金或类似物)。
请参照图3，在一些实施例中，提供至少一个第一芯片130，且将第一芯片130设置于图案化介电层116上并位于载体112的上方。在某些实施例中，第一芯片130通过芯片附着膜DA贴合图案化介电层116，其中芯片附着膜DA设置在第一芯片130和图案化介电层116之间，可以更好的地粘合第一芯片130至图案化介电层116上。如图3所示，第一芯片130的背表面是和第一芯片110是稳固地贴合于图案化介电层116。在一些实施例中，第一芯片130包括有源面130a、设置于有源面130a上的多个接垫130b、覆盖有源面130a以及部分接垫130b的钝化层130c、多个导电柱130d以及保护层130e。接垫130b是部分地被钝化层130c所暴露出来，导电柱130d设置于接垫130上并电性连结至接垫130，保护层130e覆盖钝化层130c并暴露出导电柱130d。举例来说，导电柱130d例如是铜柱(copper pillars)、铜合金柱或其他合适的金属柱。在一些实施例中，保护层130e例如是苯恶唑(polybenzoxazole，PBO)层、聚醯亚胺层或其他合适的聚合物层。在其他实施例中，保护层130e例如是由无机材料组成，如：氧化硅、氮化硅、氮氧化硅或其他合适的介电材料。在一些实施例中，第一芯片130可以选自于应用专用集成电路(application-specific integrated circuit；ASIC)芯片、模拟芯片(例如无线射频芯片(wireless and radio frequency chips)，诸如：2.4GHz射频芯片、5GHz射频芯片、2.4GHz/5GHz的射频芯片或60GHz射频芯片)、数位芯片(例如60GHz基带芯片)、整合式无源元件(integrated passive devices，IPDs)、电压调节器芯片、传感器芯片、存储器芯片或类似物。
请参照图4，在一些实施例中，将第一芯片130、第一贯穿介层孔121及第二贯穿介层孔122密封于封装模塑体140内。在一些实施例中，封装模塑体140至少填充于第一芯片130、第一贯穿介层孔121及第二贯穿介层孔122之间的空间，并覆盖图案化介电层116。在一些实施例中，封装模塑体140形成于第一芯片130、第一贯穿介层孔121及第二贯穿介层孔122上，并覆盖第一芯片130的导电柱130d与保护层130e、第一贯穿介层孔121及第二贯穿介层孔122。
请参照图5，在一些实施例中，对封装模塑体140、第一贯穿介层孔121及第二贯穿介层孔122进行平坦化工艺，直到露出第一贯穿介层孔121、第二贯穿介层孔122以及第一芯片130的导电柱130d与保护层130e的顶部被暴露出来。在一些实施例中，如图5所示，在平坦化之后，封装模塑体140、第一贯穿介层孔121、第二贯穿介层孔122以及第一芯片130的导电柱130d与保护层130e的顶部为大致等高(齐平)。依据一个实施例，封装模塑体140的顶部、第一贯穿介层孔121的顶部、第二贯穿介层孔122的顶部以及第一芯片130的导电柱130d与保护层130e的顶部为基本上共平面。在一些实施例中，封装模塑体140的材质包括例如环氧树脂、酚醛树脂或含硅树脂。在一些实施例中，封装模塑体140、第一贯穿介层孔121及第二贯穿介层孔122之平坦化是利用研磨工艺或化学机械抛光(CMP)工艺。在研磨工艺后，一道清洁步骤可选择性地被执行，例如是用于清洁或移除任何由研磨工艺所产生的残留物。然而，本发明实施例不限于此，上述的平坦化工艺亦可以通过其他合适的方式来执行。
请参照图6，在一些实施例中，于在封装模塑体140、第一贯穿介层孔121、第二贯穿介层孔122以及第一芯片130上形成第一布线层150。在一些实施例中，第一布线层150通过导电柱130d与接垫130b与第一芯片130电性连接，并电性连接至第一贯穿介层孔121以及第二贯穿介层孔122。第一布线层150的形成包括依序地且交替地形成多层聚合物介电层152以及多层金属层154。在某些实施例中，如图6所示，金属层154可以夹在聚合物介电层152之间，但是金属层154中的最顶层的顶表面会露出来，而金属层154中的最底层连接到第一贯穿介层孔121、第二贯穿介层孔122以及第一芯片130的导电柱130d。在一些实施例中，金属层154的材质包括例如铝、钛、铜、镍、钨和/或其合金，且金属层154例如是以电镀法或沉积法形成。在一些实施例中，聚合物电介质层152的材质包括例如聚醯亚胺、环氧树脂、丙烯酸树脂、酚醛树脂、苯并环丁烯(BCB)、聚苯并恶唑(PBO)或任何其他合适的聚合物类介电材料。
在某些实施例中，如图6所示，第一布线层150中靠近切割线CL但非直接位于切割线CL上的部分金属层154构成密封结构SE。在一些实施例中，密封结构SE至少重叠于第一贯穿介层孔121，且密封结构SE是电性绝缘于第一芯片130、第一贯穿介层孔121、第二贯穿介层孔122以及第一布线层150的其他部分。藉由密封结构SE的存在，使得封装结构10具有更好的承载强度。
请参照图7，将导电部件160设置于第一布线层150中最顶层的金属层154上。在一些实施例中，第一布线层150位于封装模塑体140和导电部件160之间。在一些实施例中，设置导电部件160之前，先将焊膏或焊剂(未绘示)施加于最顶层的金属层154上，便于导电部件160能够更好地固定在最顶层的金属层154上。在一些实施例中，设置于第一布线层150中最顶层的金属层154上的导电部件160例如是焊球(solder balls)或球阵列封装球(BGAballs)，而位于导电部件160下方的部分最顶层的金属层154则作为UBM层。在一些实施例中，透过第一布线层150，部分的导电部件160电性连接至第一芯片130，且部分的导电部件160电性连接至第一贯穿介层孔121及/或第二贯穿介层孔122。
请参照图8，在一些实施例中，将载体112与第一芯片130、第一贯穿介层孔121及第二贯穿介层孔122脱胶分离开来。藉由脱黏层114，封装结构10可轻易与载体112分离开来，且第一贯穿介层孔121及第二贯穿介层孔122的底表面被暴露出来。
请参考图9，在一些实施例中，从载体112分离开来的封装结构10可被翻转(上下颠倒)，并将至少一个第二芯片180设置于其上。在某些实施例中，第二芯片180通过连接结构190而设置于第二贯穿介层孔122的底表面上。在一些实施例中，在将导电部件160设置于第一布线层150上以及载体112脱胶分离之后，第二芯片180接合第二贯穿介层孔122。在一些实施例中，第二芯片180通过连接结构190以覆晶接合技术贴合至第二贯穿介层孔122，连接结构190位于第二芯片180与第二贯穿介层孔122之间。在一些实施例中，图案化介电层116位于第一芯片130和第二芯片180之间。在一些实施例中，连接结构190例如是凸块(bumps)或焊料球(solder balls)。在某些实施例中，封装材料200至少填充于第二芯片180、连接结构190以及图案化介电层116之间的空间，并覆盖图案化介电层116。在一些实施例中，封装材料200设置于封装模塑体140之上并位于第二芯片180与封装模塑体140之间。依照一个实施例，封装材料200例如是以底胶填充(underfill dispensing)或其他合适的方法形成。在一些实施例中，封装材料200与封装模塑体140的材质可以是相同或不同，本发明实施例不限于此。连接结构190接触第二芯片180以及第二贯穿介层孔122，其中第二芯片180透过连接结构190及第二贯穿介层孔122而电性连接第一布线层150。
在一些实施例中，第二芯片180例如是利用覆晶接合技术接合(flip chipbonding technology)至第二贯穿介层孔122的存储器芯片。在一些实施例中，上述存储器芯片例如是动态随机(存取)存储器(dynamic random access memories，DRAM)，然不限于此。在一些实施例中，通过连接结构190、第二贯穿介层孔122、第一布线层150、导电柱130d以及接垫130b，第二芯片180电性连接至第一芯片130。在一些实施例中，通过连接结构190、第二贯穿介层孔122以及第一布线层150，第二芯片180电性连接至导电部件160。在一些实施例中，通过连接结构190以及第一布线层150，第二芯片180电性连接至第一贯穿介层孔121及/或第二贯穿介层孔122。
请参照图10，在一些实施例中，图案化封装材料200以形成接触窗202。在某些实施例中，接触窗202暴露出第一贯穿介层孔121的底表面。依据一个实施例，封装材料200的图案化工艺例如是激光钻孔或其他合适的方法。
请参照图11，在一些实施例中，进行切单工艺(singulation process，或是切割工艺)沿着切割线CL(图中虚线)切割封装结构整体(至少切透穿过封装材料200、第一布线层150、封装模塑体140)而得到个别且分离的封装结构10。依照一个实施例，切单/切割工艺包含机械式切锯工艺或激光切割芯片工艺。
请参照图12，在一些实施例中，将电磁干扰屏蔽层210设置于第二芯片180上并电性连结至第一贯穿介层孔121；至此步骤，本发明实施例的(半导体)封装结构10已完成。在某些实施例中，电磁干扰屏蔽层210以共形式方式(conformal manner)来覆盖第二芯片180、封装材料200、第一贯穿介层孔121以及封装模塑体140与第一布线层150的侧表面。电磁干扰屏蔽层210至少覆盖被封装材料200暴露出来的第一贯穿介层孔121并至少填充部分的接触窗202。在某些实施例中，电磁干扰屏蔽层210是完全填满接触窗202。在一些实施例中，电磁干扰屏蔽层210通过接触窗202与第一贯穿介层孔121的底表面接触，其中当电磁干扰屏蔽层210通过第一贯穿介层孔121、第一布线层150以及对应连接至接地平面(groundplane(未绘示))的导电组件160而电性接地(electrically grounded)时，第一贯穿介层孔121为接地通孔。在一些实施例中，电磁干扰屏蔽层210可以由具导电性的导电材料组成。电磁干扰屏蔽层210的材质例如是铜、镍、铜铁合金、铜镍合金、银等材质，但不限于此。在一些实施例中，电磁干扰屏蔽层210可通过电解电镀(electrolytic plating)、无电电镀(electroless plating)、溅射(sputtering)、化学气相沉积法(chemical vapordeposition，CVD)、物理气相沉积法(physical vapor deposition，PVD)或其他合适的方法来制作。由于磁性材料或导电材料所制成之阻隔物可阻挡电场或磁场，因此电磁干扰屏蔽层210可用以降低或抑制一个空间中的电磁场。在一些实施例中的电磁干扰屏蔽层210可以降低诸如无线电波、电磁场及静电场间的耦合。
请再参照图12，在一些实施例中，封装结构10包括第一贯穿介层孔121、第二贯穿介层孔122、第一芯片130、封装模塑体140、第一布线层150、导电部件160、第二芯片180及电磁干扰屏蔽层210。在一些实施例中，第一贯穿介层孔121、第二贯穿介层孔122以及第一芯片130设置于图案化介电层116上并且密封于封装模塑体140内，其中第二贯穿介层孔122位于第一贯穿介层孔121和第一芯片130之间。在一些实施例中，封装模塑体140覆盖图案化介电层116且至少填充于第一贯穿介层孔121、第二贯穿介层孔122及第一芯片130之间的空间。在某些实施例中，第二芯片180设置于封装模塑体140上并通过连接结构190以覆晶接合技术贴合至第二贯穿介层孔122。在某些实施例中，连接结构190与第二芯片180以及第二贯穿介层孔122相接触。在某些实施例中，图案化介电层116位于第一芯片130和第二芯片180之间并具有多个开口116a，其中部分的第一贯穿介层孔121以及部分的第二贯穿介层孔122分别地位于对应的开口116a内。在某些实施例中，密封材料200设置于第二芯片180和密封胶体140之间并覆盖图案化介电层116，其中密封材料200至少填充于第二芯片180、连接结构190以及图案化介电层116之间的空间并具有暴露出第一贯穿介层孔121的接触窗202。在一些实施例中，电磁干扰屏蔽层210以共形式方式(conformal manner)覆盖第二芯片180、封装材料200、第一贯穿介层孔121以及封装模塑体140与第一布线层150的侧表面。由于接触窗202的存在，电磁干扰屏蔽层210藉由直接接触第一贯穿介层孔121，而电性连接至第一贯穿介层孔121。在一些实施例中，第二芯片180堆叠在第一芯片130上方，且位于密封胶体140和电磁干扰屏蔽层210之间。电磁干扰屏蔽层210接触密封胶体140、密封材料200及第一布线层150。密封材料200设置于第二芯片180和密封胶体140之间，电磁干扰屏蔽层210贯穿密封材料200而与第一贯穿介层孔121接触。
在一些实施例中，第一布线层150设置在封装模塑体140上。在某些实施例中，第一布线层150通过第一芯片130的导电柱130d与接垫130b与第一芯片130电性连接；且第一布线层150亦电性连接至第一贯穿介层孔121以及第二贯穿介层孔122。在一些实施例中，导电部件160连接第一布线层150，其中第一布线层150位于导电部件160和封装模塑体140之间。在某些实施例中，部分的导电部件160透过第一布线层150、导电柱130d及接垫130b电性连接至第一芯片130。在某些实施例中，部分的导电部件160透过第一布线层150电性连接至第一贯穿介层孔121及/或第二贯穿介层孔122。在某些实施例中，部分的导电部件160透过第一布线层150、第二贯穿介层孔122及连接结构190电性连接至第二芯片180。在某些实施例中，连接结构190与第二芯片180以及第二贯穿介层孔122接触。在一些实施例中，当电磁干扰屏蔽层210通过第一贯穿介层孔121、第一布线层150以及对应连接至接地平面(groundplane(未绘示))的导电组件160而电性接地(electrically grounded)时，第一贯穿介层孔121为接地通孔。藉由磁性材料或导电材料所制成之阻隔物来阻挡电场或磁场，电磁干扰屏蔽层210可用以降低或抑制一个空间中的电磁场。在一些实施例中的电磁干扰屏蔽层210可以降低诸如无线电波、电磁场及静电场间的耦合。
在某些实施例中，密封结构SE位于第一布线层150中靠近封装结构10的边界区域，且至少重叠于第一贯穿介层孔121。密封结构SE是电性绝缘于第一芯片130、第一贯穿介层孔121、第二贯穿介层孔122、第一布线层150及电磁干扰屏蔽层210。藉由密封结构SE的存在，使得封装结构10具有更好的承载强度。依据一个实施例，第一芯片130例如是2.4GHz射频芯片、5GHz射频芯片、2.4GHz/5GHz的射频芯片，而第二芯片180例如是动态随机(存取)存储器；然，本发明实施例不限于此。
图13到图17为依据一些本发明实施例的封装结构的局部放大的俯视示意图，以说明第一贯穿介层孔(TIVs)的各种设置态样。第一贯穿介层孔121具有多种的设置位置，并可依需求来调整。在一些实施例中，第二贯穿介层孔122位于第一芯片130和第一贯穿介层孔121之间。举例来说，封装结构10的第一贯穿介层孔121以及第二贯穿介层孔122排列成一个矩阵形态，其中每一行(row)具有一个第一贯穿介层孔121与两个第二贯穿介层孔122(如图13所示)；或者，第一行具有一个第一贯穿介层孔121与两个第二贯穿介层孔122，第二行仅具有两个第二贯穿介层孔122，其中上述第一行与上述第二行沿着列(column)方向交错排列成一个矩阵形态(如图14所示)；又或者，将具有“第一行-第二行-第二行”的重复单元沿着列方向排列成一个矩阵形态，其中上述第一行具有一个第一贯穿介层孔121与两个第二贯穿介层孔122，且上述第二行具有两个第二贯穿介层孔122(如图15所示)。在一些实施例中，一个封装结构10亦可以仅具有一个第一贯穿介层孔121，其中上述第一贯穿介层孔121可以形成在晶片(wafer)中原始设计用于位置校准的校准标记AK上(如图16所示)。在一些实施例中，除了在校准标记AK上形成第一贯穿介层孔121外，第一贯穿介层孔121更可以与第二贯穿介层孔122排列成一个矩阵形态(如图17所示)。由于上述的第一贯穿介层孔121的设置位置，本发明实施例的(半导体)封装结构10无需额外的空间来形成第一贯穿介层孔121，因此可确保较小的形状因子(form factor)并减少制作成本。
本发明实施例提供一种封装结构，包括至少一第一芯片、至少一第二芯片、封装模塑体、第一布线层、至少一第一贯穿介层孔、第二贯穿介层孔、电磁干扰屏蔽层及导电部件。第一芯片被包覆在封装模塑体内。第二芯片设置在封装模塑体上。第一布线层设置在封装模塑体上并电性连接至第一芯片以及第二芯片，其中封装模塑体位于第二芯片与第一布线层之间。第一贯穿介层孔被包覆在封装模塑体内并电性连接至第一布线层。第二贯穿介层孔被包覆在封装模塑体内并电性连接至第一布线层，且第二贯穿介层孔位于第一芯片与第一贯穿介层孔之间。电磁干扰屏蔽层设置在第二芯片上并与第一贯穿介层孔接触。导电部件连接第一布线层，其中第一布线层位于导电部件与封装模塑体之间。
本发明实施例提供一种封装结构，包括第一芯片、封装模塑体、第一布线层、至少一贯穿孔、第二芯片、封装材料、电磁干扰屏蔽层及导电部件。第一芯片被包覆在封装模塑体内。第一布线层设置在封装模塑体上并电性连接至第一芯片。贯穿孔被包覆在封装模塑体内并电性连接至第一布线层。第二芯片设置在封装模塑体上并电性连接至第一布线层，其中封装模塑体位于第二芯片与第一布线层之间。封装材料设置在封装模塑体上并且位于第二芯片与封装模塑体之间，其中封装材料具有暴露出贯穿孔的至少一接触窗。电磁干扰屏蔽层设置在第二芯片上并通过接触窗与贯穿孔接触。导电部件连接第一布线层，其中第一布线层位于导电部件与封装模塑体之间。
本发明实施例提供一种封装结构的制造方法。设置第一芯片于载体上。形成至少一第一贯穿介层孔于载体上。密封第一芯片以及第一贯穿介层孔于封装模塑体内。形成第一布线层于封装模塑体上，其中第一布线层电性连结至第一芯片以及第一贯穿介层孔。设置导电部件于第一布线层上，其中第一布线层位于封装模塑体与导电部件之间。从第一芯片以及第一贯穿介层孔移除载体。设置第二芯片于封装模塑体上，其中第二芯片电性连结至第一布线层，且封装模塑体位于第二芯片与第一布线层之间。设置封装材料于第二芯片以及封装模塑体上。对封装材料进行激光钻孔，以形成暴露出贯穿孔的至少一接触窗。形成电磁干扰屏蔽层于第二芯片上，其中电磁干扰屏蔽层通过接触窗与第一贯穿介层孔接触。
最后应说明的是：以上各实施例仅用以说明本发明实施例的技术方案，而非对其限制；尽管参照前述各实施例对本发明实施例进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。

Claims (1)

1.一种封装结构，其特征在于，包括：
至少一第一芯片，包覆在封装模塑体内；
至少一第二芯片，设置在所述封装模塑体上；
第一布线层，设置在所述封装模塑体上并电性连接至所述第一芯片以及所述第二芯片，其中所述封装模塑体位于所述第二芯片与所述第一布线层之间；
至少一第一贯穿介层孔，包覆在所述封装模塑体内并电性连接至所述第一布线层；
第二贯穿介层孔，包覆在所述封装模塑体内并电性连接至所述第一布线层，其中所述第二贯穿介层孔位于所述第一芯片与所述第一贯穿介层孔之间；
电磁干扰屏蔽层，设置在所述第二芯片上并与所述第一贯穿介层孔相接触；以及
导电部件，连接所述第一布线层，其中所述第一布线层位于所述导电部件与所述封装模塑体之间。
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