CN113327899A - 倒装芯片封装单元及封装方法 - Google Patents

倒装芯片封装单元及封装方法 Download PDF

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Publication number
CN113327899A
CN113327899A CN202110435879.2A CN202110435879A CN113327899A CN 113327899 A CN113327899 A CN 113327899A CN 202110435879 A CN202110435879 A CN 202110435879A CN 113327899 A CN113327899 A CN 113327899A
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Prior art keywords
wafer
integrated circuit
protective layer
flip chip
chip package
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CN202110435879.2A
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Inventor
蒲应江
蒋航
郭秀宏
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Chengdu Monolithic Power Systems Co Ltd
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Chengdu Monolithic Power Systems Co Ltd
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Priority to CN202110435879.2A priority Critical patent/CN113327899A/zh
Publication of CN113327899A publication Critical patent/CN113327899A/zh
Priority to US17/717,257 priority patent/US20220344175A1/en
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Abstract

提出了一种倒装芯片封装单元及制作倒装芯片封装单元的封装方法。该倒装芯片封装单元可以包括：集成电路晶片，具有晶片第一表面和与该晶片第一表面相对的晶片第二表面，该晶片第一表面上制作有多个金属柱；绕线基板，其具有基板第一表面和与该基板第一表面相对的基板第二表面，所述集成电路晶片的晶片第一表面朝向该基板第二表面焊接于该绕线基板上；底部填充材料，填充该集成电路晶片的晶片第一表面与所述基板第二表面之间的间隙；以及导热保护层，至少包裹覆盖并直接接触该集成电路晶片的晶片第二表面及晶片侧面的一部分，有助于提升集成电路晶片的散热性能，同时该导热保护层可以对集成电路晶片起到较好的保护作用。

Description

倒装芯片封装单元及封装方法
技术领域
本公开的实施例涉及集成电路，特别地，涉及用于倒装芯片的封装结构及封装方法。
背景技术
将制作有集成电路的晶片进行倒装封装是集成电路封装方式的一种。对于需要处理较大功率的集成电路晶片，散热性能是需要重点考虑的一个设计指标。目前将集成电路晶片进行倒装封装时，采用将晶片用塑封材料包裹后再将晶片背面的塑封材料去除以将晶片背面裸露的方式以改善散热效果，然而晶片背面裸露则在储存或运输过程中受损的风险增加。
发明内容
本公开一方面提出了一种倒装芯片封装单元，可以包括：集成电路晶片，具有晶片第一表面和与该晶片第一表面相对的晶片第二表面，该晶片第一表面上制作有多个金属柱；绕线基板，其具有基板第一表面和与该基板第一表面相对的基板第二表面，所述集成电路晶片的晶片第一表面朝向该基板第二表面焊接于该绕线基板上；底部填充材料，填充该集成电路晶片的晶片第一表面与所述基板第二表面之间的间隙；以及导热保护层，至少包裹覆盖并直接接触该集成电路晶片的晶片第二表面及晶片侧面的一部分。
本公开的另一方面提出了一种制作倒装芯片封装单元的晶圆级封装方法，可以包括：步骤S1，提供制作有多个集成电路单元的晶圆，该晶圆的第一表面上针对每个集成电路单元制作有多个金属柱；步骤S2,将对该晶圆进行切割，将各集成电路单元相互分离，形成多个相互分立的集成电路晶片，每个集成电路晶片的晶片第一表面上具有多个金属柱，每个集成电路单元还具有与其晶片第一表面相对的晶片第二表面；步骤S3，提供绕线基板，其具有基板第一表面和与该基板第一表面相对的第二表面,将每个集成电路晶片的晶片第一表面朝向所述基板第二表面焊接于该绕线基板上，相邻的两个集成电路晶片之间间隔第一横向距离；步骤S4，在每个集成电路晶片的晶片第一表面与所述基板第二表面之间的间隙注入底部填充材料形成每个集成电路晶片的底部填充材料；以及步骤S5，在每个集成电路晶片的晶片第二表面和晶片侧面上制作导热保护层，使该导热保护层至少包裹覆盖并直接接触每个集成电路晶片的晶片第二表面及其晶片侧面的一部分。
本公开各实施例的倒装芯片封装单元采用导热保护层不仅制作工艺简单易实现、成本可控，而且可以提升集成电路晶片的散热性能，同时该导热保护层可以对集成电路晶片起到较好的保护作用。
附图说明
下面的附图有助于更好地理解接下来对本公开实施例的描述。为简明起见，不同附图中相同或类似的组件或结构采用相同的附图标记。
图1示意出了根据本公开一实施例的倒装芯片封装单元100的局部纵向(Z轴方向)剖面图。
图2A至2F示意出了根据本公开一实施例的制作倒装芯片封装单元的晶圆级封装方法中部分阶段的剖面流程示意图。
具体实施方式
在下面对本公开的详细描述中，为了更好地理解本公开的实施例，描述了大量的电路、元件、方法等的具体细节。本领域技术人员将理解，即使缺少一些细节，本公开同样可以实施。为清晰明了地阐述本公开，一些为本领域技术人员所熟知的细节在此不再赘述。
图1示意出了根据本公开一实施例的倒装芯片封装单元100的局部纵向(Z轴方向)剖面图。图1可以看作是在相互垂直的X轴、Y轴和Z轴定义的垂直坐标系中示意出了该倒装芯片封装单元100在X-Y平面上的剖面图。如图1的示例，该倒装芯片封装单元100可以包括至少一个被封装于其中的集成电路晶片102，在图1示意的例子中的剖面图展现了包括一个集成电路晶片102。本领域的技术人员应该理解，在其它实施例中可以包括两个及以上的集成电路晶片102。不同实施例的封装结构100中所封装的集成电路芯晶片102的个数以及排布或堆叠方式可以不同，各集成电路晶片102的尺寸及所实现的电路功能可以相同也可以不同，根据各封装结构100所要实现的具体电路功能而定，本申请不做赘述。
每个集成电路晶片102可以包括制作有集成电路的衬底103。本领域的技术人员应该理解衬底103可以包括硅(Si)等半导体材料，锗硅(SiGe)等化合物半导体材料，或者绝缘体上硅(SOI)等其他形式的衬底。集成电路晶片102具有第一表面，例如可以被提及为正面(图1中标记为102T)，和与该第一表面102T相对的第二表面，例如可以被提及为背面(图1中标记为102B)。该第一表面102T上制作有多个金属柱(例如铜柱)105，可以用于将制作于衬底103中的集成电路的节点/端子引出，以便于耦接至集成电路晶片102外部的电路。
根据本公开的一个实施例，倒装芯片封装单元100可以进一步包括绕线基板107，具有第一表面107T和与该第一表面107T相对的第二表面107B,可以将每个集成电路晶片102的第一表面102T朝向该绕线基板107的第二表面107B焊接于该绕线基板107上。例如每个集成电路晶片102的多个金属柱105可以通过焊接材料106焊接于绕线基板107的第二表面107B上。该绕线基板107可以包括一层或多层层间介电层和再布线金属层，本公开不做赘述。比如，参考1示意的例子，对应于每个集成电路晶片102该绕线基板107可以包括电连接至所述多个金属柱105的再布线金属层(例如第一再布线金属层1072)。再布线金属层可以包括，例如第一再布线金属层1072，穿过第一层间介电层1071与该多个金属柱105互相电气连接。在一些实施例中，再布线金属层还可以进一步包括例如第二再布线金属层1074，穿过第二层间介电层1073与所述第一再布线金属层1072相互电气连接。在一些实施例中，再布线金属层还可以进一步包括例如第三再布线金属层1076，与所述第二再布线层1074电气连接。本领域的技术人员应该理解，第一层间介电层1071、第二层间介电层1073可以包含相同的介电材料，也可以包含不同的介电材料。
根据本公开的一个实施例，可以采用底部填充材料104填充每个集成电路晶片102的第一表面102T与绕线基板107之间的间隙。该底部填充材料104可以采用流动性、填充性和稳定性比传统塑封材料(例如：环氧树脂模塑料等请列举一两种传统塑封料)高的绝缘材料，例如NAMICS 8410-302、LOCTITE ECCOBOND UF 8830S等。在一个实施例中，该底部填充材料104仅填充集成电路晶片102的第一表面102T上的多个金属柱(例如铜柱)105(包括相应焊料106)之间的空隙以起到保护该多个金属柱105的作用。在一个实施例中，该底部填充材料104进一步纵向爬升至包裹每个集成电路晶片102的侧面102S的一部分。纵向指平行于Y轴的方向。因此，集成电路晶片102的侧面102S的大部分及其第二表面102B均未受该底部填充材料104包裹/覆盖，从而有助于更好地散热。在一个实施例中底部填充材料104自集成电路晶片102的两个侧面102S双侧地向外呈梯形状突出，底部填充材料104的侧壁104S与集成电路晶片102的侧面102S相交形成一角度α。在一个实施例中该角度α大于0度且小于90度。在一个实施例中该角度α大于0度且小于45度。在一个实施例中该角度α大于0度且小于等于30度。这样底部填充材料104不仅可以更好地起到保护该多个金属柱105的作用，而且可以更好地抓持、固定集成电路晶片102。
根据本公开的一个实施例，倒装芯片封装单元100可以进一步包括导热保护层101，至少包裹覆盖并直接接触集成电路晶片102的第二表面102B及其侧面102S的一部分。在一个实施例中，该导热保护层101可以覆盖并直接接触倒装芯片封装单元100的整个背面侧的表面(例如图1的例子中包括集成电路晶片102的第二表面102B及其侧面102S、底部填充材料104的被露出的侧壁104S和绕线基板107的第二表面107B的未被底部填充材料104覆盖的部分)。可以理解，对于倒装芯片封装单元100而言，绕线基板107的第二表面107B以及集成电路晶片102的背面102B所朝向(例如图1中用向上的箭头示意出这个朝向)的那一侧(图1中标记为100B)可以被提及为倒装芯片封装单元100的背面侧。
在一个实施例中，该导热保护层101可以包括导热率高于100W/m.K的材料薄膜，例如，在一个实施例中可以通过在倒装芯片封装单元100的整个背面侧的表面溅射导热率高于100W/m.K的材料(例如钛、铜、紫铜、SUS304等金属或合金材料)而形成。该通过溅射工艺形成的材料薄膜与倒装芯片封装单元100的整个背面侧的表面键合牢固，不易脱落，不仅可以提升集成电路晶片102的散热性能，还可以对集成电路晶片102起到较好的电磁干扰(EMI)保护和物理保护作用。在一个实施例中，该导热保护层包括导电种子层和覆盖该导电种子层的金属层。例如，在一个实施例中，该导热保护层101可以通过在倒装芯片封装单元100的整个背面侧的表面先溅射导电材料(例如钛、铜、紫铜、SUS304等金属或合金材料)而后再电镀金属材料而形成。在一个实施例中，该导热保护层101可以包括任何其它导热率高于1W/m.K的材料薄膜，例如石墨烯薄膜等等。在一个实施例中该导热保护层101的厚度在0.3μm～10μm的范围。在一个实施例中该导热保护层101的厚度在0.3μm～5μm的范围。在一个实施例中该导热保护层101的厚度在0.3μm～1μm的范围。在一个实施例中该导热保护层101的厚度在0.5μm～5μm的范围。在一个实施例中该导热保护层101的厚度在2μm～5μm的范围。在一个实施例中该导热保护层101的厚度在2μm～3μm的范围。在一个实施例中该导热保护层101的厚度在3μm～10μm的范围。
图2A至2F示意出了根据本公开一实施例的制作倒装芯片封装结构(例如以上根据图1所描述各实施例提及的倒装芯片封装单元100)的晶圆级封装方法中部分阶段的剖面流程示意图。
参考图2A的示意，在步骤S1，可以将制作有多个集成电路单元102的晶圆201置于载板201上。本领域的技术人员应该理解，载板201的形状、大小可以根据晶圆201的形状、大小、数量等合理选择，本申请不做限定。在图2A的例子中，以虚线示意出了各集成电路单元102之间的边界。针对每个集成电路单元102在晶圆201的第一表面201T上制作有多个金属柱(例如铜柱)105。
接下来参考图2B的示意，在步骤S2，对晶圆201进行切割，将各集成电路单元102相互分离，形成多个相互分立的集成电路晶片102，每个集成电路晶片102的第一表面102T(也可以提及为晶片正面)上制作有所述多个金属柱(例如铜柱)105。每个集成电路晶片102可以包括倒装芯片/晶片。每个集成电路晶片102还具有与其第一表面102T相对的第二表面102B(也可以提及为晶片背面)。
接下来参考图2C的示意，在步骤S3，去除载板201，提供绕线基板107，该绕线基板107具有第一表面107T和与该第一表面107T相对的第二表面107B,将每个集成电路晶片102的第一表面102T朝向该绕线基板107的第二表面107B焊接于该绕线基板107上。在一个实施例中，每相邻的两个集成电路晶片102之间间隔第一横向距离d1。横向指沿X轴方向的测量。该绕线基板107可以是预制的，且针对每个集成电路晶片102制作有与每个集成电路单元102相对应的已构图的多层层间介电层(例如返回参考图1例子示意的第一层间介电层1071、第二层间介电层1073)和多层再布线金属层(例如返回图1例子示意的第一再布线金属层1072、第二再布线金属层1074、第三再布线层1076等)。图2C的例子中虽未出该绕线基板107的更多细节，然本领域的技术人员应该可以参考图1的示意进行理解。
接下来参考图2D的示意，在步骤S4，在每个集成电路晶片102的第一表面102T与绕线基板107的第二表面107B之间的间隙注入底部填充材料104形成每个集成电路晶片102的底部填充材料。在一个实施例中，该底部填充材料104仅填充每个集成电路晶片102的第一表面102T与绕线基板107的第二表面107B之间的多个金属柱(例如铜柱)105(包括相应焊料)之间的空隙以起到保护该多个金属柱105的作用。在一个实施例中，注入底部填充材料的过程中使该底部填充材料104进一步纵向爬升至包裹每个集成电路晶片102的侧面102S的一部分。纵向指平行于Y轴的方向。在一个实施例中，每个集成电路晶片102的底部填充材料104自集成电路晶片102的两个侧面102S双侧地向外呈梯形状突出，每个集成电路晶片102的底部填充材料104的侧壁104S与该集成电路晶片102的侧面102S相交形成一角度α。在一个实施例中该角度α大于0度且小于90度。在一个实施例中该角度α大于0度且小于45度。在一个实施例中该角度α大于0度且小于等于30度。图2D以其中一个集成电路晶片102为例进行了示意。在一个实施例中，每个集成电路晶片102的底部填充材料104与与之相邻的集成电路晶片102的底部填充材料104之间间隔第二横向距离d2，该第二横向距离d2小于所述第一横向距离d1。该第二横向距离d2指沿与X轴方向平行的方向上测量两个相邻的底部填充材料104之间的最短距离。在一个实施例中，该第二横向距离d2在大于200μm小于等于5000μm的范围。在一个实施例中，该第二横向距离d2在大于200μm小于等于3000μm的范围。在一个实施例中，该第二横向距离d2在大于200μm小于等于1000μm的范围。在一个实施例中，所述第一横向距离d1与所述第二横向距离d2的差值(d1-d2)在大于200μm小于等于1000μm的范围。
接下来参考图2E的示意，在步骤S5，在每个集成电路晶片102的第二表面102B和侧面102S上制作导热保护层101使该导热保护层101至少包裹覆盖并直接接触每个集成电路晶片102的第二表面102B及其侧面102S的一部分。在一个实施例中，该导热保护层101可以覆盖并直接接触图2D步骤所制得的封装结构的整个背面侧的表面(例如包括每个集成电路晶片102的第二表面102B及侧面102S、每个集成电路晶片102的底部填充材料104的被露出的侧壁104S和绕线基板107的第二表面107B的未被底部填充材料104覆盖的部分)。在一个实施例中，该导热保护层101可以包括导热率高于100W/m.K的材料薄膜，例如，在一个实施例中可以通过在图2D步骤所制得的封装结构的整个背面侧的表面溅射导热率高于100W/m.K的材料(例如钛、铜、紫铜、SUS304等金属或合金材料)而形成。还例如，在一个实施例中，可以通过在在图2D步骤所制得的封装结构的整个背面侧的表面先溅射导热率高于100W/m.K的材料(例如钛、铜、紫铜、SUS304等金属或合金材料)而后再电镀金属材料而形成。可以理解，绕线基板107的第二表面107B以及集成电路晶片102的背面102B所朝向(例如图2D-2E中用向上的箭头示意出这个朝向)的那一侧(图1中标记为100B)可以被提及为封装结构的背面侧。在一个实施例中，该导热保护层101可以包括任何其它导热率高于1W/m.K的材料薄膜，例如石墨烯薄膜等等。在一个实施例中该导热保护层101的厚度在0.3μm～10μm的范围。在一个实施例中该导热保护层101的厚度在0.3μm～5μm的范围。在一个实施例中该导热保护层101的厚度在0.3μm～1μm的范围。在一个实施例中该导热保护层101的厚度在0.5μm～5μm的范围。在一个实施例中该导热保护层101的厚度在2μm～5μm的范围。在一个实施例中该导热保护层101的厚度在2μm～3μm的范围。在一个实施例中该导热保护层101的厚度在3μm～10μm的范围。
接下来参考图2F的示意，在步骤S6，采用切割工艺将图2E示意的封装结构分割成多个独立的倒装芯片封装单元100。每个倒装芯片封装单元100中可以包括至少一个集成电路晶片102，其更详细的结构描述可以参见图1各实施例的描述。本领域的技术人员应该理解在以上步骤S1～S6任两个步骤之间还可以根据制作工艺流程所需包括其它工艺步骤，本申请并不赘述。
本公开提供一种倒装芯片封装单元及相关的晶圆级封装方法，虽然详细介绍了本公开的一些实施例，然而应该理解，这些实施例仅用于示例性的说明，并不用于限定本公开的范围。其它可行的选择性实施例可以通过阅读本公开被本技术领域的普通技术人员所了解。

Claims (45)

1.一种倒装芯片封装单元，包括：
集成电路晶片，具有晶片第一表面和与该晶片第一表面相对的晶片第二表面，该晶片第一表面上制作有多个金属柱；
绕线基板，其具有基板第一表面和与该基板第一表面相对的基板第二表面，所述集成电路晶片的晶片第一表面朝向该基板第二表面焊接于该绕线基板上；
底部填充材料，填充该集成电路晶片的晶片第一表面与所述基板第二表面之间的间隙；以及
导热保护层，至少包裹覆盖并直接接触该集成电路晶片的晶片第二表面及晶片侧面的一部分。
2.如权利要求1所述的倒装芯片封装单元，其中所述底部填充材料填充该集成电路晶片的晶片第一表面上的多个金属柱之间的空隙。
3.如权利要求1所述的倒装芯片封装单元，其中所述底部填充材料进一步纵向爬升至包裹该集成电路晶片的晶片侧面的一部分。
4.如权利要求1所述的倒装芯片封装单元，其中所述底部填充材料自该集成电路晶片的双边晶片侧面双侧地向外呈梯形状突出，该底部填充材料的侧壁与该集成电路晶片的晶片侧面相交形成一角度。
5.如权利要求4所述的倒装芯片封装单元，其中所述角度大于0度且小于90度。
6.如权利要求4所述的倒装芯片封装单元，其中所述角度大于0度且小于45度。
7.如权利要求4所述的倒装芯片封装单元，其中所述角度大于0度且小于等于30度。
8.如权利要求1所述的倒装芯片封装单元，其中该导热保护层包括导热率高于100W/m.K的材料薄膜。
9.如权利要求1所述的倒装芯片封装单元，其中该导热保护层包括导热率高于1W/m.K的材料薄膜。
10.如权利要求1所述的倒装芯片封装单元，其中所述导热保护层覆盖并直接接触该倒装芯片封装单元的整个背面侧的表面，该倒装芯片封装单元的背面侧指所述基板第二表面以及所述晶片第二表面所朝向的那一侧。
11.如权利要求10所述的倒装芯片封装单元，其中该导热保护层通过在该倒装芯片封装单元的整个背面侧的表面溅射导热率高于100W/m.K的材料而形成。
12.如权利要求10所述的所述的倒装芯片封装单元，其中该导热保护层通过在该倒装芯片封装单元的整个背面侧的表面先溅射导电材料而后再电镀金属材料而形成。
13.如权利要求12所述的倒装芯片封装单元，其中，该导热保护层包括导电种子层和覆盖该导电种子层的金属层。
14.如权利要求1所述的倒装芯片封装单元，其中，所述导热保护层的厚度在0.3μm～10μm的范围。
15.如权利要求1所述的倒装芯片封装单元，其中，所述导热保护层的厚度在0.3μm～5μm的范围。
16.如权利要求1所述的倒装芯片封装单元，其中，所述导热保护层的厚度在0.3μm～1μm的范围。
17.如权利要求如权利要求1所述的倒装芯片封装单元，其中，所述导热保护层的厚度在0.5μm～5μm的范围。
18.如权利要求如权利要求1所述的倒装芯片封装单元，其中，所述导热保护层的厚度在2μm～5μm的范围。
19.如权利要求如权利要求1所述的倒装芯片封装单元，其中，所述导热保护层的厚度在2μm～3μm的范围。
20.如权利要求如权利要求1所述的倒装芯片封装单元，其中，所述导热保护层的厚度在3μm～10μm的范围。
21.一种制作倒装芯片封装单元的晶圆级封装方法，包括：
步骤S1，提供制作有多个集成电路单元的晶圆，该晶圆的第一表面上针对每个集成电路单元制作有多个金属柱；
步骤S2,将对该晶圆进行切割，将各集成电路单元相互分离，形成多个相互分立的集成电路晶片，每个集成电路晶片的晶片第一表面上具有多个金属柱，每个集成电路单元还具有与其晶片第一表面相对的晶片第二表面；
步骤S3，提供绕线基板，其具有基板第一表面和与该基板第一表面相对的第二表面,将每个集成电路晶片的晶片第一表面朝向所述基板第二表面焊接于该绕线基板上，相邻的两个集成电路晶片之间间隔第一横向距离；
步骤S4，在每个集成电路晶片的晶片第一表面与所述基板第二表面之间的间隙注入底部填充材料形成每个集成电路晶片的底部填充材料；以及
步骤S5，在每个集成电路晶片的晶片第二表面和晶片侧面上制作导热保护层，使该导热保护层至少包裹覆盖并直接接触每个集成电路晶片的晶片第二表面及其晶片侧面的一部分。
22.如权利要求21所述的封装方法，其中在步骤S4使每个集成电路晶片的底部填充材料填充该集成电路晶片的晶片第一表面上的多个金属柱之间的空隙。
23.如权利要求21所述的封装方法，其中在步骤S4使每个集成电路晶片的底部填充材料进一步纵向爬升至包裹每个集成电路晶片的侧面的一部分。
24.如权利要求22所述的封装方法，其中每个集成电路晶片的底部填充材料的侧壁与该集成电路晶片的晶片侧面相交形成一角度。
25.如权利要求24所述的封装方法，其中所述角度大于0度且小于90度。
26.如权利要求24所述的封装方法，其中所述角度大于0度且小于45度。
27.如权利要求24所述的封装方法，其中所述角度大于0度且小于等于30度。
28.如权利要求21所述的封装方法，其中在步骤S4使每个集成电路晶片的底部填充材料与与之相邻的集成电路晶片的底部填充材料之间间隔第二横向距离，该第二横向距离小于所述第一横向距离。
29.如权利要求28所述的封装方法，其中该第二横向距离在大于200μm小于等于5000μm的范围。
30.如权利要求28所述的封装方法，其中该第二横向距离d2在大于200μm小于等于3000μm的范围。
31.如权利要求28所述的封装方法，其中该第二横向距离d2在大于200μm小于等于1000μm的范围。
32.如权利要求28所述的封装方法，其中所述第一横向距离与所述第二横向距离的差值在大于200μm小于等于1000μm的范围。
33.如权利要求21所述的封装方法，其中该导热保护层包括导热率高于100W/m.K的材料薄膜。
34.如权利要求21所述的封装方法，其中该导热保护层包括导热率高于1W/m.K的材料薄膜。
35.如权利要求21所述的封装方法，其中在步骤S5使所述导热保护层覆盖并直接接触步骤S4所制得的封装结构的整个背面侧的表面，该封装结构的背面侧指所述基板第二表面所朝向的那一侧。
36.如权利要求35所述的封装方法，其中该导热保护层通过在该封装结构的整个背面侧的表面溅射导热率高于100W/m.K的材料而形成。
37.如权利要求35所述的所述的倒装芯片封装单元，其中该导热保护层通过在该封装结构的整个背面侧的表面先溅射导电材料而后再电镀金属材料而形成。
38.如权利要求21所述的封装方法，其中，所述导热保护层的厚度在0.3μm～10μm的范围。
39.如权利要求21所述的封装方法，其中，所述导热保护层的厚度在0.3μm～5μm的范围。
40.如权利要求21所述的封装方法，其中，所述导热保护层的厚度在0.3μm～1μm的范围。
41.如权利要求如权利要求21所述的封装方法，其中，所述导热保护层的厚度在0.5μm～5μm的范围。
42.如权利要求如权利要求21所述的封装方法，其中，所述导热保护层的厚度在2μm～5μm的范围。
43.如权利要求如权利要求21所述的封装方法，其中，所述导热保护层的厚度在2μm～3μm的范围。
44.如权利要求如权利要求21所述的封装方法，其中，所述导热保护层的厚度在3μm～10μm的范围。
45.如权利要求如权利要求21所述的封装方法，进一步包括：
步骤S6，采用切割工艺将步骤S5之后制得的封装结构分割成多个独立的倒装芯片封装单元，每个倒装芯片封装单元中可以包括至少一个集成电路晶片。
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