CN103311213B - 整合屏蔽膜及天线的半导体封装件 - Google Patents
整合屏蔽膜及天线的半导体封装件 Download PDFInfo
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- CN103311213B CN103311213B CN201310160656.5A CN201310160656A CN103311213B CN 103311213 B CN103311213 B CN 103311213B CN 201310160656 A CN201310160656 A CN 201310160656A CN 103311213 B CN103311213 B CN 103311213B
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
半导体封装件包括基板、半导体芯片、封装体、电磁干扰屏蔽元件、介电结构、天线元件、馈入元件及天线接地元件。半导体芯片设于基板上。封装体包覆半导体芯片。电磁干扰屏蔽元件形成于封装体上。介电结构包覆电磁干扰屏蔽元件。天线元件形成于介电结构上。馈入元件连接天线元件与基板的一馈入接点。天线接地元件连接天线元件与电磁干扰屏蔽元件。
Description
技术领域
本发明是有关于一种半导体封装件,且特别是有关于一种无线装置的半导体封装件。
背景技术
无线通信装置例如是手机(cell phone),需要天线已传送及接收信号。传统上,无线通信装置包括天线及通信模块(例如是具有无线射频(RF)通信能力的一半导体封装件),其各设于一电路板的不同部位。在传统方式中,天线及通信模块分别制造且于放置在电路板后进行电性连接。因为设备的分离组件分别制造,导致高制造成本。此外,传统方式难以完成轻薄短小的设计。
发明内容
半导体封装件包括基板、半导体芯片、封装体、电磁干扰屏蔽元件、介电结构、天线元件、馈入元件及天线接地元件。半导体芯片设于基板上。封装体包覆半导体芯片。电磁干扰屏蔽元件形成于封装体上。介电结构包覆电磁干扰屏蔽元件。天线元件形成于介电结构上。馈入元件连接天线元件与基板的一馈入接点。天线接地元件连接天线元件与电磁干扰屏蔽元件。
根据本发明的另一实施例,提出一种半导体封装件。半导体封装件包括一半导体芯片、一贯孔、一电磁干扰屏蔽元件、一封装体、一馈入元件、一天线元件及一天线接地件。半导体芯片具有一整合电路部及一基板部,整合电路部具有一主动面且基板部具有一非主动面。贯孔延伸自主动面且电性连接于整合电路部。电磁干扰屏蔽元件设于非主动面且电性连接于贯孔。封装体包覆半导体芯片的一部分及电磁干扰屏蔽元件的一部分,封装体具有一上表面。
馈入元件贯穿封装体及基板部。天线元件设于上表面且电性连接于馈入元件。天线接地件设于封装体内且连接天线元件与电磁干扰屏蔽元件。
根据本发明的另一实施例,提出一种半导体封装件。半导体封装件包括一半导体芯片、一第一导通孔、一第二导通孔、一电磁干扰屏蔽元件、一馈入元件、一天线元件及一天线接地件。半导体芯片具有一整合电路部及一基板部,整合电路部具有一主动面且该基板部具有一非主动面。第一导通孔及第二导通孔各形成于半导体芯片且电性连接于整合电路部。电磁干扰屏蔽元件设于非主动面且电性连接于第一导电孔。介电层设于电磁干扰屏蔽元件上,介电层具有一上表面。馈入元件包括一第一子馈入元件及一第二子馈入元件,第一子馈入元件第二导通孔,第二子馈入元件设于介电层。天线元件设于上表面且电性连接于馈入元件。天线接地件连接天线元件与电磁干扰屏蔽元件。
附图说明
图1绘示依照本发明一实施例的半导体封装件的剖视图。
图2绘示本发明另一实施例的馈入元件的剖视图。
图3绘示依照本发明另一实施例的半导体封装件的剖视图。
图4绘示另一实施例的第一子馈入元件及第二子馈入元件的剖视图。
图5绘示另一实施例的第一子馈入元件及第二子馈入元件的剖视图。
图6绘示本发明另一实施例的馈入元件的剖视图。
图7绘示图1中局部7’的放大示意图。
图8至图14B绘示本发明数个实施例的天线元件的上视图。
图15绘示依照本发明一实施例的半导体封装件的剖视图。
图16绘示依照本发明再一实施例的半导体封装件的剖视图。
图17绘示依照本发明再一实施例的半导体封装件的剖视图。
图18至图25绘示依照本发明另一实施例的半导体封装件的剖视图。
图26A绘示依照本发明另一实施例的半导体封装件的剖视图。
图26B绘示图26A的侧视图。
图27A至图27I绘示图1的半导体封装件的制造过程图。
图28A至图28D绘示图3的半导体封装件的制造过程图。
图29A至图29F绘示图15的半导体封装件的制造过程图。
图30A至图30F绘示图17的半导体封装件的制造过程图。
图31A至图31G绘示图18的半导体封装件的制造过程图。
图32A至图32G绘示图18的半导体封装件的制造过程图。
图33A至图33F绘示图19的半导体封装件的制造过程图。
图34A至图34E绘示图21的半导体封装件的制造过程图。
图35A至图35D绘示图22的半导体封装件的制造过程图。
图36A至图36E绘示图23的半导体封装件的制造过程图。
图37A至图37K绘示图24的半导体封装件的制造过程图。
图38A至图38C绘示图25的半导体封装件的制造过程图。
主要元件符号说明:
100、200、300、400、500、600、700、800、900、1000、1100、1200、1300、1400:半导体封装件
110、610:整合电路部
111:基板
111u、120u、140u、532u、620u、632u、680u:上表面
111b、140b、610b、680b、1120b:下表面
111s、120s、140s、331s、370s、610s、620s、632s:侧面
111a:馈入接点
112a:半导体装置
112b:被动元件
114、114a:电性接点
120、1120:封装体
120s:内侧壁
121:馈入贯孔
122:接地贯孔
123:种子层
124:天线接地贯孔
130、330、530:电磁干扰屏蔽元件
131:第一防电磁干扰膜
131a、140a、155r、160dr、331a、631a:开孔
132、332、532:接地元件
140:介电结构
140w:内侧壁
150:天线元件
150r:沟槽
155:天线接地件
160、160′、260、660:馈入元件
160a:导电层
160b:填充树脂
160c、260a、260a″、660a:第一子馈入元件
160d、260b、260″:第二子馈入元件
170、370、532、570、670:接地部
171:接地接点
172:突出部
180:接地支架
190:介电材料层
331:第一防电磁干扰膜
380:载板
611:焊块
611a:馈入接点
613:接垫
620:硅基板
630、1130:电磁干扰屏蔽元件
631:第一共形屏蔽膜
632:接地元件
633:第一金属层
661:第二金属层
680:第二基板
1080:重布层
1080a1:第一介电层
1080a2:图案化导电层
1080a3:第二介电层
A1:夹角
C:凹痕
H:高度
T1、T3:第一切割狭缝
具体实施方式
请参照图1,其绘示依照本发明一实施例的半导体封装件100的剖视图。半导体封装件100包括基板111、半导体装置112a、被动元件112b、封装体120、电磁干扰屏蔽元件130、介电结构140、天线元件150、馈入元件160及天线接地件155。本实施例的半导体封装件100整个以半导体封装工艺制作,因此在不需额外的天线制作设备的情况下,可同时形成天线元件150。
基板111包括上表面111u、下表面111b及侧面111s,下表面111b相对于上表面111u,侧面111s位于基板111的边缘(periphery)。侧面111s延伸于上表面111u与下表面111b之间,定义出基板111的边界。基板111例如是一多层有机基板或一陶瓷基板。
本实施例中,半导体装置112a处于”面下(face-down)”方位,亦即其通过数个焊球(solder ball)电性连接于基板111,如此的结构可称为”覆晶(flip-chip)”。另一实施例中,半导体装置112a处于”面上(face-up)”方位,亦即其通过数条焊线(bond wire)电性连接于基板111。被动元件112b可包括一电阻、一电感或一电容。此外,半导体装置112a及被动元件112b可内埋于基板111。
封装体120设于基板111的上表面111u,且包覆半导体装置112a及被动元件112b。封装体120包括一上表面120u及一侧面120s。封装体120的材料可包括酚醛基树脂(Novolac-based resin)、环氧基树脂(epoxy-based resin)、硅基树脂(silicone-basedresin)或其它适当的包覆剂。封装体120亦可包括适当的填充剂,例如是粉状的二氧化硅。可利用数种封装技术形成封装体,例如是压缩成型(compression molding)、注射成(injection molding)或转注成型(transfer molding)。
电磁干扰屏蔽元件130实质上覆盖封装体120的上表面120u及侧面120s。电磁干扰屏蔽元件130可包括第一防电磁干扰膜131及接地元件132,且提供电磁干扰屏蔽效果。
第一防电磁干扰膜131直接形成于封装体120的上表面120u且包括一开孔。当天线元件150一平板天线(patch antenna),第一防电磁干扰膜131可作为天线元件150的接地结构。第一防电磁干扰膜131可包括铝、铬、金、银、镍、不锈钢、任何其它适合材料或适合的合金。
接地元件132覆盖封装体120的侧面120s,且电性连接第一防电磁干扰膜131与基板111。其中,接地元件132一第二防电磁干扰膜。接地元件132及第一防电磁干扰膜131可由相同材料形成,且于同一工艺中一体成形,或分别于不同工艺中形成。介电结构140覆盖第一防电磁干扰膜131及接地元件132,且包括上表面140u。介电结构140可由例如是封装体材料、介电材料(例如是环氧树脂(epoxy))或预浸材迭层(prepreg lamination)形成。介电结构140的侧面140s与基板111的侧面111s实质上共面。
天线元件150形成于介电结构140的上表面140u,并沿实质上平行于第一防电磁干扰膜131的方向延伸。天线元件150具有数个实施方面。天线元件150可形成于介电结构140的上表面的一部分上,且馈入元件160可部分地或完全地与天线元件150重迭。此外,天线元件150与半导体装置112a或被动元件112b可位于不同垂直高度的位置,以减少基板111的上表面111u的使用面积,使整个半导体封装件100的长、宽尺寸缩小。
如图所示,天线接地件155经过介电结构140且电性连接天线元件150与电磁干扰屏蔽元件130。如图所示,天线接地件155经过介电结构140及封装体120,且天线接地件155电性连接天线元件150与接地部170。另一实施例中,天线接地件155连接天线元件150与设于半导体封装件100的电位(potential)。相较于省略天线接地件155的半导体封件的设计,天线元件150可较小,进而缩小半导体封装件100的尺寸。一实施例中,天线元件150的分布区域约可减少50~75%的分布面积。天线接地件155例如是焊线(bond wire)材料,其以打线技术形成。
本发明实施例的馈入元件160通过封装体120及介电结构140。馈入元件160电性连接天线元件150与基板111的一馈入接点(feeding point)111a。例如,本发明实施例的馈入元件160可以是导电柱,其设于一提供电磁干扰保护的接地导孔。馈入元件160亦可为导电膜、导电层或导电层与树脂的组合(例如,树脂覆盖导电层且填满被导电层环绕的空间,如后所述)。
馈入接点111a可以是接垫、焊点、凸块或第一基板111中露出的线路层。馈入接点111a可位于半导体装置112a、被动元件112b或基板111上。馈入元件160连接于馈入接点111a。本实施例中,馈入接点111a位于基板111上且从基板111的上表面111u露出。
接地部170与接地元件132电性连接,且位于半导体装置112a、被动元件112b与基板111的一者。本实施例中,接地部170位于基板111上。接地部170例如是接垫、焊点、凸块或露出基板111的线路层。
半导体封装件100更包括至少一接垫113及一电性接点114,电性接点114设于下表面111b,其中电性接点114例如是焊球(solder ball)、导通孔(conductive via)或凸块(bump)。本实施例的电性接点以焊球为例说明,使半导体封装件100成为一球栅阵列(BallGrid Array,BGA)结构。或者,半导体封装件100可省略电性接点114,而成为一平面闸格阵列(Land Grid Array,LGA)结构。此外,该些电性接点114中的一电性接点114a例如是接地接点,其通过基板111电性连接于接地部170。电性接点114a用以电性连接于一外部电路元件的接地端。请参照图2,其绘示本发明另一实施例的馈入元件的剖视图。馈入元件160’包括导电层160a及填充树脂160b,其中填充树脂160b覆盖导电层160a,并填满导电层160a所围绕的空间。其中,封装体120具有一馈入贯孔121。导电层160a设于对应的馈入贯孔121的内侧壁120s上,馈入贯孔121通过封装体120及介电结构140;然后,利用适当的涂布技术形成填充树脂160b覆盖导电层160a,并填满导电层160a所围绕的空间,以形成图2的馈入元件160’。上述涂布技术例如是印刷(printing)、镀层(plating)、旋涂(spinning)或喷涂(spraying)。
请参照图3,其绘示依照本发明另一实施例的半导体封装件的剖视图。半导体封装件200的馈入元件260包括第一子馈入元件260a及第二子馈入元件260b,第一子馈入元件260a经过封装体120,而第二子馈入元件260b经过介电结构140。第一子馈入元件260a及第二子馈入元件260b可于不同工艺中分别形成。虽然第二子馈入元件260b的下端面积小于第一子馈入元件260a的上端面积,然于其它实施方面中,第二子馈入元件260b的下端面积实质上大于或实质上等于第一子馈入元件260a的上端面积。
第一子馈入元件260a与第二子馈入元件260b可以是不同结构。例如,第一子馈入元件260a可以是导电柱,且第二子馈入元件260b可以是导电层或导电层与树脂的组合(例如是图2所示的馈入元件的结构)。另一实施例中,第一子馈入元件260a可以是导电层或导电层与第二子馈入元件260的组合,其中第二子馈入元件260例如是导电柱。
请参照图4,其绘示另一实施例的第一子馈入元件及第二子馈入元件的剖视图。第一子馈入元件260a’导电柱,而第二子馈入元件260b’的结构相似于图2所示的馈入元件160’,其导电层与填充树脂的组合。此外,第一子馈入元件260a’的形成方法相似于图1的馈入元件160的形成方法,第二子馈入元件260b’的形成方法相似于图2的馈入元件160’的形成方法。
请参照图5,其绘示另一实施例的第一子馈入元件及第二子馈入元件的剖视图。第一子馈入元件260a”的结构相似于图2的馈入元件160’,其导电层与填充树脂的组合。第二子馈入元件260b”导通孔,第二子馈入元件260b”的形成方法相似于图1的馈入元件160的形成方法。
请参照图6,其绘示本发明另一实施例的馈入元件的剖视图。馈入元件160a例如是导电柱。介电结构140具有一开孔140a,开孔140a露出馈入元件160a,天线元件150经由开孔140a连接于馈入元件160。在图6的实施例中,介电结构140薄型介电结构,使天线元件150于转弯部分形成一均匀厚度,然此非用以限制本发明。另一实施例中,可增加开孔140a的内侧壁140w与介电结构140的上表面140u之间的夹角A1,以增加内侧壁140w的斜度,使天线元件150的转弯部分形成一均匀厚度。另外,控制开孔140a的宽度亦可以使天线元件150的厚度更为均匀,较佳但非限定地,开孔140a的宽度与介电结构140的厚度的比例小于或实质上等于1.5,例如,若介电结构140的厚度为0.3微米(um),则开孔140a的宽度可以介于约0.3微米(um)至0.5微米(um)之间。
图6中,天线元件150经由开孔140a连接于馈入元件160a,因而形成一转弯部分。也就是说,天线元件150连续地设于介电结构的上表面140u、内侧壁140w及馈入元件160a的上表面,且天线元件150直接接触馈入元件160a。较佳但非限定地,介电结构140预浸材迭层,以减少其厚度并使天线元件150于转弯部分形成一均匀厚度。另一实施例中,即使介电结构140非薄型结构,在增加介电结构140的开孔140a的内侧壁140w的斜度下,仍可使天线元件150于转弯部分形成一均匀厚度。
请参照图7,其绘示图1中局部7’的放大示意图。接地部170包括接地接点171及突出部172。接地接点171位于基板111的上表面111u上,其可以是接垫且电性连接于第一基板111的接地(grounding)电路。于一实施方面中,接地接点171可以是接垫、焊点、凸块或露出第一基板111的线路层。接地接点171的厚度介于约12um至18um之间或介于其它数值范围。突出部172例如是锡焊点,其覆盖接地接点171并电性连接于接地接点171。
图7中,由于突出部172具有高度H,可避免制造过程中切割刀具切断接地接点171。即,突出部172的形成可避免接地接点171被分离成二部分。此外,切割刀具经过突出部172并于突出部172上切割出凹痕C。凹痕C的外形可呈V字型,然此非用以限定本发明,凹痕C的外形视切割刀具或切割方式而定。
如图8所示,其绘示本发明一实施例的天线元件的上视图,天线元件150的外形矩形且形成于介电结构140的上表面140u的一部分上,而馈入元件160的一部分与天线元件150的一部分重迭。
如图9所示,天线元件150的外形弯曲型(serpentine shape),然其它实施方面中,天线元件150亦可形成螺旋形、菱形结构与S型结构的一者。天线元件150的外形可设计为具有数个激发态(excited state)。
如图10所示,天线元件150一图案化天线结构,其形成于介电结构140的上表面140u的一部分上,且整个馈入元件160与天线元件150重迭,然馈入元件160亦可与天线元件150部分重迭。本实施例的天线元件150具有双频特性(dual-band property)。
如图11所示,天线元件150形成于介电结构140的上表面140u的一部分上,而整个馈入元件160与天线元件150重迭。此外,天线元件150的位置、外形及尺寸视通信要求而定,本发明实施例不作任何限制。此外,天线元件150例如是使用图案化箔片(patternedfoil)、电镀、溅镀或其它相似工艺去涂布一金属层而形成。天线元件150的材质例如是金属,其可选自于铝、铜、铬、锡、金、银、镍、不锈钢及其组合所构成的群组。
如图11所示,为了降低电磁干扰影响信号品质,数个天线接地件155环绕馈入元件160。其它实施例中,少数或只有单个天线接地件155环绕或邻近馈入元件160设置。
如图12A所示,天线元件150一图案化天线元件,其具有一沟槽150r,沟槽150r延伸于天线元件150的二对角之间。本实施例中,沟槽150r一封闭沟槽,其不与天线元件150的外侧面连接。本实施例的天线元件150可具有多种图案,并不受本发明实施例所限制。本实施例的天线元件150具有双频特性。
如图12B所示,沟槽150r可以是开放沟槽,其延伸至天线元件150的外侧面。虽然图12B的天线接地件155只有单个,然可理解地,多个天线接地件155可设于天线元件150上。本实施例的天线元件150具有双频特性。
如图13A及图13B所示,天线元件150一图案化天线元件,其延伸呈螺旋形或是迂回地延伸。本实施例的天线元件150具有双频特性。
如图14A所示,天线元件150是一图案化天线元件,其延伸呈封闭环状,且邻近半导体封装件100的边缘。本实施例的天线元件150具有双频特性。
如图14B所示,天线元件150是一图案化天线元件,其延伸呈开放环状,且邻近半导体封装件100的边缘。本实施例的天线元件150具有双频特性。
请参照图15,其绘示依照本发明一实施例的半导体封装件300的剖视图。半导体封装件300包括基板111、半导体装置112a、被动元件112b、封装体120、电磁干扰屏蔽元件330、介电结构140、天线元件150、馈入元件160及天线接地件155。半导体装置112a及被动元件112b设于基板111的上表面111u且电性连接于基板111。封装体120包覆半导体装置112a及被动元件112b且具有一上表面120u。电磁干扰屏蔽元件330包括第一防电磁干扰膜331与接地元件332。
接地元件332例如是第二防电磁干扰膜,其覆盖封装体120的侧面120s、基板111的侧面111s、介电结构140的侧面140s及第一防电磁干扰膜331的侧面331s。此外,封装体120的侧面120s、基板111的侧面111s与介电结构140的侧面140s实质上齐平或共面。
半导体封装件300更包括接地部370,其设于第一基板111内并从基板111的侧面111s露出,使接地元件332可电性接触于接地部370。此外,接地部370的侧面与基板111的侧面111s实质上齐平或共面。接地部370可延伸于第一基板111的上表面111u与下表面111b之间,例如,如图15所示,接地部370埋设于第一基板111且不贯穿基板111,并从基板111的侧面111s露出。又例如,另一实施例中,接地部370可从上表面111u延伸至下表面111b,即贯穿整个基板111。
请参照图16,其绘示依照本发明再一实施例的半导体封装件400的剖视图。半导体封装件400的馈入元件形成如图3所示的馈入元件260。也就是说,馈入元件包括第一子馈入元件260a及第二子馈入元件260b。
请参照图17,其绘示依照本发明再一实施例的半导体封装件500的剖视图。半导体封装件500包括基板111、半导体装置112a、被动元件112b、电磁干扰屏蔽元件530、介电结构140、天线元件150、馈入元件160及天线接地件155。半导体装置112a及被动元件112b设于基板111的上表面111u且电性连接于基板111。半导体封装件500的封装体120包覆半导体装置112a及被动元件112b。电磁干扰屏蔽元件530包括第一防电磁干扰膜331与接地元件532。或者,更多接地元件532可以被提供,在此例子中,数个接地元件532可配置于邻近半导体装置112a的设置区域的周边,且环绕半导体装置112a以降低或消除电磁干扰。
半导体封装件500的接地元件532经过封装体120。接地元件532例如是一导电柱,其电性连接于第一防电磁干扰膜331与基板111的接地部570,其中,接地部570从第一基板111的上表面111u露出。本实施例中,第一防电磁干扰膜331覆盖接地元件532的上表面532u。一实施例中,第一防电磁干扰膜331可覆盖接地元件532的侧面,而接地元件532的上表面532u从第一防电磁干扰膜331露出。或者,接地部532可以是一通过封装体120的电镀孔(plated via),且该电镀孔的内侧壁上设有一导电层。
半导体封装件500的馈入元件160导电柱,其电性连接天线元件150与被动元件112b。一实施例中,馈入元件160亦可连接天线元件150与基板111,此相似于图1的馈入元件160。或者,半导体封装件500的馈入元件160的结构可相似于图2至图6的一的馈入元件的结构。
封装体120的侧面120s、基板111的侧面111s、介电结构140的侧面140s与第一防电磁干扰膜331的侧面331s实质上齐平,或共面。
请参照如图18,其绘示依照本发明另一实施例的半导体封装件600的剖视图。半导体封装件600包括一覆晶式半导体芯片、电磁干扰屏蔽元件630、封装体120、天线元件150、馈入元件660及天线接地件155。覆晶式半导体芯片包括一整合电路部610及一硅基板620,其中整合电路部610形成于硅基板620上,且硅基板620具有一上表面620u。整合电路部610可包括一个或多个晶体管、二极管、电感、电容、电阻及其它电路元件。此外,多个电性触点(electrical contact)形成于整合电路部610的接触垫(contact pad)。
半导体封装件600的电磁干扰屏蔽元件630包括第一共形屏蔽膜(conformalshield film)631及一接地元件632。第一共形屏蔽膜631覆盖硅基板620的上表面620u。接地元件632硅通孔(through-silicon via,TSV)。其中,硅通孔可经由于硅基板620开设一开孔且以导电材料填满该开孔而形成。接地元件632贯穿硅基板620,且电性连接第一共形屏蔽膜631与整合电路部610。
馈入元件660贯穿封装体120及硅基板620,且电性连接天线元件150与整合电路部610。如图18所示,馈入元件660包括一第一子馈入元件660a及一第二子馈入元件660b。第二子馈入元件660b形成于封装体120的一贯孔的一导通孔。贯孔经由例如是激光钻孔于封装体120开设一开孔,且以导电材料填满该开孔而形成。第一子馈入元件660a形成于硅基板620的一贯孔的一导通孔。接地元件632及第一子馈入元件660a可一并于同一工艺中形成。或者,半导体封装件600的馈入元件660的结构亦可相似于图2至图6的馈入元件。
半导体封装件600的封装体120包覆整合电路部610与硅基板620。半导体封装件600更包括第二基板680,其通过焊块(solder bump)611电性连接于整合电路部610。第二基板680的结构及材质可相似于第一基板111,容此不再赘述。
请参照如图19,其绘示依照本发明另一实施例的半导体封装件700的剖视图。差异在于,接地元件632及馈入元件660通过整合电路部610及硅基板620此二者。此外,馈入元件660更通过封装体120及直接接触天线元件150。
请参照如图20,其绘示依照本发明另一实施例的半导体封装件800的剖视图。半导体封装件800的第一共形屏蔽膜631覆盖硅基板620的上表面620u,且直接接触接地元件632的上表面632u。一实施例中,接地元件632的上表面632u从第一共形屏蔽膜631露出,而非被第一共形屏蔽膜631覆盖。馈入元件160通过封装体120且通过第二基板680的电路部局(circuit layout)电性连接天线元件150与整合电路部610。或者,半导体封装件800的馈入元件160的结构亦可相似于图2至图6的一者的馈入元件。
请参照如图21,其绘示依照本发明另一实施例的半导体封装件900的剖视图。半导体封装件900包括整合电路部610、硅基板620、电磁干扰屏蔽元件630、介电结构140、天线元件150、馈入元件160及天线接地件155。本实施例的半导体封装件900可为一整合天线结构的半导体晶圆级芯片尺寸封装件(WLCSP;Wafer Level Chip Scale Package),其中整合电路部610可包含一个或多个晶体管、二极管、电感、电容、电阻及其它电路结构。如图21所示,半导体封装件900更包括多个焊块,其中焊块可通过接触垫或重布层(redistributionlayer,RDL)连接于整合电路部610。
电磁干扰屏蔽元件630包括第一共形屏蔽膜631及接地元件632。接地元件632例如是硅通孔,其电性连接第一共形屏蔽膜631与整合电路部610。亦即,接地元件632可经由于硅基板620开设一开孔且以导电材料填满该开孔而形成,其中,该开孔从硅基板620的上表面620u延伸至硅基板620的一表面(整合电路部形成于该表面上)。本实施例中,第一共形屏蔽膜631电性接触接地元件632的一侧面632s,且接地元件632的上表面632u从第一共形屏蔽膜631露出。亦即,第一共形屏蔽膜631未覆盖接地元件632的上表面632u。于一实施例中,第一共形屏蔽膜631可覆盖接地元件632的上表面632u的一部分。馈入元件160经过封装体120及硅基板620此二者,以电性连接天线元件150与整合电路部610。或者,半导体封装件800的馈入元件160的结构亦可相似于图2至图6的馈入元件。此外,介电结构140覆盖硅基板620的上表面620u。
请参照图22,其绘示依照本发明另一实施例的半导体封装件1000的剖视图。半导体封装件1000为一扇出型晶圆级封装件(Fan-out Wafer Level Package,FOWLP)。半导体封装件1000包括半导体芯片、电磁干扰屏蔽元件630、封装体120、天线元件150、馈入元件160及天线接地件155。半导体芯片包括一整合电路部610及一硅基板620,其中,整合电路部610可包括一个或多个晶体管、二极管、电感、电容、电阻及其它电路元件。
电磁干扰屏蔽元件630包括第一共形屏蔽膜631与接地元件632。第一共形屏蔽膜631覆盖硅基板620的上表面620u。半导体封装件1000更包括一重布层1080,其电性连接至整合电路部610。重布层1080形成于整合电路部610与硅基板620被封装体120包覆之后。因此,硅基板620包覆整合电路部610、硅基板620及重布层1080的一部分。
请参照图23,其绘示依照本发明另一实施例的半导体封装件1100的剖视图。半导体封装件1100可以为一扇出型晶圆级封装件(Fan-out Wafer Level Package,FOWLP)。半导体封装件1100包括半导体芯片、电磁干扰屏蔽元件1130、介电结构140、天线元件150、馈入元件160及天线接地件155。半导体芯片包括一整合电路部610及一硅基板620,其中,整合电路部610可包括一个或多个晶体管、二极管、电感、电容、电阻及其它电路元件。半导体封装件1100更包括封装体1120,其覆盖硅基板620的上表面620u及侧面620s,以及整合电路部610的侧面610s。
电磁干扰屏蔽元件1130包括第一防电磁干扰膜331与接地元件632,其中第一防电磁干扰膜331形成于封装体1120上且被介电结构140覆盖。接地元件632封装体1120的一导通贯孔(conductive through-hole),其从硅基板620的上表面620u延伸至硅基板620的其它表面(整合电路部610形成于其上的表面)。亦即,接地元件632通过封装体1120及硅基板620,以电性连接第一防电磁干扰膜331与整合电路部610。
馈入元件160经过介电结构140、封装体120及硅基板620,以电性连接天线元件150与整合电路部610,其中,馈入元件160直接接触天线元件150。或者,馈入元件160的结构亦可相似于图2至图6之一中的馈入元件的结构。
请参照图24,其绘示依照本发明另一实施例的半导体封装件1200的剖视图。半导体封装件1200包括基板111、半导体装置112a、被动元件112b、封装体120、电磁干扰屏蔽元件130、介电结构140、天线元件150、馈入元件160、天线接地件155及接地支架180。
电磁干扰屏蔽元件130覆盖封装体120的外表面120s及接地支架180从封装体120的外表面120s露出的外侧面。电磁干扰屏蔽元件130的接地路径包含接地支架180以及基板111与电性接点114a的互连机制(interconnection),该互连机制连接至一外部接地点以增进屏蔽效果。
天线元件150形成于介电结构140上,且电性连接于馈入元件160及基板111的馈入接点111a。天线接地件155例如是焊线材料,其以打线技术形成。另一实施例中,天线接地件155的结构可相似于上述馈入元件160’或260b’。
馈入元件160包括第一子馈入元件160c及第二子馈入元件160d。位于封装体120的第一子馈入元件160c电性连接于基板111,而位于介电结构140的第二子馈入元件160d连接于第一子馈入元件160c。第一子馈入元件160a及第二子馈入元件160d例如是焊线材料,其以打线技术形成。
接地支架180设于基板111的一上表面111u,且通过基板111的互连机制而电性连接于电性接点114a(接地接点)。
请参照图25,其绘示依照本发明另一实施例的半导体封装件1300的剖视图。半导体封装件1300包括基板111、半导体装置112a、被动元件112b、封装体120、电磁干扰屏蔽元件130、介电结构140、天线元件150、馈入元件160、天线接地件155、接地支架180及介电材料层190。
介电材料层190形成于介电结构140的上表面140u,其中介电结构140的介电常数低于需求水准,介电材料层190可形成以增加介电材料层190与介电结构140整体的介电值至需求水准。介电材料层190的介电系数εr1大于介电结构140的介电系数εr2,例如,介电系数εr1约介电系数εr2的2至100倍之间。介电材料层190与介电结构140整体的等效介电系数ε可经由下式(1)计算。
介电材料层190高介电系数材料,其材质包括陶瓷材料,如氧化铝或氧化硅等。
如图25所示,介电材料层190的厚度d1小于介电结构140的厚度d2,例如,介电材料层190的厚度d1介于介电结构140的厚度d2的5%至90%之间。另一实施例中,介电材料层190的厚度d1可大于介电结构140的厚度d2。相较于数值大的等效介电系数,数值小的介电系数值使天线元件150的分布区域可以设计得较小,如此可缩小半导体封装件的尺寸。介电系数值可视天线阻抗而定。
请参照图26A,其绘示依照本发明另一实施例的半导体封装件1400的剖视图。半导体封装件1400包括基板111、半导体装置112a、被动元件112b、封装体120、电磁干扰屏蔽元件130、介电结构140、天线元件150、馈入元件160、天线接地件155、接地支架180及介电材料层190。
请参照图26B,其绘示图26A的侧视图。天线接地件155形成于介电结构140的外侧面140s及电磁干扰屏蔽元件130,以电性连接于电性接点114a(接地接点)。馈入元件160形成于介电结构140的外侧面140s且延伸至基板111的馈入接点111a(未绘示)。也就是说,本例中,天线接地件155及馈入元件160天线元件150的延伸,其延伸至半导体封装件100的侧面的层结构。天线接地件155、馈入元件160与天线元件150可于同一工艺中一并形成。
请参照图27A至图27I,其绘示图1的半导体封装件100的制造过程图。
如图27A所示,以例如是表面黏着技术(Surface Mount Technology,SMT)于邻近第一基板111的上表面111u设置一半导体装置112a及被动元件112b。基板111包括接地部170。
如图27B所示,于基板111的上表面111u形成封装体120包覆半导体元件,其中,封装体120具有上表面120u。
如图27C所示,形成至少一第一切割狭缝T1,其中第一切割狭缝T1经过封装体120。第一切割狭缝T1由适合的激光或其它切割工具所形成,因此于封装体120上形成侧面120s。在一实施例中,第一切割狭缝T1亦可经过部分的基板111。在本实施例中,切割方法采用半穿切(Half-cut)方式,即第一切割狭缝T1不切断基板111。
如图27D所示,形成电磁干扰屏蔽元件130,电磁干扰屏蔽元件130包括第一防电磁干扰膜131与接地元件132。可以例如是材料形成技术形成电磁干扰屏蔽元件130,而上述材料形成技术例如是化学气相沉积、无电镀法(electroless plating)、电解电镀(electrolytic plating)、印刷、旋涂、喷涂、溅镀(sputtering)或真空沉积法(vacuumdeposition),本实施例中,第一防电磁干扰膜131与接地元件132于同一工艺中一体形成,然此非用以限制本发明。
图27D中,第一防电磁干扰膜131覆盖封装体120的上表面120u。第一防电磁干扰膜131具有一开孔131a,其露出封装体120的一部分。开孔131a的位置对应于馈入接点111a,即,开孔131a位于馈入接点111a的正上方。本实施例中,馈入接点111a形成于邻近第一基板111的上表面111u。一实施例中,馈入接点111a亦可位于半导体装置112a或被动元件112b中。接地元件132第二防电磁干扰膜,其连接于第一防电磁干扰膜131及接地部170且覆盖封装体120的侧面120s。
如图27E所示,形成介电结构140覆盖第一防电磁干扰膜131、接地元件132及第一基板111中露出的上表面。可使用任何已知技术形成介电结构140,例如是封装技术或压合(1aminate)技术。
如图27F所示,形成一馈入贯孔121贯穿封装体120及介电结构140,以及形成天线接地贯孔124贯穿介电结构140。馈入贯孔121经过介电结构140、开孔131a及封装体120,且馈入贯孔121露出馈入接点111a。形成馈入贯孔121的图案化技术包括微影工艺(photolithography)、化学蚀刻(chemical etching)、激光钻孔(1aser drilling)或机械钻孔(mechanical drilling)。天线接地贯孔124露出第一防电磁干扰膜131。
如图27G所示,使用电镀、锡膏(solder paste)或其它涂布导电材料的方式将导电材料填满馈入贯孔121及天线接地贯孔124以形成馈入元件160及天线接地件155。馈入元件160延伸自介电结构140的上表面140u,且电性连接于馈入接点111a上。此外,可采用电镀、锡膏或其它涂布导电材料的方式,填入导电材料于天线接地贯孔124内而形成天线接地件155,其中天线接地件155接触第一防电磁干扰膜131。
如图27H所示,形成天线元件150于介电结构140的上表面140u,并直接与馈入元件160及天线接地件155接触,使天线元件150通过馈入元件160电性连接整合电路部110且通过天线接地件155电性连接于接地部170。天线元件150可使用例如是上述电镀/微影工艺形成。
如图27I所示,形成数道经过介电结构140及整个第一基板111的第二切割狭缝T2,例如是以激光或其它切割刀具的方式形成第二切割狭缝T2。此外,于形成第二切割狭缝T2之前或之后,可形成电性接点114于邻近基板111的下表面111b,以形成如图1所示的半导体封装件100。
请参照图28A至图28D,其绘示图3的半导体封装件的制造过程图。
如图28A所示,形成至少一贯穿封装体120的馈入贯孔121。
如图28B所示,将导电材料填满馈入贯孔121,形成第一子馈入元件260a。
如图28C所示,形成电磁干扰屏蔽元件130及介电结构140,且于介电结构140形成一开孔140a及天线接地贯孔124,其中开孔140a露出对应的第一子馈入元件260a,而天线接地贯孔124露出第一防电磁干扰膜131。
如图28D所示,以导电材料填满对应的开孔140a及天线接地贯孔124,以形成一第二子馈入元件260b及天线接地件155,其中第一子馈入元件260a与第二子馈入元件260b构成图3所示的馈入元件260。
请参照图29A至图29F,其绘示图15的半导体封装件的制造过程图,本实施例采用全穿切(Full-cut)方式。
如图29A所示,形成第一防电磁干扰膜331于封装体120的上表面120u。第一防电磁干扰膜331具有一开孔331a,其露出封装体120的一部分,且其位置对应于馈入接点111a。
如图29B所示,形成覆盖第一防电磁干扰膜331的介电结构140。
如图29C所示,形成一贯穿介电结构140及封装体120的馈入贯孔121,以及形成天线接地贯孔124。
如图29D所示,以导电材料填满馈入贯孔121,而形成馈入元件160,以及以导电材料填满对应的天线接地贯孔124,而形成天线接地件155。其中,馈入元件160经过介电结构140、开孔331a及封装体120,而天线接地件155接触于第一防电磁干扰膜331。
如图29E所示,形成一经过封装体120、介电结构140、第一防电磁干扰膜331及基板111的第一切割狭缝T3。其中,封装体120的侧面120s、第一基板111的侧面111s、介电结构140的侧面140s、第一防电磁干扰膜331的侧面331s及接地部370的侧面370s实质上齐平。此外,第一切割狭缝T3形成前,可将第一基板111黏贴于载板380上。第一切割狭缝T3可经过部分的载板380,以彻底切断封装体120、介电结构140、第一防电磁干扰膜331及第一基板111。
如图29F所示,形成至少一天线元件150于介电结构140的上表面140u。形成接地元件332覆盖封装体120的侧面120s、第一基板111的侧面111s、介电结构140的侧面140s、第一防电磁干扰膜331的侧面331s及接地部370的侧面370s。待移除载板380及形成电性接点114于邻近基板111的下表面111b后,完成如图15所示的半导体封装件300。
请参照图30A至图30F,其绘示图17的半导体封装件的制造过程图。
如图30A所示,使用例如是表面黏着技术(Surface Mount Technology,SMT),设置至少一半导体装置112a及一被动元件112b于邻近第一基板111的上表面111u。然后,形成封装体120覆盖基板111的上表面111u、半导体装置112a及被动元件112b。
如图30B所示,形成一贯穿封装体120的接地贯孔122。接地贯孔122露出接地部570。一实施例中,接地贯孔122的形成可整合至封装体120的形成工艺中。
如图30C所示,使用导电材料填满接地贯孔122以形成至少一接地元件532,其中接地元件532电性连接于基板111的接地部570。
如图30D所示,形成第一防电磁干扰膜331覆盖封装体120的上表面120u。第一防电磁干扰膜331具有一开孔331a,其露出封装体120的一部分,且其位置对应于半导体元件装置112a及被动元件112b。本实施例中,第一防电磁干扰膜331的开孔331a的位置对应于被动元件112b。图30D中,第一防电磁干扰膜331直接接触接地元件532的上表面532u,然于其它实例中,接地元件532可形成于第一防电磁干扰膜331形成于封装体120的上表面120u之后,使接地元件532的上表面532u的一部份从第一防电磁干扰膜331露出。
如图30E所示,形成介电结构140覆盖第一防电磁干扰膜331。
如图30F所示,经由开设一通过封装体120及介电结构140的开孔且使用导电材料填满该开孔,形成一馈入元件160。本实施例中,馈入元件160电性连接于半导体装置112a及被动元件112b。然后,形成如图17所示的天线元件150于介电结构140上且直接接触馈入元件160。此外,经由开设一通过介电结构140的开孔且使用导电材料填满该开孔,形成一天线接地件155。然后,形成一如图17所示的电性接点114于邻近基板111的下表面111b。然后,形成一切割狭缝(未绘示),切割狭缝经过介电结构140、封装体120、第一防电磁干扰膜331及基板111,以形成一如图17所示的半导体封装件500。一实施例中,电性接点114亦可形成于切割狭缝形成之后。
请参照图31A至图31G,其绘示图18的半导体封装件的制造过程图。
如图31A所示,提供半导体芯片(semiconductor die),该半导体芯片包括一具有一主动面的整合电路部610及具有一非主动面的一硅基板620。整合电路部610可包括一个或多个晶体管、二极管、电感、电阻及其它电路元件,且一接地部670及一馈入接点111a形成于整合电路部610内。此外,数个接触垫及一重布层(未绘示)可设于整合电路部610并与整合线路部610电性连接。为了减少半导体芯片的厚度,可使用磨削(grinding)方法,移除硅基板620的一部分。
如图31B所示,形成一馈入贯孔121及一接地贯孔122(其可包括一硅穿孔)于硅基板620。其中,馈入贯孔121及接地贯孔122从硅基板620的上表面620u延伸至一前表面(整合电路部610形成于该前表面上)。例如,使用深反应式离子蚀刻法(reactive-ion etching,RIE),形成馈入贯孔121及接地贯孔122于硅基板620。馈入贯孔121及接地贯孔122使用″贯孔后形成(via-last approach)″方式形成,亦即,馈入贯孔121及接地贯孔122形成于整合电路部610形成之后。
如图31C所示,形成一种子层123于馈入贯孔121及接地贯孔122的侧壁上。种子层123的材料可以例如是铜或铜合金。一实施例中,种子层可使用溅镀(sputtering)形成;其它实施例中,可使用化学蒸镀(chemical vapor deposition,CVD)或电镀。此外,一环状绝缘层(未绘示)可于种子层123形成之前形成于馈入贯孔121。
如图31D所示,可使用导电材料填满馈入贯孔121及接地贯孔122,形成一接地元件632及一第一子馈入元件660a,导电材料例如是铜、铝、锡、镍、金或银。接地元件632电性连接于整合电路部610的接地部670,且第一子馈入元件660a电性连接于整合电路部610的馈入接点111a。此外,接地元件632及第一子馈入元件660a的形成可于同一工艺中一并完成。
如图31E所示,形成第一共形屏蔽膜631覆盖硅基板620的上表面620u。第一共形屏蔽膜631及接地元件632形成后,如第31E图所示的导通孔(via)便形成,接地元件632提供一接地路径且电性连接整合电路部610与第一共形屏蔽膜631。此外,第一共形屏蔽膜631具有一开孔631a以露出第一子馈入元件660a,例如,馈入元件660及第一子馈入元件660a与第一共形屏蔽膜631为电性隔离。
如图31F所示,形成一电性接点614a于整合电路部610的接触垫上。然后,设置半导体芯片于邻近第二基板680的上表面680u。其中,整合电路部610通过电性接点614a与第二基板680电性连接。然后,形成封装体120包覆第一共形屏蔽膜631、第二基板680的上表面680u及半导体芯片。
如图31G所示,形成一第二子馈入元件660b。其中,第一子馈入元件660a与第二子馈入元件660b构成馈入元件660。此外,第二子馈入元件660b的形成方法相似于图3的第二子馈入元件260b的形成方法,容此不再赘述。此外,经由开设一通过封装体120的开孔且使用导电材料填满该开孔,形成一天线接地件155。然后,形成如图18所示的天线元件150于封装体120,及形成一切割狭缝(未绘示),切割狭缝经过介电结构140及第二基板680,以形成一如图18所示的半导体封装件600。于一实施例中,可于切割狭缝形成之前或之后,形成至少一如图1所示的电性接点114于邻近第二基板680的下表面680b。
如图31G所示,第一子馈入元件660a与第二子馈入元件660b构成馈入元件660。然而,如图20所示,馈入元件660可贯穿封装体120以电性连接于天线元件150及设于第二基板680的馈入接点。
请参照图32A至图32G,其绘示图18的半导体封装件的制造过程图,以”贯孔先形成(via-first approach)”方式为例说明。
如图32A所示,提供硅基板620。形成一馈入贯孔121及接地贯孔122于硅基板620。可使用深反应式离子蚀刻法(RIE)或激光去除技术(1aser ablation),形成馈入贯孔121及接地贯孔122于硅基板620。
如图32B所示,一薄种子层123形成于馈入贯孔121及接地贯孔122的侧壁。种子层123的材料可例如是铜或铜合金。一实施例中,种子层可使用溅镀(sputtering)形成;其它实施例中,可使用物理蒸镀(physical vapor deposition,PVD)或电镀。
如图32C所示,可使用导电材料填满馈入贯孔121及接地贯孔122,形成一接地元件632及一第一子馈入元件660a,导电材料例如是铜、铝、锡、镍、金或银。
如图32D所示,形成整合电路部610于硅基板。整合电路部610可包括一个或多个晶体管、二极管、电感、电阻及其它电路元件。形成一接地部670及一馈入接点111a于整合电路部610内。本实施例中,馈入贯孔121及接地贯孔122使用”贯孔先形成”方式完成,亦即,馈入贯孔121及接地贯孔122可以形成于整合电路部610形成之前。接地元件632电性连接于接地部670,且第一子馈入元件660a电性连接于馈入接点111a。此外,数个接触垫及一重布层(未绘示)可设于于整合电路部610并且电性连接于整合电路部610。
如图32E所示,使用磨削,移除硅基板620的一部分。硅基板620的上表面620u从接地元件632及第一子馈入元件660a露出。
如图32F所示,一第一共形屏蔽膜631覆盖硅基板620的上表面620u。第一共形屏蔽膜631及接地元件632形成后,接地元件632电性连接于整合电路部610与第一共形屏蔽膜631。此外,第一共形屏蔽膜631具有一开孔631a,其露出第一子馈入元件660a。
如图32G所示,形成一电性接点614a于整合电路部610的接触垫上。然后,如图18所示,设置半导体芯片于邻近第二基板680的上表面680u,其中,整合电路部610通过电性接点614a与第二基板680电性连接。然后,形成介电结构140包覆第一共形屏蔽膜631、第二基板680的上表面680u及半导体芯片。接下来的步骤相似于半导体封装件600,容此不再赘述。
请参照图33A至图33F,其绘示图19的半导体封装件的制造过程图。
如图33A所示,形成一馈入贯孔121及一接地贯孔122于硅基板620及整合电路部610,亦即,馈入贯孔121及接地贯孔122从整合电路部610的一表面(接触垫形成于该表面上)延伸至硅基板620,然而馈入贯孔121及接地贯孔122之后端(back end)未从硅基板620的上表面620u露出。本实施例中,可使用深反应式离子蚀刻法(RIE)形成馈入贯孔121及接地贯孔122于整合电路部610。此外,接地贯孔122可使用激光去除技术(1aser ablation)形成接地贯孔122于硅基板620。
如图33B所示,一薄种子层123形成于馈入贯孔121及接地贯孔122。种子层的材料可使用铜或铜合金。一实施例中,种子层可使用溅镀方式形成;其它实施例中,可使用物理蒸镀(physical vapor deposition,PVD)或电镀。
如图33C所示,可使用导电材料填满馈入贯孔121及接地贯孔122,形成一接地元件632及一第一子馈入元件660a,导电材料例如是铜、铝、锡、镍、金或银。接地元件632通过第一金属层633电性连接于整合电路部610的接地部670,且第一子馈入元件660a通过第二金属层661电性连接于整合电路部610的馈入接点111a。此外,接地元件632及第一子馈入元件660a的形成可于同一工艺中一并完成。
如图33D所示,使用磨削的方式移除硅基板620的一部分,且接地元件632及第一子馈入元件660a的底端因此从硅基板620的上表面620u露出。
如图33E所示,形成一第一共形屏蔽膜631覆盖硅基板620的上表面620u。第一共形屏蔽膜631及接地元件632形成后,接地元件632电性连接整合电路部610与第一共形屏蔽膜631。此外,第一共形屏蔽膜631具有一开孔631a,第一子馈入元件660a从开孔631a露出。
如图33F所示,形成一电性接点614a于整合电路部610的接触垫上。然后,如图19所示,设置半导体芯片于邻近第二基板680的上表面680u。其中,整合电路部610通过电性接点614a与第二基板680电性连接。然后,形成介电结构140包覆第一共形屏蔽膜631、第二基板680的上表面680u及半导体芯片。然后,形成一第二子馈入元件660b,其中,第一子馈入元件660a与第二子馈入元件660b构成馈入元件660。然后,形成如图19所示的天线元件于介电结构140上,且形成一切割狭缝(未绘示)经过过介电结构140及第二基板680,以形成一如图19所示的半导体封装件700。
请参照图34A至图34E,其绘示图21的半导体封装件的制造过程图。
如图34A所示,提供一半导体芯片,半导体芯片包括一整合电路部610及一硅基板620。整合电路部610可包括一个或多个晶体管、二极管、电感、电容、电阻及其它电路元件。一接地部670及一馈入接点111a形成于整合电路部610内。此外,多个接触垫及一重布层(未绘示)设于整合电路部610上。
如图34B所示,形成第一共形屏蔽膜631覆盖硅基板620的上表面620u。第一共形屏蔽膜631具有开孔631a,其露出硅基板620的一部分,且其位置对应于馈入接点111a。
如图34C所示,经由形成一接地贯孔122于半导体芯片的硅基板620且使用导电材料填满接地贯孔122形成一接地元件632。第一共形屏蔽膜631覆盖接地元件632的一侧面,且接地元件632的上表面632u从第一共形屏蔽膜631露出。接地元件632电性连接于整合电路部610与第一共形屏蔽膜631。
如图34D所示,形成一介电结构140覆盖第一共形屏蔽膜631及接地元件632的上表面632u。
如图34E所示,经由形成一通过介电结构140、开孔631a与硅基板620的馈入贯孔121,然后使用导电材料填满馈入贯孔121,以形成一馈入元件160。其中,馈入元件160电性连接于整合电路部610。此外,经由形成一通过介电结构140的天线接地贯孔124,然后使用导电材料填满天线接地贯孔124,以形成天线接地件155,其中天线接地件155电性连接第一共形屏蔽膜631。然后,形成如图21所示的天线元件150于介电结构140,其中,天线元件150直接接触于馈入元件160。然后,邻近整合电路部610的下表面610b,形成如图21所示的电性接点114于介电结构140。形成一经过过介电结构140、第一共形屏蔽膜631、硅基板620及整合电路部610的切割狭缝(未绘示),以形成一如图21所示的半导体封装件900。一实施例中,电性接点114可于切割狭缝形成之前或之后形成。
请参照图35A至图35D,其绘示图22的半导体封装件的制造过程图。
如图35A所示,提供一半导体芯片,半导体芯片包括一整合电路部610及一硅基板620。整合电路部610可包括一个或多个晶体管、二极管、电感、电容、电阻及一接地部670。一馈入接点111a形成于整合电路部610内。
如图35B所示,经由形成一开孔于硅基板620且使用导电材料填满该开孔,以形成一接地元件632。然后,形成第一共形屏蔽膜631覆盖硅基板620的上表面620u,其中,第一共形屏蔽膜631覆盖接地元件632的侧面,且接地元件632的上表面从第一共形屏蔽膜631露出。接地元件632电性连接于整合电路部610的接地部670。
如图35C所示,形成封装体120覆盖整合电路部610及硅基板620。封装体120形成前,整合电路部610及硅基板620经由接垫613黏贴于载板380。封装体120形成后,可移除载板380,以露出接垫613及封装体120的下表面140b。
如图35D所示,形成重布层1080于整合电路部610及封装体120的下表面140b上。重布层1080包括一第一介电层1080a1、一图案化导电层1080a2及一第二介电层1080a3。第一介电层1080a1覆盖封装体120的下表面140b,且露出接垫613。图案化导电层1080a2覆盖第一介电层1080a1且电性连接于接垫613。第二介电层1080a3覆盖图案化导电层1080a2且露出第二介电层1080a3的一部分。
如图35D所示,采用例如是印刷、旋涂或喷涂的涂布技术形成一介电材料后,再以例如是上述图案化技术形成第一介电层1080a1,第二介电层1080a3的形成方法同第一介电层1080a1。采用材料形成技术形成一导电材料后,再以例如是图案化技术形成图案化导电层1080a2。
如图35D所示,经由形成一开孔于硅基板620及封装体120且使用导电材料填满该开孔以形成馈入元件160,其中,馈入元件160电性连接于整合电路部610的馈入接点611a。此外,经由形成一开孔于封装体120且使用导电材料填满该开孔以形成天线接地件155,其中,天线接地件电性连接于第一共形屏蔽膜631。然后,形成如图22所示的电性接点114于露出的图案化导电层1080a2,使得电性接点114电性连接于接垫113。然后,形成一经过过封装体120及重布层1080的切割狭缝(未绘示),以形成一如图22所示的半导体封装件1000。一实施例中,电性接点114可形成于切割狭缝形成之前或之后。
请参照图36A至图36E,其绘示图23的半导体封装件的制造过程图。
如图36A所示,提供一半导体芯片,半导体芯片包括一整合电路部610及一硅基板620。整合电路部610及硅基板620黏贴于载板380后,形成包覆半导体芯片的封装体1120。封装体1120形成后,移除载板380以露出整合电路部610的接垫613及封装体1120的下表面1120b。
如图36B所示,形成重布层1080于整合电路部610及封装体1120的下表面1120b。
如图36C所示,经由形成一通过硅基板620及封装体1120开孔且使用导电材料填满该开孔,以形成接地元件632,其中,接地元件632电性连接于整合电路部610的接地部670。然后,形成第一防电磁干扰膜331于邻近硅基板620的上表面。如第33C图所示,形成第一防电磁干扰膜331于封装体1120上,该封装体1120邻近硅基板620的上表面620u。
如图36D所示,形成介电结构140覆盖第一防电磁干扰膜331。
如图36E所示,经由形成一通过封装体1120及介电结构140贯孔且使用导电材料填满该贯孔,以形成馈入元件160。此外,经由形成一通过封装体1120的贯孔且使用导电材料填满该贯孔,以形成天线接地件155。然后,形成天线元件150于介电结构140的上表面140u。然后,形成如图23所示的一电性接点614于露出的图案化导电层1080a2,使电性接点614电性连接于接垫613。然后,形成一通过介电结构140、第一防电磁干扰膜331、封装体1120与重布层1080的切割狭缝,如此,形成图23所示的半导体封装件1100。一实施例中,电性接点614亦可形成于切割狭缝形成后。
请参照图37A至图37K,其绘示图24的半导体封装件的制造过程图。
如图37A所示,以例如是表面黏着技术设置一半导体装置112a及被动元件112b于邻近第一基板111的上表面111u。第一基板111包括接地部170及馈入接点111a。如图37A所示,以例如是表面黏着技术设置接地支架180于邻近第一基板111的上表面111u,其中接地支架180连接于接地部170。
如图37B所示,采用例如是打线技术,形成第一子馈入元件160c于馈入接点111a上。第一子馈入元件160c焊线材料。
如图37C所示,于基板111的上表面111u形成封装体120包覆半导体元件及第一子馈入元件160c。
如图37D所示,采用例如是磨削方法,移除部分封装体120,以露出第一子馈入元件160c。
如图37E所示,形成至少一第一切割狭缝T1经过封装体120及接地支架180,并切断接地支架180。本实施例中,第一切割狭缝T1经过部分封装体120。另一实施例中,第一切割狭缝T1亦可经过整个封装体120。再一实施例中,第一切割狭缝T1可经过整个封装体120及部分第一基板111。
如图37F所示,形成电磁干扰屏蔽元件130以覆盖封装体120的外侧面及从封装体120的外侧面露出的接地支架180。电磁干扰屏蔽元件130包括第一防电磁干扰膜131与接地元件132。本实施例中,电磁干扰屏蔽元件130露出第一子馈入元件160c。
如图37G所示,采用例如是打线技术,形成第二子馈入元件160d于第一子馈入元件160c上。第二子馈入元件160d焊线材料。第一子馈入元件160c与第二子馈入元件160d构成馈入元件160。此外,采用例如是打线技术,形成天线接地件155于电磁干扰屏蔽元件130上,天线接地件155焊线材料。
如图37H所示,形成介电结构140覆盖第二子馈入元件160d、电磁干扰屏蔽元件130及天线接地件155。
如图37I所示,形成开孔155r及160dr分别露出天线接地件155及第二子馈入元件160d。
如图37J所示,形成天线元件150于介电结构140的上表面140u,并直接与馈入元件160及天线接地件155接触,使天线元件150通过馈入元件160电性连接整合电路部110,且通过天线接地件155及电磁干扰屏蔽元件130电性连接于接地部170。天线元件150可使用例如是上述电镀/微影工艺形成。
如图37K所示,形成数道第二切割狭缝T2经过介电结构140及整个第一基板111,而如图24所示的半导体封装件1200。第二切割狭缝T2例如是以激光或其它切割刀具的方式形成。
请参照图38A至图38C,其绘示图25的半导体封装件的制造过程图。
如图38A所示,形成一介电材料层190覆盖介电结构140的上表面140u。
如图38B所示,形成开孔155r及160dr分别露出天线接地件155及第二子馈入元件160d。
如图38C所示,形成天线元件150于介电材料层190的上表面,并直接与馈入元件160及天线接地件155接触。然后,形成数道第二切割狭缝(未绘示)经过介电结构140及整个第一基板111,以形成至少一如图25所示的半导体封装件1300。
综上所述,虽然本发明已以至少一实施例揭露如上,然其并非用以限定本发明。本发明所属技术领域中具有通常知识者,在不脱离本发明的精神和范围内,当可作各种的更动与润饰。因此,本发明的保护范围当视权利要求书所界定者为准。
Claims (15)
1.一种半导体封装件,包括:
一基板;
一半导体芯片,设于该基板上;
一封装体,包覆该半导体芯片;
一电磁干扰屏蔽元件,形成于该封装体上;
一介电结构,包覆该电磁干扰屏蔽元件;
一介电材料层,覆盖该介电结构,其中,该介电材料层的介电系数高于该介电结构的介电系数;
一天线元件,形成于该介电结构上;
一馈入元件,连接该天线元件与该基板的一馈入接点;以及
数个天线接地元件,设于该介电结构内且直接连接该天线元件与该电磁干扰屏蔽元件,该数个天线接地元件还连接该天线元件与设于该半导体封装件的电位,其中该数个天线接地元件环绕该馈入元件。
2.如权利要求1所述的半导体封装件,其中该馈入元件贯穿该封装体与该介电结构。
3.如权利要求1所述的半导体封装件,更包括:
一接地支架,设于该基板上且连接该基板与电磁干扰屏蔽元件。
4.一种半导体封装件,包括:
一半导体芯片,该半导体芯片具有一整合电路部及一基板部,该整合电路部具有一主动面且该基板部具有一非主动面;
一贯孔,延伸自该主动面且电性连接于该整合电路部;
一电磁干扰屏蔽元件,设于该非主动面且电性连接于该贯孔;
一封装体,包覆该半导体芯片的一部分及该电磁干扰屏蔽元件的一部分,该封装体具有一上表面;
一馈入元件,贯穿该封装体及该基板部,且电性连接于该整合电路部;
一天线元件,设于该上表面且电性连接于该馈入元件;
数个天线接地元件,设于包覆该电磁干扰屏蔽元件的一介电结构内,且直接连接该天线元件与该电磁干扰屏蔽元件,该数个天线接地元件还连接该天线元件与设于该半导体封装件的电位,其中该数个天线接地元件环绕该馈入元件;以及
一介电材料层,覆盖该介电结构,其中,该介电材料层的介电系数高于该介电结构的介电系数。
5.如权利要求4所述的半导体封装件,其中该馈入元件包括一第一子馈入元件及一第二子馈入元件,该第一子馈入元件设于该基板部,该第二子馈入元件设于该封装体。
6.如权利要求5所述的半导体封装件,其中该第一子馈入元件一硅通孔。
7.如权利要求4所述的半导体封装件,其中该贯孔形成于该基板部的一硅通孔。
8.如权利要求4所述的半导体封装件,其中该封装体具有一开孔,该馈入元件从该开孔露出。
9.如权利要求4所述的半导体封装件,其中该馈入元件未直接接触该电磁干扰屏蔽元件。
10.如权利要求4所述的半导体封装件,更包括一重布层,设置且电性连接于该主动面。
11.如权利要求4所述的半导体封装件,更包括:
一接地支架,设于该基板部上且连接该基板部与该电磁干扰屏蔽元件。
12.一种半导体封装件,包括:
一半导体芯片,该半导体芯片具有一整合电路部及一基板部,该整合电路部具有一主动面且该基板部具有一非主动面;
一第一导通孔及一第二导通孔各形成于该半导体芯片且电性连接于该整合电路部;
一电磁干扰屏蔽元件,设于该非主动面且电性连接于该第一导电孔;
一介电结构,设于该电磁干扰屏蔽元件上;
一介电材料层,覆盖该介电结构,其中,该介电材料层的介电系数高于该介电结构的介电系数;
一馈入元件,其中该馈入元件包括一第一子馈入元件及一第二子馈入元件,该第一子馈入元件该第二导通孔,该第二子馈入元件设于介电结构;
一天线元件,设于该介电材料层上且电性连接于该馈入元件;以及
数个天线接地元件,设于该介电结构内且直接连接该天线元件与该电磁干扰屏蔽元件,该数个天线接地元件还连接该天线元件与设于该半导体封装件的电位,其中该数个天线接地元件环绕该馈入元件。
13.如权利要求12所述的半导体封装件,其中该馈入元件未直接接触该电磁干扰屏蔽元件。
14.如权利要求12所述的半导体封装件,其中该介电结构具有一开孔,该馈入元件从该开孔露出。
15.如权利要求12所述的半导体封装件,更包括一重布层,设置且电性连接于该主动面。
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US20130292808A1 (en) | 2013-11-07 |
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