CN108155178A - 集成扇出型封装 - Google Patents

集成扇出型封装 Download PDF

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Publication number
CN108155178A
CN108155178A CN201710140211.9A CN201710140211A CN108155178A CN 108155178 A CN108155178 A CN 108155178A CN 201710140211 A CN201710140211 A CN 201710140211A CN 108155178 A CN108155178 A CN 108155178A
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China
Prior art keywords
antenna
earth conductor
line structure
layer
out package
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Pending
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CN201710140211.9A
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English (en)
Inventor
张守仁
蔡仲豪
王垂堂
吴凯强
刘明凯
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN108155178A publication Critical patent/CN108155178A/zh
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Abstract

一种集成扇出型封装，其包括绝缘包封体、射频集成电路、天线、接地导体以及重布线路结构。射频集成电路包括多个导电端子。射频集成电路、天线及接地导体嵌于绝缘包封体中，且接地导体位于射频集成电路与天线之间。重布线路结构配置于绝缘封包体上，且重布线路结构与导电端子、天线以及接地导体电性连接。

Description

集成扇出型封装
技术领域
本发明的实施例涉及一种集成扇出型封装。
背景技术
由于不同电子组件(例如是晶体管、二极管、电阻、电容等)的集成度持续地增进，半导体工业经历了快速成长。大部分而言，集成度的增进是来自于最小特征尺寸(featuresize)上不断地缩减，这允许更多的较小组件能够被整合到一预定区域内。较小的电子组件会需要比以往体积更小的封装。一般而言，较小型的半导体组件封装包括有四面扁平封装(quad flat packages，QFPs)、引脚阵列(pin grid array，PGA)封装、球阵列(ball gridarray，BGA)封装等等。目前，集成扇出型封装由于其密实度(compactness)而趋于热门，且集成扇出型封装也逐渐被应用于射频集成电路(RF-IC)。在射频集成电路的封装技术中，如何将射频集成电路以及与射频集成电路搭配的天线整合在单一集成扇出型封装中，为研发人员关注的议题之一。
发明内容
本发明的实施例提供一种集成扇出型封装，其包括绝缘包封体、射频集成电路、天线、接地导体以及重布线路结构。射频集成电路包括多个导电端子。射频集成电路、天线及接地导体嵌于绝缘包封体中，且接地导体位于射频集成电路与天线之间。重布线路结构配置于绝缘封包体上，且重布线路结构与导电端子、天线以及接地导体电性连接。
附图说明
结合附图阅读以下详细说明，会最好地理解本发明的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸。
图1至图7为依照一些实施例所绘示的一种集成扇出型封装的制造流程。
图8为图1中图案化导电层的立体示意图。
图9为图4中图案化导电层以及部分重布线路结构的立体示意图。
图10至图14为依照不同实施例所绘示的图案化导电层以及部分重布线路结构的立体示意图。
[符号的说明]
C：载板
DB：剥离层
DI：介电层
100：集成扇出型封装
110、110’、110a～110e：图案化导电层
112、112’：天线
112a：第一天线部
112b：第二天线部
114、114’、114a～114c：接地导体
116：遮蔽环
120：射频集成电路
120a：有源表面
122：导电端子
124、124a：保护层
130：绝缘材料
130a：绝缘包封体
140：重布线路结构
142：内介电层
144：重布导电层
144a：球下金属层图案
144b：连接垫
150：导电球
160：无源组件
具体实施方式
以下公开内容提供用于实作所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及排列的具体实例以简化本公开内容。当然，这些仅为实例且不旨在进行限制。举例来说，以下说明中将第一特征形成于第二特征之上或第二特征上可包括其中第一特征及第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成有附加特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。另外，本公开内容可能在各种实例中重复参考编号及/或字母。这种重复是出于简洁及清晰的目的，而不是自身表示所论述的各种实施例及/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个组件或特征与另一(其他)组件或特征的关系。所述空间相对性用语旨在除图中所绘示的定向外还囊括装置在使用或操作中的不同定向。设备可具有其他定向(旋转90度或处于其他定向)且本文中所用的空间相对性描述语可同样相应地进行解释。
图1至图7为依照一些实施例所绘示的一种集成扇出型封装的制造流程，图8为图1中图案化导电层的立体示意图，而图9为图4中图案化导电层以及部分重布线路结构的立体示意图。
请参照图1，提供载板C，此载板C上具有剥离层DB以及介电层DI，其中剥离层DB与介电层DI依序堆叠于载板C上。意即，剥离层DB位于载板C以及介电层DI之间。在一些实施例中，载板C例如是玻璃基板，而剥离层DB例如是形成于玻璃基板上的光热转换(light-to-heat conversion,LTHC)释放层，且介电层DI例如为形成于剥离层DB上的聚苯恶唑(PBO)层。然而，本发明不限定载板C、剥离层DB以及介电层DI的材质。在其他可行的实施例中，介电层DI可被省略；换言之，仅有剥离层DB形成于载板C上。
如图1所示，接着，于介电层DI上形成图案化导电层110。在一些实施例中，前述的图案化导电层110是藉由种子层溅射(seed layer sputtering)、微影、镀覆、刻蚀以及光刻胶移除工艺所形成。详言之，图案化导电层110的制作方法包括下列步骤。首先，可于介电层DI的表面上以溅射方式形成种子层(例如，钛/铜种子层)，之后进行光刻胶的涂布，并以光刻(lithography)工艺将特定图案转移至光刻胶上，以使种子层的部分区域能够被光刻胶所暴露。随后，以经图案化后之光刻胶为掩模进行镀覆工艺，以使导电材料能够被镀覆于被光刻胶所暴露出的种子层上。之后，再以镀覆形成之导电材料为掩模，将未被导电材料所覆盖的种子层移除以完成图案化导电层110的制作。举例来说，前述图案化导电层110的材料包括铜或其他合适的金属。
请参照图1与图8，图案化导电层110至少包括相互电性绝缘的至少一个天线112以及至少一个接地导体114。图1中绘示出二个天线112以及四个接地导体114作为示例，然而，本发明并不限定天线112与接地导体114的数量，前述天线112与接地导体114的数量可依据实际的设计需求而作出适当的更动。在一些实施例中，所述至少一个天线112例如为偶极子天线(Dipole antenna)，而所述至少一个天线112包括相互分离的第一天线部112a以及一第二天线部112b，且第一天线部112a以及第二天线部112b例如皆为L形之天线部，如图8所示。所述至少一个接地导体114例如为一个或是多个相互平行之板状接地导体。然而，本发明并不限定第一天线部112a、第二天线部112b以及接地导体114的形状，前述第一天线部112a、第二天线部112b以及接地导体114的形状可依据实际的设计需求而作出适当的更动。所述至少一个接地导体114除了提供天线112所需的接地功能之外，所述至少一个接地导体114亦可具有反射电磁波的功能，以反射来自于天线112(即第一天线部112a以及一第二天线部112b)所发出的电磁波。换言之，所述至少一个接地导体114可被视为电磁波反射件，且此电磁波反射件与天线112电性绝缘。在其他可行的实施例中，图案化导电层110可进一步包括多个用以与重布导电层144(绘示于图4)电性连接的导电柱体(conductive vias)。
由于图案化导电层110中的天线112与接地导体114是藉由同一镀覆工艺所制作，因此天线112与接地导体114的材质与高度实质相同。
在其他可行的实施例中，图案化导电层110除了包括相互电性绝缘的天线112以及接地导体114之外，图案化导电层110可进一步包括导电柱体(未绘示)。值得注意的是，导电柱体可与天线112以及接地导体114一并制作。换言之，导电柱体、天线112以及接地导体114可藉由同一镀覆工艺形成，且导电柱体、天线112以及接地导体114可为相同材质。
请参照图2，将一个射频集成电路120拾取并且放置于介电层DI上，以使各个接地导体114分别位于射频集成电路120与对应的天线112之间。射频集成电路120具有多个导电端子122以及保护层124，其中导电端子122例如为铜柱体(copper pillars)或其他适合的导电柱体(conductive pillars)，导电端子122分布于射频集成电路120的有源表面120a上，而保护层124位于射频集成电路120的有源表面120a上，以覆盖住前述的导电端子122。举例而言，射频集成电路120是藉由管芯附着膜(die attach film,DAF)、黏附膏等方式附着或黏附于介电层DI上。在其他可行的实施例中，可将多个射频集成电路120拾取并且放置到介电层DI上，其中被拾取并且放置于介电层DI上的射频集成电路120可排列成阵列。当被设置于介电层DI上的射频集成电路120被排列成阵列时，天线112与接地导体114的使用数量为多个，且前述之天线112与接地导体114可被分成多个群组。射频集成电路120的数目对应于天线112以及接地导体114的群组数目。
如图2所示，保护层124的顶表面例如是低于天线112与接地导体114的顶表面，且保护层124的顶表面例如是高于导电端子122的顶表面。然而，本发明并不仅限于此。在另一些实施例中，保护层124的顶表面可以实质上对准天线112与接地导体114的顶表面，且保护层124的顶表面可高于导电端子122的顶表面。
如图2所示，一个或多个射频集成电路120可在天线112与接地导体114形成之后才被设置于介电层DI上。然而，本发明并不仅限于此。在其他可行的实施例中，一个或多个射频集成电路120可在天线112与接地导体114形成之前被设置于介电层DI上。
在完成射频集成电路120的设置以及天线112与接地导体114的制作之后，于介电层DI上形成绝缘材料130以覆盖住射频集成电路120、天线112与接地导体114。在一些实施例中，绝缘材料130是由模塑工艺(molding process)所形成的封装胶体(moldingcompound)。射频集成电路120的导电端子122以及保护层124被绝缘材料130所包覆或覆盖。换言之，射频集成电路120的导电端子122以及保护层124在此阶段并不会被显露出来而获得一定程度的保护。在一些实施例中，前述之绝缘材料130例如为环氧化合物或其他合适的树脂。
请参照图2与图3，接着，对绝缘材料130进行研磨直到天线112、接地导体114、导电端子122以及保护层124的顶表面被暴露出来。在一些实施例中，前述绝缘材料130的研磨工艺包括机械研磨(mechanical grinding)及/或化学机械抛光(chemical mechanicalpolishing,CMP)。
在绝缘材料130被研磨之后，绝缘包封体130a会形成于介电层DI上，且在对绝缘材料130进行研磨工艺期间，部分的保护层124会被研磨而形成保护层124a。在一些实施例中，在对绝缘材料130以及保护层124进行研磨工艺期间，天线112与接地导体114也会被部分研磨而形成天线112’与接地导体114’。如图3所示，经过研磨后的天线112’与接地导体114’即构成图案化导电层110’。
如图3所示，经过研磨后的绝缘包封体130a会包覆射频集成电路120的侧壁，且绝缘包封体130a被天线112’及接地导体114’所贯穿。换言之，射频集成电路120、天线112’以及接地导体114’会嵌于绝缘包封体130a之中。值得注意的是，经过研磨后的天线112’与接地导体114’(或电磁波反射件)的高度与经过研磨后的绝缘包封体130a的高度实质上相同。
请参照图4至图5以及图9，在形成绝缘包封体130a之后，于绝缘包封体130a、天线112’、接地导体114’以及保护层124a上形成重布线路结构140。如图4与图5所示，本实施例之重布线路结构140包括彼此交替堆叠的多个内介电层(inter-dielectric layers)142以及多个重布导电层144，且重布导电层144会与射频集成电路120的导电端子122以及嵌于绝缘包封体130a中的天线112’及接地导体114’电性连接。如图4与图9所示，最底层的内介电层142局部覆盖于绝缘包封体130a、天线112’、接地导体114’以及保护层124a上，以将天线112’、接地导体114’以及导电端子122的部分区域暴露，而最底层的重布导电层144则配置于最底层的内介电层142上。最底层的内介电层142可具有多个暴露出天线112’、接地导体114’以及导电端子122的接触开口。此外，嵌于绝缘包封体130a中的天线112’可透过最底层的重布导电层144与射频集成电路120的导电端子122电性连接，且嵌于绝缘包封体130a中的多个接地导体114’可透过最底层的重布导电层144彼此相互连接。在其他可行的实施例中，嵌于绝缘包封体130a中的多个接地导体114’亦可透过最底层的重布导电层144而与射频集成电路120的导电端子122(即接地端子)电性连接。
图10至图14为依照不同实施例所绘示的图案化导电层以及部分重布导电层的立体示意图。请参照图10，本实施例之图案化导电层110a包括多组天线112’以及多个接地导体114a，其中每个接地导体114a分布于一组对应的天线112’与射频集成电路120之间，而天线112’透过部分的重布导电层144与射频集成电路120电性连接，且接地导体114a透过部分的重布导电层144彼此电性连接。如图10所示，四组天线112’分别分布于射频集成电路120的四侧，且四个接地导体114a分别平行于射频集成电路120的四个侧边而设置。然而，本实施例不限定天线112’与接地导体114a的数量。
请参照图11，本实施例之图案化导电层110b包括多组天线112’以及多个接地导体114b，其中每个接地导体114b分布于一组天线112’与射频集成电路120之间，而天线112’透过部分的重布导电层144与射频集成电路120电性连接，且接地导体114b透过部分的重布导电层144彼此电性连接。如图11所示，四组天线112’分别分布于射频集成电路120的四侧，而四个接地导体114b分别具有朝向各组天线112’的凹口，且四个接地导体114b沿着射频集成电路120的四个侧边设置。然而，本实施例不限定天线112’与接地导体114b的数量。
请参照图12，本实施例之图案化导电层110c包括多组天线112’、多个接地导体114a以及多个接地导体114c，其中每个接地导体114a分布于对应的一组天线112’与射频集成电路120之间，接地导体114c对应于射频集成电路120的角落分布，且各个接地导体114c可用以分隔与其相邻的两组天线112’。天线112’透过部分的重布导电层144与射频集成电路120电性连接，且接地导体114a以及接地导体114c透过部分的重布导电层144彼此电性连接。如图12所示，四组天线112’分别分布于射频集成电路120的四侧，四个接地导体114a分别平行于射频集成电路120的四个侧边而设置。然而，本实施例不限定天线112’、接地导体114a以及接地导体114c的数量。
请参照图13，本实施例之图案化导电层110d包括多组天线112’、多个接地导体114a以及遮蔽环(shielding ring)116，其中每个接地导体114a分布于一组对应的天线112’与射频集成电路120之间，遮蔽环116环绕射频集成电路120并且位于接地导体114a与射频集成电路120之间，以遮蔽射频集成电路120对于各组天线112’的干扰。天线112’透过部分的重布导电层144与射频集成电路120电性连接，且接地导体114a透过部分的重布导电层144彼此电性连接。如图13所示，四组天线112’分别分布于射频集成电路120的四侧，四个接地导体114a分别平行于射频集成电路120的四个侧边而设置，且遮蔽环116的尺寸略大于射频集成电路120的尺寸。然而，本实施例不限定天线112’、接地导体114a以及遮蔽环116的数量。
请参照图14，本实施例之图案化导电层110e包括多组天线112’以及遮蔽环116，其中遮蔽环116接地，遮蔽环116分布于各组天线112’与射频集成电路120之间，且遮蔽环116环绕射频集成电路120以遮蔽射频集成电路120对于各组天线112’的干扰。在图14所绘示的实施例中，由于遮蔽环116接地，因此遮蔽环116可以被视为接地导体。天线112’透过部分的重布导电层144与射频集成电路120电性连接。如图14所示，四组天线112’分别分布于射频集成电路120的四侧，且接地的遮蔽环116的尺寸略大于射频集成电路120的尺寸。然而，本实施例不限定天线112’以及遮蔽环116的数量。
如图5所示，重布线路结构140中最顶层的重布导电层144包括多个接垫。在一些实施例中，前述之接垫包括用来植球(ball mount)的多个球下金属层(under-ballmetallurgy,UBM)图案144a及/或用来设置无源组件的至少一个连接垫144b。本发明并不限制球下金属层图案144a以及连接垫144b的数目。
请参照图6，在形成重布线路结构140之后，将多个导电球150置于球下金属层图案144a上，并将至少一个无源组件160设置于连接垫144b上。在一些实施例中，导电球150可以植球工艺的方式被设置于球下金属层图案144a上，而无源组件160可设置于连接垫144b上并且藉由焊料与连接垫144b电性连接。导电球150透过重布线路结构140与多个天线112’、接地导体114’以及射频集成电路120的导电端子122中的至少一者电性连接。此外，无源组件160透过重布线路结构140与多个天线112’、接地导体114’以及射频集成电路120的导电端子122中的至少一者电性连接。
参照图6以及图7，在将导电球150以及无源组件160设置于重布线路结构140之后，将形成于绝缘包封体130a的表面上的介电层DI从剥离层DB上剥离，以使介电层DI与剥离层DB以及载板C分离。在一些实施例中，前述剥离层DB(例如光热转换释放层)可被紫外光雷射照射而使介电层DI从载板C上剥离。如图7所示，在形成导电球150与无源组件160之后，射频集成电路120的集成扇出型封装100便已初步完成。
在前述的实施例中，由于射频集成电路120与天线112’是嵌于集成扇出型封装100的绝缘包封体130a之中，因此天线112’不会占据重布线路结构140中的布线面积，使得重布线路结构140具有较佳的线路布局弹性。此外，由于绝缘包封体130a具有一定的厚度及/或体积以容纳天线112’以及射频集成电路120，因此射频集成电路120与天线112’的整合不会导致集成扇出型封装的体积大幅增加。
在本发明的实施例中，由于射频集成电路与天线是嵌于集成扇出型封装的绝缘包封体之中，因此天线的整合不会影响到集成扇出型封装中的重布线路结构的线路布局弹性。
本发明的一实施例提供一种集成扇出型封装，其包括绝缘包封体、射频集成电路、天线、接地导体以及重布线路结构。射频集成电路包括多个导电端子。射频集成电路、天线及接地导体嵌于绝缘包封体中，且接地导体位于射频集成电路与天线之间。重布线路结构配置于绝缘封包体上，且重布线路结构与导电端子、天线以及接地导体电性连接。
在所述的集成扇出型封装中，天线包括偶极子天线。
在所述的集成扇出型封装中，天线与接地导体的高度实质相同。
在所述的集成扇出型封装中，接地导体包括电磁波反射件。
在所述的集成扇出型封装更包括多个导电球，导电球配置于重布线路结构上且与重布线路结构电性连接，其中导电球透过重布线路结构与天线、接地导体以及射频集成电路的导电端子中的至少一者电性连接。
在所述的集成扇出型封装更包括至少一个无源组件，无源组件配置于重布线路结构上且与重布线路结构电性连接，其中无源组件透过重布线路结构与天线、接地导体以及射频集成电路的导电端子中的至少一者电性连接。
所述的集成扇出型封装更包括遮蔽环，其中遮蔽环环绕射频集成电路，且遮蔽环位于接地导体与射频集成电路之间。
所述的集成扇出型封装中，接地导体包括遮蔽环以环绕射频集成电路。
本发明的另一实施例提供一种集成扇出型封装，其包括绝缘包封体、射频集成电路、多个天线、多个电磁波反射件以及重布线路结构。射频集成电路包括多个导电端子。射频集成电路、天线及电磁波反射件嵌于绝缘包封体中，而各个电磁波反射件分别位于射频集成电路与对应的天线之间以反射对应的天线所发出的电磁波。重布线路结构配置于绝缘封包体上，重布线路结构与导电端子、天线以及电磁波反射件电性连接，且多个电磁波反射件透过重布线路结构彼此相连接。
在所述的集成扇出型封装中，天线包括偶极子天线。
在所述的集成扇出型封装中，电磁波反射件与天线电性绝缘，且电磁波反射件接地。
在所述的集成扇出型封装中，天线、电磁波反射件以及绝缘包封体的高度实质相同。
在所述的集成扇出型封装更包括多个导电球，导电球配置于重布线路结构上且与重布线路结构电性连接，其中导电球透过重布线路结构与天线、接地导体以及射频集成电路的导电端子中的至少一者电性连接。
在所述的集成扇出型封装更包括至少一个无源组件，无源组件配置于重布线路结构上且与重布线路结构电性连接，其中无源组件透过重布线路结构与天线、接地导体以及射频集成电路的导电端子中的至少一者电性连接。
所述的集成扇出型封装更包括遮蔽环，其中遮蔽环环绕射频集成电路，且遮蔽环位于电磁波反射件与射频集成电路之间。
本发明的又一实施例提供一种集成扇出型封装的制造方法，包括下列步骤：于载板上形成图案化导电层，其中图案化导电层包括相互电性绝缘的天线以及接地导体；于载板上设置射频集成电路，射频集成电路包括多个导电端子，且接地导体位于射频集成电路与天线之间；于载板上形成绝缘包封体，以使射频集成电路、天线以及接地导体嵌于绝缘包封体中；以及于绝缘封包体上形成重布线路结构，其中重布线路结构与导电端子、天线以及接地导体电性连接，且天线透过重布线路结构与导电端子电性连接。
在集成扇出型封装的制造方法中，天线以及接地导体藉由同一镀覆工艺所形成。
在集成扇出型封装的制造方法中，射频集成电路是在天线与接地导体形成之前被设置于载板上。
在集成扇出型封装的制造方法中，射频集成电路是在天线与接地导体形成之后被设置于载板上。
集成扇出型封装的制造方法更包括：在形成重布线路结构之后，令载板与绝缘封包体分离。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本发明的各个方面。所属领域中的技术人员应知，他们可容易地使用本发明作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或达成与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，该些等效构造并不背离本发明的精神及范围，而且他们可在不背离本发明的精神及范围的条件下对其作出各种改变、代替及变更。

Claims (1)

1.一种集成扇出型封装，其特征在于，包括：
绝缘包封体；
射频集成电路，包括多个导电端子；
天线；
接地导体，其中该射频集成电路、所述天线及所述接地导体嵌于所述绝缘包封体中，且所述接地导体位于所述射频集成电路与所述天线之间；以及
重布线路结构，配置于所述绝缘封包体上，且所述重布线路结构与所述导电端子、所述天线以及所述接地导体电性连接。
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