CN111952201B - 一种嵌入式封装基板的制造方法 - Google Patents
一种嵌入式封装基板的制造方法 Download PDFInfo
- Publication number
- CN111952201B CN111952201B CN202010677083.3A CN202010677083A CN111952201B CN 111952201 B CN111952201 B CN 111952201B CN 202010677083 A CN202010677083 A CN 202010677083A CN 111952201 B CN111952201 B CN 111952201B
- Authority
- CN
- China
- Prior art keywords
- layer
- insulating layer
- double
- sided
- photosensitive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 238000004806 packaging method and process Methods 0.000 title abstract description 18
- 229910052751 metal Inorganic materials 0.000 claims abstract description 34
- 239000002184 metal Substances 0.000 claims abstract description 34
- 239000011810 insulating material Substances 0.000 claims abstract description 30
- 239000011521 glass Substances 0.000 claims abstract description 27
- 239000002390 adhesive tape Substances 0.000 claims abstract description 9
- 239000011248 coating agent Substances 0.000 claims abstract description 8
- 238000000576 coating method Methods 0.000 claims abstract description 8
- 238000007747 plating Methods 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 31
- 229920005989 resin Polymers 0.000 claims description 15
- 239000011347 resin Substances 0.000 claims description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 13
- 229910052802 copper Inorganic materials 0.000 claims description 13
- 239000010949 copper Substances 0.000 claims description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 239000004642 Polyimide Substances 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 5
- 229920001955 polyphenylene ether Polymers 0.000 claims description 5
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 claims description 4
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims description 4
- 238000002834 transmittance Methods 0.000 claims description 4
- JYEUMXHLPRZUAT-UHFFFAOYSA-N 1,2,3-triazine Chemical compound C1=CN=NN=C1 JYEUMXHLPRZUAT-UHFFFAOYSA-N 0.000 claims description 3
- XQUPVDVFXZDTLT-UHFFFAOYSA-N 1-[4-[[4-(2,5-dioxopyrrol-1-yl)phenyl]methyl]phenyl]pyrrole-2,5-dione Chemical compound O=C1C=CC(=O)N1C(C=C1)=CC=C1CC1=CC=C(N2C(C=CC2=O)=O)C=C1 XQUPVDVFXZDTLT-UHFFFAOYSA-N 0.000 claims description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 239000011651 chromium Substances 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229920003192 poly(bis maleimide) Polymers 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 229910052720 vanadium Inorganic materials 0.000 claims description 3
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium atom Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 claims description 3
- 239000006117 anti-reflective coating Substances 0.000 claims description 2
- 238000010030 laminating Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 239000003822 epoxy resin Substances 0.000 claims 1
- 230000000149 penetrating effect Effects 0.000 claims 1
- 229920000647 polyepoxide Polymers 0.000 claims 1
- 239000010410 layer Substances 0.000 description 73
- 239000000463 material Substances 0.000 description 10
- 229910000679 solder Inorganic materials 0.000 description 6
- 238000011161 development Methods 0.000 description 5
- 230000018109 developmental process Effects 0.000 description 5
- 238000005553 drilling Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 238000012536 packaging technology Methods 0.000 description 3
- 238000004381 surface treatment Methods 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 230000031700 light absorption Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 229920001169 thermoplastic Polymers 0.000 description 2
- 239000004416 thermosoftening plastic Substances 0.000 description 2
- 239000004721 Polyphenylene oxide Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- 238000009432 framing Methods 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000003384 imaging method Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000005022 packaging material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920006380 polyphenylene oxide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 230000011218 segmentation Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6835—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during build up manufacturing of active devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
- H01L2221/68386—Separation by peeling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
- H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
- H01L2224/214—Connecting portions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
本发明公开了一种嵌入式封装基板的制造方法,包括以下步骤:a)在玻璃承载板的上表面上贴附双面胶带;b)将器件贴附在双面胶带上;c)在双面胶带上涂覆感光性绝缘材料,形成器件嵌埋在其中的绝缘层;d)从玻璃承载板的上下两面对绝缘层的感光性绝缘材料进行曝光并显影形成第一图案;e)移除玻璃承载板;f)在所述绝缘层的表面上和所述第一图案中镀覆金属,形成在绝缘层上的金属层和在绝缘层中的金属柱;和g)在所述金属层上形成布线层。
Description
技术领域
本发明涉及电子器件封装结构,具体涉及无预置框架的嵌入式封装基板制造方法。
背景技术
在电子行业,尤其是消费电子行业中,越来越多的高密度,多功能和小型化的封装需求给芯片封装都带来了新的挑战,很多新的封装技术应运而生,包括嵌入式封装技术,嵌入式封装技术是把电阻、电容、电感等无源器件甚或是IC芯片等有源器件埋入到封装基板内部。这种做法可以缩短器件相互之间的线路长度,改善电气特性,而且还能进一步缩小芯片的尺寸面积,从而提高封装的可靠性,并降低成本,是一种非常理想的高密度封装技术。
嵌入式封装基板通过将芯片直接嵌埋在封装基板中,可以节省后续的封装环节,缩短芯片交期,提升行业效率,明显节约成本。同时,直接嵌埋也使得产品尺寸更小,对电路信号的损耗也进一步减小,提升了芯片的性能。
US9240392公开了一种利用预置芯片嵌埋框架通过形成铜通孔柱制造嵌入式封装基板的方法。该方法首先通过铜通孔柱工艺形成芯片嵌埋框架,框架内包含至少一个芯片放置口框和上下表面的铜通孔柱,将芯片放入嵌埋框架的口框内后利用热固性绝缘材料进行封装和再布线完成多层线路制作,层间导通通常采用激光开孔填铜或通过形成铜通孔柱的方式实现层间电导通。该方法可以获得更高密度的通孔,通孔直径小至30微米是可能的,并且各种几何形状的通孔可以在同一层内共同制造,因此可以进一步缩小芯片封装,缩短与外界的连接,消除芯片到基板的组装过程并可提高可靠性。
然而,在此种嵌入式封装基板制作过程中,预置埋芯框架是必不可少的步骤。但是,预先制作预置框架的步骤无疑会增加制作的成本和延长生产时间。而且,预置埋芯框架的制造过程中由于需要进行磨板,存在玻纤暴露的风险,容易导致出现线路短路。此外,现有技术的嵌入式封装基板制造方法常常需要对嵌埋器件的绝缘层进行诸如磨板、蚀刻或激光钻孔等流程,容易造成芯片损伤,因此也需要一种对嵌埋器件不施加物理机械力的方法。
发明内容
本发明的实施方案意图解决上述技术问题,为此提供一种嵌入式封装基板的制造方法。本发明通过利用感光性绝缘材料作为器件嵌埋层的封装材料,节省了预置框架步骤,实现了器件的直接嵌埋。
本发明涉及一种嵌入式封装基板的制造方法,包括以下步骤:
a)在玻璃承载板的上表面上贴附双面胶带;
b)将器件贴附在双面胶带上;
c)在双面胶带上涂覆感光性绝缘材料,形成器件嵌埋在其中的绝缘层;
d)从玻璃承载板的上下两面对绝缘层的感光性绝缘材料进行曝光并显影形成第一图案;
e)移除玻璃承载板;
f)在所述绝缘层的表面上和所述第一图案中镀覆金属,形成在绝缘层上的金属层和在绝缘层中的金属柱;和
g)在所述金属层上形成布线层。
在一些实施方案中,步骤a还包括在玻璃承载板的下表面施加抗反射涂层。
在一些实施方案中,所述感光型绝缘材料选自包括聚酰亚胺感光树脂或聚苯醚感光树脂的组别。
在一些实施方案中,所述器件选自集成电路、无源器件和有源器件中的至少其一。
在一些实施方案中,所述器件选自单颗芯片或背对背堆叠的多颗芯片。
在一些实施方案中,所述器件包括单面端子器件或双面端子器件。
在一些实施方案中,步骤e包括通过加热使双面胶带失去粘性来移除玻璃承载板。
在一些实施方案中,所述方法还包括在步骤f前,在所述绝缘层的一面或两面上施加种子层。
在一些实施方案中,所述种子层选自钛、镍、钒、铜、铝、钨、铬、银和金中的至少一种。
在一些实施方案中,步骤f包括在所述绝缘层的表面上和所述第一图案中镀覆铜或铝。
在一些实施方案中,步骤g包括在所述绝缘层的一面或两面上涂布光刻胶层并图案化,在所得图案中填充铜形成布线层。
在一些实施方案中,所述方法还包括在步骤g之后,在所述布线层上增层形成附加层。在一些实施方案中,所述附加层通过层压绝缘材料形成,该绝缘材料包括半固化片、ABF(膜状有机树脂)、聚酰亚胺、环氧树脂、双马来酰亚胺/三嗪树脂、聚苯醚、苯并环丁烯树脂或它们的共混物。
附图说明
为了更好地理解本发明并示出本发明的实施方式,以下纯粹以举例的方式参照附图。
具体参照附图时,必须强调的是特定的图示是示例性的并且目的仅在于说明性地讨论本发明的优选实施方案,并且基于提供被认为是对于本发明的原理和概念方面的描述最有用和最易于理解的图示的原因而被呈现。就此而言,没有试图将本发明的结构细节以超出对本发明基本理解所必须的详细程度来图示;参照附图的说明使本领域技术人员认识到本发明的几种形式可如何实际体现出来。在附图中:
图1(a)~1(k)示出本发明的无预置框架的嵌入式封装基板的制造方法的各个步骤的中间结构的截面示意图;
图2示出利用图1所示的方法制造的具有多层互连结构的嵌入式封装基板的截面示意图。
具体实施方式
参照图1(a)~1(k),示出无预置框架的嵌入式封装基板100的制造方法的各个步骤的中间结构的截面示意图。
无预置框架的嵌入式封装基板100的制造方法包括如下步骤:准备临时承载板110—步骤(a),如图1(a)所示。临时承载板110通常是透明玻璃承载板,使用具有高透光性、低反射率的玻璃作为临时承载板。临时承载板是在基板制作过程中起到临时键合,叠成和承托的作用。玻璃承载板110具有两个表面,其中一面是上表面111,相对一面是下表面112。优选在玻璃承载板110的下表面112上进行表面抗反射处理,施加抗反射涂层120,作用是在曝光机进行曝光时减少反射,增强光的吸收。
接着,在临时玻璃承载板110的上表面111上施加贴附双面胶带130—步骤(b),如图1(b)所示。双面胶带130的一面固定贴附在玻璃承载板110上,另一面用于将待嵌埋的器件临时固定在指定位置。通常,双面胶带130是市售的透明膜,其表面可以通过加热至一定温度或暴露于紫外光等而分解,使得胶带表面的粘性失效,从而便于进行后续的分离操作。此外,双面胶带130可以允许光穿过胶带以进行成像对准或者曝光。
然后,将器件140贴装在双面胶带130上—步骤(c),如图1(c)所示。器件103可以是集成电路、无源器件或有源器件中的至少其一,例如可以是功率器件,也可以是射频或逻辑芯片,亦或是电容、电阻、电感等。器件140可以是单颗芯片器件或背对背堆叠(3D堆叠)的多颗芯片器件。器件140可以是单面端子器件或双面端子器件,例如可以是单面导电,也可以是双面导电或单面散热等。图中示出的器件140为单面端子器件,其中包含端子143的器件140的端子面142贴附在双面胶带130上,端子面142可以朝下或朝上,视具体设计要求而定。可以通过贴装机将器件140贴附在双面胶带130上,安装精度可根据贴装机台的精度而定。
接着,在双面胶带130和器件140上涂覆感光性绝缘材料,形成器件140嵌埋在其中的绝缘层150—步骤(d),如图1(d)所示。通常,使用感光性绝缘材料作为封装绝缘材料150,通过压合或涂覆的方式将器件140和胶带130的表面完全覆盖,感光性绝缘材料形成的绝缘层150的厚度至少应与器件140的背面141齐平,至多可达150微米以上。感光绝缘层150具有两个表面,其中与双面胶带130完全附着的为下表面152,相对的一面为上表面151。
本发明使用的感光性绝缘材料通常是聚酰亚胺感光树脂或聚苯醚感光树脂,例如Microsystems HD-4100、Hitachi PVF-02等。
然后,从玻璃承载板110的上下两面对绝缘层150的感光性绝缘材料进行曝光并显影形成第一图案170—步骤(e),如图1(e)所示。可以利用玻璃承载板110的高透光性,根据设计的图案,用曝光机对感光性绝缘材料150的上下表面进行双面曝光,将除盲孔位置外的其它位置曝光固化,显影得到第一图案170后,将第一图案170中盲孔位置的感光性绝缘材料去除,形成器件上的盲孔171以及在非器件区域的盲孔172和173,其中盲孔172和173位置可以完全重叠。
本发明采取双面曝光的方式可以允许使用厚度较大的感光性绝缘层150,例如厚达150微米以上。传统单面曝光对于100微米以上厚度的感光性绝缘材料会出现明显的曝光不足。本发明采用高透光的玻璃承载板110,使得双面曝光成为可能,由此可以使较厚的感光性绝缘材料曝光区域完全固化,可以满足厚度较大的器件的嵌埋需求。进一步地,可以在玻璃承载板110的下表面上施加抗反射涂层120,使得从玻璃承载板110一侧对感光性绝缘材料150进行曝光时,可以减小光反射和增强光吸收,进一步减小下表面曝光不足的风险。
接着,移除临时玻璃承载板110—步骤(f),如图1(f)所示。在感光性绝缘层150固化形成具有刚性的基板100后,可以移除临时玻璃承载板110。可以通过加热移加热到一定温度或施加特定紫外光照射等方式,使双面胶带130的表面粘性失效,从而方便地进行分板操作。如图所示例中,通过分板操作,移除包含双面胶带130的临时玻璃承载板110,露出器件140的下表面(端子面)142、端子143、盲孔173和绝缘层150的下表面152,其中器件的下表面142和绝缘层150的下表面152处于同一平面上。
然后,在绝缘层150的上下表面151、152上和盲孔171、172、173内形成金属种子层180—步骤(g),如图1(g)所示。通常,可以通过化学镀或者溅射的方式在绝缘层150的表面151、152上和盲孔171、172、173内形成一层金属种子层180。通常,金属种子层180包括钛、镍、钒、铜、铝、钨、铬、银和金中的至少一种,但不仅限于上述金属。
接着,在金属种子层180上镀覆金属,形成在绝缘层上的金属层190和在绝缘层中的金属柱191—步骤(h),如图1(h)所示。通常,可以采用电镀金属的方式在种子层180上施加金属层190、191,得到表面金属层190和盲孔金属层191。盲孔金属层191可以是实心金属柱,也可以是边缘镀覆金属的空心金属柱。镀覆的金属一般为铜、铝一类的导电金属,但不限于上述金属。
然后,在金属层190上施加光刻胶层1100,通过曝光和显影形成布线层保护图案—步骤(i),如图1(i)所示。可以在基板100的上下金属层190上同时施加光刻胶层1100,例如感光干膜,其厚度可根据设计的线路厚度来选定。光刻胶层1100通过曝光和显影后形成布线层保护图案,暴露出需要蚀刻的位置。
接着,对布线层保护图案进行蚀刻并移除光刻胶层1100,形成设计的布线层193—步骤(j),如图1(j)所示。在本实施方案中,光刻胶层1100为负性光刻胶,曝光显影后形成负片,固化的光刻胶保护布线层193,暴露位置的金属层和种子层被蚀刻掉。在移除光刻胶层1100后形成布线层193。布线层193不限于在绝缘层150上下表面上的2层,可根据需求,在基板100的上下面未做表面处理前可进行多次增层和重新布线形成附加层,形成多层互连结构,例如封装上封装等。用于多次增层的材料可以是感光性绝缘材料、热固性绝缘材料或热塑性绝缘材料。
最后,在完成增层和重新布线后,在封装基板100的上下表面上进行表面处理,施加阻焊层1110和形成阻焊窗口1120—步骤(k),如图1(k)所示。通常,可以在完成封装后,在封装基板的外层两面涂覆或压合阻焊材料1110。阻焊材料包括AUS308或AUS410等,但不限上述材料。还可以通过施加光刻胶进行曝光和显影,在阻焊材料1110上开出特定的阻焊窗口1120,用于基板100与外界进行导电连通。
在制程最后,可以将封装基板分割成单独的封装组件。分割或切割可以使用旋转锯片或其它切割技术来实现,例如激光器。
图2示出利用图1所示的方法制造的具有三层绝缘层的嵌入式封装基板200。在以感光性绝缘材料为封装材料形成绝缘层150以及在其上形成布线层193后,在其两面各压合一层封装材料1200,例如半固化片(PP),再通过激光开孔或光刻开孔以及填孔电镀等方式形成外层线路,经表面处理后得到具有三层绝缘层的嵌入式封装基板200。这种多层互连结构能够进一步加强无芯基板的结构强度,缓冲内应力。增层的封装材料可以是感光性绝缘材料、热固性绝缘材料或热塑性绝缘材料,例如半固化片(PP)、ABF(膜状有机树脂)、聚酰亚胺、环氧树脂、双马来酰亚胺/三嗪树脂、聚苯醚、苯并环丁烯树脂或它们的共混物。
综上,本发明的实施方案省略了现有技术中制造嵌入式封装基板所必需的预置框架步骤。本发明的无预置框架的嵌入式封装基板制造工艺能够节省预置框架的步骤,通过直接对芯片进行定位封装,再进行增层布线来完成基板制作,这种方式大大缩短了流程和节约材料,达到节约成本的目的。同时,利用感光性绝缘材料作为嵌埋层的增层材料,能够有效避免激光开孔对芯片器件造成的损伤。而且,利用透明的临时承载板,能够解决厚感光性绝缘材料(100微米以上)存在的曝光不足的问题。此外,还可以利用外层层压诸如预浸半固化片PP等封装材料,进一步加强结构强度,缓冲内应力。
本领域技术人员将会认识到,本发明不限于上下文中具体图示和描述的内容。而且,本发明的范围由所附权利要求限定,包括上文所述的各个技术特征的组合和子组合以及其变化和改进,本领域技术人员在阅读前述说明后将会预见到这样的组合、变化和改进。
在权利要求书中,术语“包括”及其变体例如“包含”、“含有”等是指所列举的组件被包括在内,但一般不排除其他组件。
Claims (13)
1.一种嵌入式封装基板的制造方法,包括以下步骤:
a)在高透光性玻璃承载板的上表面上贴附双面胶带;
b)将器件贴附在双面胶带上;
c)在双面胶带上涂覆感光性绝缘材料,形成器件嵌埋在其中的绝缘层;
d)从玻璃承载板的上下两面对绝缘层的感光性绝缘材料进行曝光并显影形成第一图案;
e)移除玻璃承载板;
f)在所述绝缘层的表面上和所述第一图案中镀覆金属,形成在绝缘层上的金属层和贯穿绝缘层的金属柱;和
g)在所述金属层上形成布线层。
2.根据权利要求1所述的方法,其中步骤a还包括在所述玻璃承载板的下表面上施加抗反射涂层。
3.根据权利要求1所述的方法,其中所述感光型绝缘材料选自包括聚酰亚胺感光树脂或聚苯醚感光树脂的组别。
4.根据权利要求1所述的方法,其中所述器件包括选自集成电路、无源器件和有源器件中的至少其一。
5.根据权利要求4所述的方法,其中所述器件选自单颗芯片或背对背堆叠的多颗芯片。
6.根据权利要求4所述的方法,其中所述器件包括单面端子器件或双面端子器件。
7.根据权利要求1所述的方法,其中步骤e包括通过加热或紫外光照射使双面胶带失去粘性来移除玻璃承载板。
8.根据权利要求1所述的方法,其中所述方法还包括在步骤f前,对所述绝缘层的一面或两面施加种子层。
9.根据权利要求8所述的方法,其中所述种子层选自钛、镍、钒、铜、铝、钨、铬、银和金中的至少一种。
10.根据权利要求1所述的方法,其中步骤f包括在所述绝缘层的表面上和所述第一图案中镀覆铜。
11.根据权利要求1所述的方法,其中步骤g包括在所述绝缘层的一面或两面上涂布光刻胶层并图案化,在所得图案中填充铜形成布线层。
12.根据权利要求1所述的方法,其中所述方法还包括在步骤g之后,在所述布线层上增层形成附加层。
13.根据权利要求12所述的方法,其中所述附加层通过层压绝缘材料形成,该绝缘材料包括半固化片、膜状有机树脂、聚酰亚胺、环氧树脂、双马来酰亚胺/三嗪树脂、聚苯醚、苯并环丁烯树脂或它们的共混物。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010677083.3A CN111952201B (zh) | 2020-07-14 | 2020-07-14 | 一种嵌入式封装基板的制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010677083.3A CN111952201B (zh) | 2020-07-14 | 2020-07-14 | 一种嵌入式封装基板的制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN111952201A CN111952201A (zh) | 2020-11-17 |
CN111952201B true CN111952201B (zh) | 2022-02-18 |
Family
ID=73340528
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202010677083.3A Active CN111952201B (zh) | 2020-07-14 | 2020-07-14 | 一种嵌入式封装基板的制造方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN111952201B (zh) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN114666995B (zh) * | 2022-02-25 | 2024-03-26 | 珠海越亚半导体股份有限公司 | 封装基板及其制作方法 |
CN115483110B (zh) | 2022-08-08 | 2023-10-20 | 珠海越亚半导体股份有限公司 | 一种嵌埋器件封装基板及其制作方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101303981A (zh) * | 2007-05-07 | 2008-11-12 | 日本特殊陶业株式会社 | 具有内置部件的布线板及其用于制造该布线板的方法 |
CN103745936A (zh) * | 2014-02-08 | 2014-04-23 | 华进半导体封装先导技术研发中心有限公司 | 扇出型方片级封装的制作方法 |
CN104332414A (zh) * | 2014-04-09 | 2015-02-04 | 珠海越亚封装基板技术股份有限公司 | 嵌入式芯片的制造方法 |
CN106997870A (zh) * | 2016-01-26 | 2017-08-01 | 珠海越亚封装基板技术股份有限公司 | 新型嵌入式封装 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103456645B (zh) * | 2013-08-06 | 2016-06-01 | 江阴芯智联电子科技有限公司 | 先蚀后封三维系统级芯片正装堆叠封装结构及工艺方法 |
JP6377894B2 (ja) * | 2013-09-03 | 2018-08-22 | 信越化学工業株式会社 | 半導体装置の製造方法、積層型半導体装置の製造方法、及び封止後積層型半導体装置の製造方法 |
CN104241210A (zh) * | 2014-09-29 | 2014-12-24 | 华进半导体封装先导技术研发中心有限公司 | 一种低成本超薄扇出型封装结构及其制作方法 |
US10163824B2 (en) * | 2016-12-02 | 2018-12-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated fan-out package and method of fabricating the same |
JP2019062016A (ja) * | 2017-09-25 | 2019-04-18 | 住友ベークライト株式会社 | 半導体装置の製造方法 |
US10867929B2 (en) * | 2018-12-05 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structures and methods of forming the same |
-
2020
- 2020-07-14 CN CN202010677083.3A patent/CN111952201B/zh active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101303981A (zh) * | 2007-05-07 | 2008-11-12 | 日本特殊陶业株式会社 | 具有内置部件的布线板及其用于制造该布线板的方法 |
CN103745936A (zh) * | 2014-02-08 | 2014-04-23 | 华进半导体封装先导技术研发中心有限公司 | 扇出型方片级封装的制作方法 |
CN104332414A (zh) * | 2014-04-09 | 2015-02-04 | 珠海越亚封装基板技术股份有限公司 | 嵌入式芯片的制造方法 |
CN106997870A (zh) * | 2016-01-26 | 2017-08-01 | 珠海越亚封装基板技术股份有限公司 | 新型嵌入式封装 |
Also Published As
Publication number | Publication date |
---|---|
CN111952201A (zh) | 2020-11-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US8943683B2 (en) | Fabricating method of embedded package structure | |
KR101096614B1 (ko) | 전자 부품 실장 구조 및 그 제조 방법 | |
JP5249173B2 (ja) | 半導体素子実装配線基板及びその製造方法 | |
JP7277521B2 (ja) | 線路プリセット放熱埋め込み型パッケージ構造及びその製造方法 | |
WO2021196351A1 (zh) | 嵌入式芯片封装及其制造方法 | |
US9779940B2 (en) | Chip package | |
US20100288535A1 (en) | Electronic component-embedded printed circuit board comprising cooling member and method of manufacturing the same | |
JP2013243345A (ja) | 超薄埋設ダイモジュール及びその製造方法 | |
JP2008306173A (ja) | 部品内蔵配線基板及びその製造方法 | |
US9334576B2 (en) | Wiring substrate and method of manufacturing wiring substrate | |
CN111952201B (zh) | 一种嵌入式封装基板的制造方法 | |
JP7333454B2 (ja) | モールド成形プロセスに基づくパッケージ基板及びその製造方法 | |
JP3917484B2 (ja) | 半導体装置の製造方法および半導体装置 | |
CN115763416A (zh) | 一种金属框架封装基板及其制造方法 | |
JP4438389B2 (ja) | 半導体装置の製造方法 | |
US20220302037A1 (en) | Embedded packaging structure and manufacturing method thereof | |
TW201944551A (zh) | 封裝結構及其製造方法 | |
JP5880036B2 (ja) | 電子部品内蔵基板及びその製造方法と積層型電子部品内蔵基板 | |
JP2010123632A (ja) | 電子部品内蔵配線基板の製造方法 | |
JP5097006B2 (ja) | プリント配線基板及びその製造方法 | |
CN110265311B (zh) | 部件承载件及其制造方法、半成品和电子器件 | |
US9730329B2 (en) | Active chip package substrate and method for preparing the same | |
US20200068721A1 (en) | Package structure and manufacturing method thereof | |
JP3643764B2 (ja) | 回路装置の製造方法 | |
CN116013870A (zh) | 嵌埋器件封装基板及其制作方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |