WO2021196351A1 - 嵌入式芯片封装及其制造方法 - Google Patents

嵌入式芯片封装及其制造方法 Download PDF

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Publication number
WO2021196351A1
WO2021196351A1 PCT/CN2020/089735 CN2020089735W WO2021196351A1 WO 2021196351 A1 WO2021196351 A1 WO 2021196351A1 CN 2020089735 W CN2020089735 W CN 2020089735W WO 2021196351 A1 WO2021196351 A1 WO 2021196351A1
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Prior art keywords
chip
frame
wiring layer
polymer dielectric
photosensitive polymer
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PCT/CN2020/089735
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English (en)
French (fr)
Inventor
陈先明
冯进东
黄本霞
冯磊
王闻师
Original Assignee
珠海越亚半导体股份有限公司
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Application filed by 珠海越亚半导体股份有限公司 filed Critical 珠海越亚半导体股份有限公司
Priority to US17/044,087 priority Critical patent/US11854920B2/en
Publication of WO2021196351A1 publication Critical patent/WO2021196351A1/zh
Priority to US18/389,264 priority patent/US20240087972A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/041—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction having no base used as a mounting for the semiconductor body
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    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/86—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using tape automated bonding [TAB]
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    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
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    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables

Definitions

  • the invention relates to chip packaging, in particular to embedded chip packaging and a manufacturing method thereof.
  • Embedded packaging technology is to embed passive components such as resistors, capacitors, inductors, or even active components such as ICs into the package substrate. This approach can shorten the line length between the components, improve the electrical characteristics, and improve the effective
  • the printed circuit board packaging area reduces a large number of solder joints on the printed circuit board surface, thereby improving the reliability of the packaging and reducing the cost. It is a very ideal high-density packaging technology.
  • the packaging materials are all thermosetting polymers (such as epoxy resin polymers such as prepreg PP or film resin ABF) or thermoplastic polymer Materials (such as polyethylene PE).
  • thermosetting polymers such as epoxy resin polymers such as prepreg PP or film resin ABF
  • thermoplastic polymer Materials such as polyethylene PE.
  • U.S. Patent Publication US20190124772A1 discloses the use of thermosetting electrical insulating materials (cured under certain temperature and pressure conditions) as packaging materials, and then use laser opening to expose the conductive posts (terminals) of the chip or device, and finally fill the holes with electroplating The laser hole is filled with copper to achieve electrical connection.
  • this method is not suitable for embedding bare chips and devices without conductive pillars with high aspect ratio, because the thickness of the conductive metal pads on the outer layer of the bare chip is only 2 to 5 ⁇ m, and the thickness of the conductive terminals of the devices without conductive pillars It is only 6-15 ⁇ m, and the energy generated by laser irradiation is enough to destroy the entire chip structure or the conductive terminals of the breakdown device for a metal pad or terminal of this thickness.
  • Chinese patent CN106997870A discloses a double-sided conductive embedded structure, which also uses thermosetting electrical insulating materials as packaging materials to fix the chip, and then uses plasma dry etching to open the back of the chip to achieve double-sided connection.
  • this method to produce large openings, such as millimeter to centimeter-level openings, especially when the packaging material has a large thickness, the etching time is very long and the efficiency is low.
  • the thickness of the packaging material in the patent is 15 ⁇ m to 50 ⁇ m.
  • the etching time of dry etching requires 50 min to 150 min, which results in low work efficiency.
  • the energy of the laser is likely to cause stress inside the chip or device, and it is easy to cause damage to the chip or device. Therefore, it is not suitable for the embedding of bare chips/devices without conductive pillars.
  • An object of the present invention is to provide an embedded chip package using a photosensitive polymer dielectric material as a package material and a manufacturing method thereof, so as to overcome the technical defects in the prior art.
  • the first embodiment relates to an embedded chip package.
  • the chip package includes at least one chip and a frame surrounding the at least one chip, the chip having a terminal surface and a back surface separated by a height of the chip.
  • the height is equal to or greater than the height of the chip, wherein the gap between the chip and the frame is completely filled with photosensitive polymer dielectric material, the terminal surface of the chip is coplanar with the frame, and the A first wiring layer is provided on the terminal surface of the chip, and a second wiring layer is provided on the back surface of the chip.
  • the photosensitive polymer dielectric material is selected from the group consisting of polyimide photosensitive resin and polyphenylene ether photosensitive resin.
  • the frame further includes at least one frame through hole column that extends through the height of the frame from the first frame face to the second frame face of the frame.
  • the terminal surface of the chip includes metal terminal contacts, and the metal terminal contacts are conductively connected to the first wiring layer through a first via post enclosed in a photosensitive polymer dielectric material .
  • a second via post is formed on the back surface of the chip, and the second via post is surrounded by a photosensitive polymer dielectric material.
  • the second via post conducts connection between the back surface of the chip and the second wiring layer.
  • the second wiring layer includes a heat dissipation pad.
  • the backside of the chip has through silicon vias that connect the terminals of the chip, or the chips are stacked back-to-back so that the backside of the chip has terminals.
  • third and fourth through-hole posts are respectively formed on the two end faces of the frame through-hole posts on both sides of the frame, wherein the third through-hole posts are conductively connected to the first wiring Layer, the fourth via post is conductively connected to the second wiring layer.
  • the chip includes at least one selected from an integrated circuit, a passive device, and an active device.
  • the chip includes a power device or a back-to-back stacked combination of chips.
  • the material of the frame via post and the first, second, third and fourth via post includes copper.
  • the second embodiment relates to a method of manufacturing an embedded chip package, including the following steps:
  • the photosensitive polymer dielectric material is selected from the group consisting of polyimide photosensitive resin and polyphenylene ether photosensitive resin.
  • the metal seed layer includes Ti, W, or Ti/W alloy.
  • the first wiring layer is conductively connected to the chip terminal contacts through a first via post
  • the second wiring layer is conductively connected to the backside of the chip through a second via post.
  • the material of the frame via post and the first, second, third and fourth via post includes copper.
  • the method further includes removing the photoresist layer and etching away the exposed metal seed layer after the copper electroplating.
  • the method further includes layer build-up and rewiring on the first and second wiring layers to build additional wiring layers.
  • the method further includes applying a solder resist layer on the first and/or second wiring layer.
  • the method also includes cutting the chip socket array into individual packaged chips.
  • the photosensitive polymer dielectric material mentioned in this application refers to a type of photosensitive resin material with a relatively low dielectric constant and dielectric loss.
  • negative photosensitive polymer dielectric materials are commonly used.
  • the photoinitiator Under the action of light such as ultraviolet light or visible light or high energy rays (such as electron beams), the photoinitiator can be excited to make small molecules of unsaturated organic oligomerization. After cross-linking and polymerization, a stable solid organic polymer product is formed.
  • photosensitive resins are generally used as photoresist materials such as photoresists, but in the packaging applications mentioned in the present invention, such photosensitive polymer dielectric materials need to have some special properties, for example, in a wide temperature range and It has high dielectric properties in the frequency range, such as dielectric constant 2.5 ⁇ 3.4, dielectric loss 0.001 ⁇ 0.01, dielectric strength 100KV ⁇ 400KV, and has better adhesion, lower stress, etc.
  • This application uses photosensitive polymer dielectric materials as chip packaging materials, which can simplify the process steps, improve production efficiency, and reduce production costs. For example, multiple patterns can be formed at the same time and then electroplated and filled at the same time; at the same time, traditional hole-opening methods can be avoided The risk of damage to the embedded chip improves the yield rate. At the same time, since the method of the present application does not require a grinding plate, there is no risk such as glass fiber exposure.
  • Figure 1 is a schematic side view of a first embedded chip structure
  • Figure 2 is a schematic side view of a second embedded chip structure
  • Figure 3 is a schematic side view of a third embedded chip structure
  • FIGS 4 (a) to (i) schematically show intermediate structures obtained by the method steps of the present invention.
  • the present invention relates to an embedded chip package, which is characterized in that the chip and frame are embedded in a photosensitive polymer dielectric material as the packaging material, an opening is directly formed on the back of the chip and metal such as copper is deposited, and the chip terminal surface is also passed through
  • the photosensitive polymer dielectric material is arranged to produce openings to form metal pillars that conduct the chip terminals, thereby forming a double-sided conduction or heat dissipation structure of the chip.
  • the photosensitive polymer dielectric materials used in the present invention mainly include polyimide photosensitive resin and polyphenylene ether photosensitive resin, such as Microsystems HD-4100, Hitachi PVF-02, etc.
  • the metal post formed on the chip terminal surface is used to connect the chip terminal and the first wiring layer.
  • the metal pillar formed on the back of the chip is usually used as a heat dissipation pad or connected to a heat dissipation device, so that the packaged chip can dissipate heat more effectively.
  • the copper pillars formed on the back of the chip can also provide electrical connection functions.
  • additional layers can also be added on the back surface and terminal surface of the chip to build additional wiring layers to form a multilayer interconnection structure, forming a so-called package on package (PoP) structure.
  • PoP package on package
  • the embedded chip package 100 includes a chip 140 having a terminal surface 141 and a back surface 142 separated by the height of the chip.
  • the chip 140 is disposed in the cavity 130 and is surrounded by a frame 110, and the frame 110 has a first frame surface 111 that is coplanar with the chip terminal surface 141 and a second frame surface 112 opposite to it.
  • the thickness of the frame 110 is greater than the height of the chip 140, and is usually 15 ⁇ m to 50 ⁇ m higher, so that the second frame surface 112 is higher than the back surface 142 of the chip 140.
  • the gap between the chip 140 and the frame 110 is filled with a photosensitive polymer packaging material 160, and the packaging material 160 includes a polyimide photosensitive resin or a polyphenylene ether photosensitive resin.
  • the packaging material 160 not only covers the chip back surface 142 and the second frame surface 112, but can also cover the chip terminal surface 141 and the first frame surface 111. In this way, via photolithography and hole filling can be used to form via post layers on both surfaces of the chip package 100 to respectively conduct the first wiring layer 131 and the second wiring layer 132.
  • One or more conductive via posts 120 such as copper via posts may be provided to pass through the thickness of the frame 110. These through-hole posts 120 connect the first frame surface 111 and the second frame surface 112.
  • the chip 140 may be a device with through silicon vias penetrating the chip or a plurality of chips stacked back to back, so that there are electrically connectable terminals on the back surface 142 of the chip 140.
  • the frame 110 has a first polymer matrix, and may also include glass fibers and ceramic fillers.
  • the frame 110 is made of a prepreg of woven glass fiber impregnated with a polymer.
  • an embedded chip package 200 in which a heat dissipation pad is formed on the back of the chip.
  • the structure of the embedded chip package 200 is similar to the chip package 100 of FIG.
  • Such a chip package 200 is suitable for high-power devices, especially chips that require electrical conduction on one side and heat dissipation on both sides.
  • the packaged chips 100 and 200 of Figs. 1 and 2 are not limited to the case where double-sided conduction and single-sided electrical conduction are required for double-sided heat dissipation, and also when the chip is electrically conductive on one side (terminal surface) and does not have holes on the back side. It can be applied.
  • the chip terminal surfaces 141 of the packaged chips 100 and 200 of FIGS. 1 and 2 can be used to cover the photosensitive polymer dielectric material 161 to lead out the metal terminals according to the design requirements, or the photosensitive polymer dielectric material layer 161 may not be added.
  • Wiring is directly on the chip terminal surface 141 that is flush with the surface 111 of the frame 110, 210.
  • FIG. 3 shows that additional wiring layers 351 and 352 are continuously formed on both sides of the packaged chip 100 of FIG. 1 to form a build-up interconnect structure 300. Similarly, it is also possible to continue build-up layers to form additional layers on the packaged chip 200 of FIG. 2 to form "PoP" and similar interconnect structures are encapsulated on the package.
  • layer build-up processing can be performed on both sides of the frame at the same time. It should also be understood that since the seed layer can be sputtered on both sides of the frame and the chip, additional wiring layers and conductive structures can be constructed on both sides. Once a wiring layer with conductive features is formed on one or both sides of the package, other chips can be attached to the conductive features using technologies such as ball grid array (BGA) or contact grid array (LGA).
  • BGA ball grid array
  • LGA contact grid array
  • packaging technology discussed herein can be used to package chips with circuits on both sides. This allows the wafer to be processed on both sides, such as a processor chip on one side and a memory chip on the other side.
  • the packaging technology discussed herein is not limited to packaging IC chips.
  • the chip includes passive devices selected from fuses, capacitors, inductors, and filters.
  • FIG. 1 a manufacturing method for manufacturing the embedded chip package structure of FIG. 1 is shown.
  • the method can be adapted to manufacture other similar structures, such as the structures shown in FIGS. 2 and 3.
  • the method includes obtaining a chip socket array composed of a first polymer frame 110 (see FIG. 4a), each through socket 130 is defined by the frame 110, and optionally further includes at least one frame through hole post 120 passing through the frame 110.
  • the organic frame 110 can be fabricated according to the US Patent Publication US20160165731A1.
  • the frame 110 has two upper and lower surfaces 112, 111 and an array of cavities or sockets 130 arranged according to the size of the chip.
  • the thickness of the frame 110 is greater than and close to the thickness of the chip, and is usually 15-50 ⁇ m higher than the thickness of the chip.
  • the frame 110 is arranged on the disposable adhesive tape 150, and the chip 140 is arranged face down (that is, the terminal face down) in the cavity 130 of the frame 110 so that the chip terminal surface 141 is in contact with the adhesive tape 150 (see FIG. 4b).
  • the tape 150 is generally a commercially available transparent film, which can be decomposed by heating or exposure to ultraviolet light, and can be aligned or exposed by imaging through the tape to promote curing of the photosensitive polymer dielectric material.
  • a photosensitive polymer dielectric material 160 such as polyimide photosensitive resin or polyphenylene ether photosensitive resin, as an encapsulating material on the frame 110 including the chip 140, so that the photosensitive polymer dielectric material 160 is completely filled
  • the gap between the chip 140 and the frame 110 covers the back surface 142 of the chip, the upper surface 112 of the frame and the upper surface 122 of the copper pillar 120 (see FIG. 4c).
  • An exposure machine is used to expose the photosensitive polymer dielectric material 160 on the back side of the chip and develop a first pattern.
  • the photosensitive polymer dielectric material at the opening position in the first pattern is not cured and is removed. Therefore, the first pattern includes a first blind hole 171 and a second blind hole 172.
  • the first blind hole 171 exposes the upper surface 122 of the frame through hole column 120 on the frame 110, and the second blind hole 172 exposes the back surface 142 of the chip 140. (See Figure 4c).
  • auxiliary exposure can also be performed from one side of the tape to promote rapid curing of the photosensitive polymer dielectric material filled between the frame and the chip.
  • the adhesive tape 150 is removed, and a photosensitive polymer dielectric material 161 is laminated or coated on the terminal surface 141 of the chip 140 and the lower surface 111 of the frame; the photosensitive polymer dielectric material 161 is exposed and developed to form a second pattern.
  • the second pattern includes a third blind hole 173 and a fourth blind hole 174.
  • the third blind hole 173 exposes the metal terminal contacts on the terminal surface 141 of the chip 140, and the fourth blind hole 174 exposes the frame on the lower surface 111 of the frame.
  • the lower end surface 121 of the through hole column 120 see FIG. 4d).
  • the tape 150 can be burned or removed by exposure to ultraviolet light.
  • the photosensitive polymer dielectric materials 160 and 161 may be the same or different photosensitive polymer dielectric materials, and may only differ in thickness.
  • a metal seed layer 180 is formed on the surface of the photosensitive polymer dielectric material 160, 161 and the blind holes 171, 172, 173, 174 by means of electroless plating or sputtering (see FIG. 4e).
  • Commonly used seed layer metals are selected from titanium, copper, or titanium-tungsten alloys, but are not limited to the above metals.
  • a photoresist layer 190 is applied on the metal seed layer 180 on both sides of the package 100, and a third pattern including the first and second wiring layers is directly formed by exposure and development.
  • the third pattern formed by exposure and development of the photoresist layer 190 exposes the metal seed layer 180 where the first and second wiring layers need to be formed (see FIG. 4f).
  • Copper is electroplated and filled into the first, second, and third patterns by electroplating, so that all open blind holes and wiring layer openings are filled with copper at the same time to form the first, second, third, and fourth through holes
  • the pillars 120a, 120b, 120c, 120d and the first and second wiring layers 131, 132 (see FIG. 4g).
  • the photoresist layer 190 is removed by a stripping solution, and then the exposed metal seed layer 180 is removed by etching (see FIG. 4h).
  • the upper and lower surfaces of the substrate can be added and re-wired multiple times without surface treatment to build additional wiring layers.
  • the dielectric material used for the build-up can be a photosensitive polymer dielectric.
  • the material can also be a traditional packaging material, such as a thermosetting insulating material or a thermoplastic insulating material; the method of adding layers to build an additional wiring layer can be a conventional method, such as dry etching.
  • solder resist material 195 can be coated or pressed on one or both sides of the outer layer.
  • the solder resist material includes AUS308 or AUS410, but is not limited to the above materials.
  • a specific solder resist window 196 can be opened on the solder resist material 195 by exposure and development of photoresist (see FIG. 4i).
  • the panel array can be divided to obtain a single chip package. Dividing or cutting can be achieved using rotating saw blades or other cutting techniques, such as lasers.

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Abstract

一种嵌入式芯片封装（100）及其制造方法，所述芯片封装（100）包括至少一个芯片（140）和包围所述至少一个芯片（140）的框架（110），所述芯片（140）具有被芯片（140）高度分隔开的端子面（141）和背面（142），所述框架（110）的高度等于或大于所述芯片（140）的高度，其中所述芯片（140）和所述框架（110）之间的间隙完全被感光型聚合物介电材料（160）填充，所述芯片（140）的端子面（141）与所述框架（110）共平面，并且在所述芯片（140）的端子面（141）上设置有第一布线层（131），在所述芯片（140）的背面（142）上设置有第二布线层（132）。

Description

嵌入式芯片封装及其制造方法 技术领域
本发明涉及芯片封装，具体涉及嵌入式芯片封装及其制造方法。
背景技术
随着电子产业的蓬勃发展，电子产品也逐渐进入多功能、微型化和高性能的时代。越来越多的高密度、多功能和小型化的需求给封装和基板都带来了新的挑战，很多新的封装技术应运而生，包括嵌入式封装技术。
嵌入式封装技术是把电阻、电容、电感等无源器件甚或IC等有源器件埋入到封装基板内部，这种做法可以缩短元件相互之间的线路长度，改善电气特性，而且还能提高有效的印制电路板封装面积，减少大量的印制电路板板面的焊接点，从而提高封装的可靠性，并降低成本，是一种非常理想的高密度封装技术。
然而，不论是晶圆级嵌埋技术，还是面板级嵌埋技术，封装材料都是采用热固型聚合物(如半固化片PP或薄膜型树脂ABF等环氧树脂类聚合物)或热塑型聚合物(如聚乙烯类PE)。而要实现芯片双面导通或散热，就必须在封装材料上暴露出开口以形成通孔柱、端子或散热垫，常用的方式包括在封装材料上进行激光打孔和掩膜干法蚀刻，然而这两种方式都存在明显的技术缺陷。
美国专利公报US20190124772A1公开了采用热固性电绝缘材料(在一定温度和压力条件下固化)作为封装材料，然后利用激光开孔的方式将芯片或器件的导电柱(端子)暴露出来，最后用电镀填孔的方式将激光孔填充铜实现电连接。但是，此种方式不适用于嵌埋裸芯片和没有高长径比的导电柱的器件，因为裸芯片外层的导电金属垫厚度仅有2～5μm，没有导电柱的器件的导电端子的厚度也仅为6～15μm，而激光照射产生的能量对此种厚度的金属垫或端子而言足以破坏整个芯片结构或击穿器件的导电端子。
中国专利CN106997870A公开了一种双面导通的嵌埋结构，也是采用热 固型电绝缘材料作为封装材料固定芯片，然后用等离子体干法蚀刻的方式打开芯片背面实现双面连接。用这种方法产生大开口例如毫米至厘米级开口时，尤其是在封装材料厚度较大的情况下，蚀刻时间很长，效率低下。例如，该专利中封装材料的厚度为15μm～50μm，在开大开口用于散热的情况下，干法蚀刻的蚀刻时间需要50min～150min，作业效率低下。而在开小孔例如孔径200μm以下的情况下，由于干法蚀刻气体在小孔内的交换率更低，会导致蚀刻速率进一步下降，并且孔底的质量(孔径、真圆度)差，难以实现良好的导热/导电性能。
因此，现有技术中存在着以下缺点：
在常规封装材料上通过激光打孔暴露开口的情况下，激光的能量容易在芯片或器件内部产生应力，易造成芯片或器件的破坏，因此不适合裸芯片/无导电柱器件的嵌埋。
在常规封装材料上通过干法蚀刻暴露开口的情况下，难以实现开小孔，而且即便是大开口，也存在作业流程长，制程产出低下，产品的设计受到局限，均匀性差，寿命短等缺点。此外，干法蚀刻通常需要对封装材料进行研磨减薄，而面板框架通常是由玻璃纤维复合材料(例如BT)制成，因此不得不面对磨板后玻纤暴露的问题，玻纤暴露会限制精细线路的能力，例如铜在玻纤上的结合力差、易剥离；以及暴露的玻纤容易形成电迁移的通道，导致电性能失效，寿命降低。
发明内容
本发明的一个目的是提供一种利用感光型聚合物介电材料作为封装材料的嵌入式芯片封装以及其制造方法，以克服现有技术中的技术缺陷。
第一实施方案涉及一种嵌入式芯片封装，所述芯片封装包括至少一个芯片和包围所述至少一个芯片的框架，所述芯片具有被芯片高度分隔开的端子面和背面，所述框架的高度等于或大于所述芯片的高度，其中所述芯片和所述框架之间的间隙完全被感光型聚合物介电材料填充，所述芯片的端子面与所述框架共平面，并且在所述芯片的端子面上设置有第一布线层，在所述芯片的背面上设置有第二布线层。
优选地，所述感光型聚合物介电材料选自包括聚酰亚胺感光树脂和聚苯醚感光树脂的组别。
在一些实施方案中，所述框架还包括至少一个框架通孔柱，所述框架通孔柱延伸穿过从所述框架的第一框架面到第二框架面的框架高度。
在一些实施方案中，所述芯片的端子面包含金属端子触点，所述金属端子触点通过包围在感光型聚合物介电材料中的第一通孔柱导通连接所述第一布线层。
在一些实施方案中，在所述芯片的背面上形成有第二通孔柱，所述第二通孔柱被感光型聚合物介电材料包围。
优选地，所述第二通孔柱导通连接芯片背面和第二布线层。优选地，所述第二布线层包括散热垫。
在一些实施方案中，所述芯片背面具有连接芯片端子的硅通孔，或者具有背对背堆叠的芯片使得芯片背面具有端子。
在一些实施方案中，在所述框架通孔柱在框架两侧的两个端面上分别形成有第三和第四通孔柱，其中所述第三通孔柱导通连接所述第一布线层，所述第四通孔柱导通连接所述第二布线层。
通常，所述芯片包括选自集成电路、无源器件和有源器件中的至少其一。优选地，所述芯片包括功率器件或背靠背堆叠组合的芯片。
优选地，所述框架通孔柱以及第一、第二、第三和第四通孔柱的材料包括铜。
第二实施方案涉及一种制造嵌入式芯片封装的方法，包括以下步骤：
·获得由框架构成的芯片插座阵列，其中在框架中形成穿过所述框架高度的框架通孔柱；
·将所述芯片插座阵列放置在胶带上；
·将芯片的端子面朝下放入所述芯片插座阵列的被框架包围的空腔中；
·在芯片和框架上层压或涂覆感光型聚合物介电材料，使得感光型聚合物介电材料完全填充芯片与框架之间的间隙并覆盖芯片背面和框架的上表面；
·对感光型聚合物介电材料曝光并显影出第一图案，所述第一图案形成暴露出框架通孔柱在框架上表面的端部的第一盲孔和暴露出所述芯片背面的第 二盲孔；
·移除所述胶带，在芯片的端子面和框架的下表面上层压或涂覆感光型聚合物介电材料；
·曝光并显影出第二图案，所述第二图案形成暴露出芯片的端子的第三盲孔和暴露出框架通孔柱在框架下表面的端部的第四盲孔；
·在第一图案和第二图案上施加金属种子层；
·在所述金属种子层上施加光刻胶层，图案化所述光刻胶层形成包括第一布线层和第二布线层的第三图案；和
·通过电镀铜，同时填充所述第一、第二和第三图案，形成第一、第二、第三和第四通孔柱以及第一布线层和第二布线层。
在一些实施方案中，所述感光型聚合物介电材料选自包括聚酰亚胺感光树脂和聚苯醚感光树脂的组别。
在一些实施方案中，所述金属种子层包括Ti、W或Ti/W合金。
在一些实施方案中，所述第一布线层通过第一通孔柱导通连接芯片端子触点，所述第二布线层通过第二通孔柱导通连接芯片的背面。
优选地，所述框架通孔柱以及第一、第二、第三和第四通孔柱的材料包括铜。
在一些实施方案中，所述方法还包括在电镀铜之后，移除光刻胶层并蚀刻掉暴露的金属种子层。
在一些实施方案中，所述方法还包括在所述第一和第二布线层上进行增层和重新布线以叠加构建附加布线层。
在一些实施方案中，所述方法还包括在第一和/或第二布线层上施加阻焊层。
通常，所述方法还包括将所述芯片插座阵列切割成单独的封装芯片。
本申请所提及的感光型聚合物介电材料是指具有较低的介电常数和介电损耗的一类感光树脂材料。目前通常使用的是负性的感光型聚合物介电材料，可以在诸如紫外光或可见光的光线或高能射线(例如电子束)的作用下，激发光引发剂使小分子的不饱和有机低聚物经交联聚合形成稳定的固态有机高分子产物。
通常感光树脂一般用作光刻胶等光阻材料，但在本发明所提及的封装应用中，此类感光型聚合物介电材料需要具有一些特殊的性能，例如在较宽的温度范围和频率范围内具有较高的介电性能，例如介电常数2.5～3.4，介电损耗0.001～0.01，介电强度100KV～400KV，以及具有较好的附着性、较低应力等。
本申请通过利用感光型聚合物介电材料作为芯片封装材料，从而能够简化工艺流程步骤，提高生产效率，降低生产成本，例如可以同时形成多个图案再同时电镀填充；同时能够避免传统开孔方式对嵌入式芯片的损坏风险，提高了良率。同时，由于本申请的方法不需要磨板，因此不存在诸如玻纤暴露的风险。
附图说明
为了更好地理解本发明并示出本发明的实施方式，纯粹以举例的方式参照附图。
现在具体参照附图，必须强调的是，具体图示仅为示例且出于示意性讨论本发明优选实施方案的目的，提供图示的原因是确信附图是最有用且易于理解本发明的原理和概念的说明。就此而言，没有试图将本发明的结构细节以超出对本发明基本理解所必需的详细程度来图示。在附图中：
图1是第一嵌入式芯片结构的侧视示意图；
图2是第二嵌入式芯片结构的侧视示意图；
图3是第三嵌入式芯片结构的侧视示意图；
图4(a)至(i)示意性地示出通过本发明的方法步骤所获得的中间结构。
具体实施方式
本发明涉及嵌入式芯片封装，其特征在于将芯片和框架嵌埋在作为封装材料的感光型聚合物介电材料中，在芯片背面直接形成开口并沉积金属例如铜，同时也在芯片端子面通过布设感光型聚合物介电材料产生开孔，形成导通芯片端子的金属柱，由此形成芯片双面导通或散热结构。
本发明使用的感光型聚合物介电材料主要包括聚酰亚胺感光树脂和聚苯醚感光树脂，例如Microsystems HD-4100、Hitachi PVF-02等。
芯片端子面上形成的金属柱用于连接芯片端子与第一布线层。在芯片背面形成的金属柱通常用作散热垫或连接至散热装置，使得封装芯片能够更有效地散热。在芯片背面也存在端子的情况下，例如芯片具有贯穿芯片的硅通孔结构或者是背靠背3D堆叠的多个芯片时，芯片背面上形成的铜柱也可提供电连接功能。
此外，在芯片的背面和端子面上也可以继续增层以叠加构建附加布线层形成多层互连结构，形成所谓封装上封装(PoP)的结构。
参考图1，示出一种双面导通的嵌入式芯片封装100。嵌入式芯片封装100包括芯片140，其具有由芯片高度分隔开的端子面141和背面142。芯片140设置在空腔130中被框架110包围，框架110具有与芯片端子面141共面的第一框架面111和相反的第二框架面112。框架110的厚度大于芯片140的高度，通常高出15微米至50微米，使得第二框架面112高于芯片140的背面142。在芯片140和框架110之间的空隙填充有感光型聚合物封装材料160，封装材料160包括聚酰亚胺感光树脂或聚苯醚感光树脂。
与现有技术的嵌入式芯片封装不同，在芯片封装100中，封装材料160不仅覆盖芯片背面142和第二框架面112，而且也可以覆盖在芯片端子面141和第一框架面111上。从而可以通过光刻和填孔，在芯片封装100的两个表面上分别形成通孔柱层以分别导通第一布线层131和第二布线层132。
一个或多个导电通孔柱120例如铜通孔柱可以设置为穿过框架110的厚度。这些通孔柱120连接第一框架面111和第二框架面112。
芯片140可以是具有贯穿芯片的硅通孔的器件或者是背靠背堆叠的多个芯片，使得在芯片140的背面142上具有可电连接的端子。
框架110具有第一聚合物基质，并且还可以包括玻璃纤维和陶瓷填料。在一些实施方案中，框架110由浸渍有聚合物的编织玻璃纤维的预浸料制成。
参考图2，示出一种在芯片背面形成散热垫的嵌入式芯片封装200。嵌入式芯片封装200的结构类似于图1的芯片封装100，区别仅在于在芯片背面142上形成的大开口中通过填充散热金属形成散热垫250。此种芯片封装200适用于大功率器件，特别是需要单面电导通并且双面散热的芯片。
图1和图2的封装芯片100和200并不局限于需要双面导通和单面电导通双面散热的情况，在芯片单面(端子面)电导通并且背面不开孔的情况下也可以适用。图1和图2的封装芯片100和200的芯片端子面141可根据设计需要，通过覆盖感光型聚合物介电材料161开孔引出金属端子，也可以不增加感光性聚合物介电材料层161，直接在与框架110、210的表面111齐平的芯片端子面141上布线。
图3示出在图1的封装芯片100的两面上继续形成附加布线层351、352从而形成增层互连结构300，同样也可以在图2的封装芯片200上继续增层形成附加层，形成封装上封装“PoP”及其类似的互连结构。
应该理解的是，可以在框架的两面上同时进行增层加工。还应当理解的是，由于可以在框架和芯片的两面上溅射种子层，因此可以两面构建附加的布线层和导通结构。一旦在封装的一面或两面上形成具有导体特征结构的布线层后，就可以利用球栅阵列(BGA)或触点栅格阵列(LGA)等技术将其它芯片附接到导体特征结构上。
应当理解的是，本文所讨论的封装技术可用于封装在两面上具有电路的芯片。这使得晶圆能够被两面加工，例如一面上是处理器芯片，另一面上是存储器芯片。
应当理解的是，本文所讨论的封装技术不限于封装IC芯片。在一些实施方案中，芯片包括选自熔丝、电容器、电感器和滤波器的无源器件。
参照图4(a)至4(aa)，示出一种制造图1的嵌入式芯片封装结构的制造方法。然而，应当理解的是，该方法可以适于制造其他类似的结构，例如图2和3中所示的结构。
该方法包括获得由第一聚合物框架110构成的芯片插座阵列(参见图4a)，每个贯穿插座130被框架110限定，可选地还包括穿过框架110的至少一个框架通孔柱120。可以根据美国专利公报US20160165731A1制作有机框架110，框架110具有上下两个表面112、111以及根据芯片的尺寸生成的阵列式排布的空腔或插座130。框架110厚度大于并且接近芯片的厚度，通常比芯片厚度高出15-50μm。
框架110设置在一次性胶带150上，将芯片140面朝下(即端子面向 下)设置在框架110的空腔130中，使得芯片端子面141与胶带150接触(参见图4b)。胶带150通常是市售的透明膜，其可以通过加热或暴露于紫外光而分解，并且可以通过穿过胶带成像来对准或者曝光以促进感光型聚合物介电材料的固化。
在包括芯片140的框架110上层压或涂覆作为封装材料的感光型聚合物介电材料160，例如聚酰亚胺感光树脂或聚苯醚感光树脂，使得感光型聚合物介电材料160完全填充芯片140与框架110之间的间隙并覆盖芯片的背面142、框架的上表面112和铜柱120的上表面122(参见图4c)。
利用曝光机对芯片背面一侧的感光型聚合物介电材料160进行曝光并显影出第一图案，在第一图案中开孔位置的感光型聚合物介电材料未被固化从而被移除，因此第一图案包括第一盲孔171和第二盲孔172，第一盲孔171暴露出框架110上的框架通孔柱120的上表面122，第二盲孔172暴露出芯片140的背面142(参见图4c)。
同时，也可以从胶带一侧进行辅助曝光，以促使填充在框架和芯片之间的感光型聚合物介电材料快速固化。
移除胶带150，在芯片140的端子面141和框架的下表面111上层压或涂覆感光型聚合物介电材料161；对感光型聚合物介电材料161曝光并显影出第二图案，第二图案包括第三盲孔173和第四盲孔174，第三盲孔173暴露出芯片140的端子面141上的金属端子触点，第四盲孔174暴露出在框架下表面111上的框架通孔柱120的下端面121(参见图4d)。
根据所使用的特定胶带，胶带150可以通过暴露于紫外光而被烧掉或移除。感光型聚合物介电材料160和161可以是相同或不同的感光型聚合物介电材料，可以仅是厚度的区别。
通过化学镀或者溅射的方式在感光型聚合物介电材料160、161的表面和盲孔171、172、173、174内形成金属种子层180(参见图4e)。常用的种子层金属选自钛、铜或钛钨合金，但不限于上述金属。
在封装100的两面的金属种子层180上施加光刻胶层190，直接通过曝光、显影的方式形成包括第一和第二布线层的第三图案。光刻胶层190通过曝光和显影形成的第三图案暴露出需要形成第一和第二布线层的位置的金属 种子层180(参见图4f)。
通过电镀的方式将铜电镀填充到第一、第二和第三图案中，使得所有打开的盲孔和布线层开孔被同时填充铜以形成第一、第二、第三和第四通孔柱120a、120b、120c、120d以及第一和第二布线层131、132(参见图4g)。
利用退膜药水去除光刻胶层190，再通过蚀刻的方式将暴露的金属种子层180去除(参见图4h)。
根据具体需求，基板的上下表面可在不进行表面处理的情况下即可进行多次增层和重新布线以叠加构建附加布线层，用于增层的介电材料可以是感光型聚合物介电材料，也可以是传统的封装材料，如热固性绝缘材料或热塑性绝缘材料；进行增层以叠加构建附加布线层的方法可以是常规方法，例如干法蚀刻等。
嵌入式芯片封装完成后可以在外层一面或两面涂覆或压合施加阻焊材料195，阻焊材料包括AUS308或AUS410等，但不限于上述材料。可以通过光刻胶的曝光和显影在阻焊材料195上开出特定的阻焊开窗196(参见图4i)。
最后，可以将面板阵列进行分割，得到单个芯片封装。分割或切割可以使用旋转锯片或其它切割技术来实现，例如采用激光器。
本领域技术人员将会认识到，本发明不限于上文中具体图示和描述的内容。而且，本发明的范围由所附权利要求限定，包括上文所述的各个技术特征的组合和子组合以及其变化和改进，本领域技术人员在阅读前述说明后将会预见到这样的组合、变化和改进。

Claims (20)

  1. 一种嵌入式芯片封装，所述芯片封装包括至少一个芯片和包围所述至少一个芯片的框架，所述芯片具有被芯片高度分隔开的端子面和背面，所述框架的高度等于或大于所述芯片的高度，其中所述芯片和所述框架之间的间隙完全被感光型聚合物介电材料填充，所述芯片的端子面与所述框架共平面，并且在所述芯片的端子面上设置有第一布线层，在所述芯片的背面上设置有第二布线层。
  2. 根据权利要求1所述的嵌入式芯片封装，其中所述感光型聚合物介电材料选自包括聚酰亚胺感光树脂或聚苯醚感光树脂的组别。
  3. 根据权利要求1所述的嵌入式芯片封装，其中所述框架还包括至少一个框架通孔柱，所述框架通孔柱延伸穿过从所述框架的第一框架面到第二框架面的框架高度。
  4. 根据权利要求1所述的嵌入式芯片封装，其中所述芯片的端子面包含金属端子触点，所述金属端子触点通过包围在感光型聚合物介电材料中的第一通孔柱导通连接所述第一布线层。
  5. 根据权利要求1所述的嵌入式芯片封装，在所述芯片的背面上形成有第二通孔柱，所述第二通孔柱被感光型聚合物介电材料包围。
  6. 根据权利要求5所述的嵌入式芯片封装，其中所述第二通孔柱导通连接芯片背面和第二布线层。
  7. 根据权利要求6所述的嵌入式芯片封装，其中所述芯片背面具有连接芯片端子的硅通孔，或者具有背对背堆叠的芯片使得芯片背面具有端子。
  8. 根据权利要求6所述的嵌入式芯片封装，其中所述第二布线层包括散热垫。
  9. 根据权利要求1所述的嵌入式芯片封装，其中在所述框架通孔柱在框架两侧的两个端面上分别形成有第三和第四通孔柱，其中所述第三通孔柱导通连 接所述第一布线层，所述第四通孔柱导通连接所述第二布线层。
  10. 根据权利要求1所述的嵌入式芯片封装，其中所述芯片包括选自集成电路、无源器件和有源器件中的至少一个。
  11. 根据前述权利要求中的任一项所述的嵌入式芯片封装，其中所述框架通孔柱、第一、第二、第三或第四通孔柱的材料包括铜。
  12. 一种制造嵌入式芯片封装的方法，包括以下步骤：
    ·获得由框架构成的芯片插座阵列，其中在框架中形成穿过所述框架高度的框架通孔柱；
    ·将所述芯片插座阵列放置在胶带上；
    ·将芯片的端子面朝下放入所述芯片插座阵列的被框架包围的空腔中；
    ·在芯片和框架上层压或涂覆感光型聚合物介电材料，使得感光型聚合物介电材料完全填充芯片与框架之间的间隙并覆盖芯片背面和框架的上表面；
    ·对感光型聚合物介电材料曝光并显影出第一图案，所述第一图案形成暴露出框架通孔柱在框架上表面的端部的第一盲孔和暴露出所述芯片背面的第二盲孔；
    ·移除所述胶带，在芯片的端子面和框架的下表面上层压或涂覆感光型聚合物介电材料；
    ·曝光并显影出第二图案，所述第二图案形成暴露出芯片的端子的第三盲孔和暴露出框架通孔柱在框架下表面的端部的第四盲孔；
    ·在第一图案和第二图案上施加金属种子层；
    ·在所述金属种子层上施加光刻胶层，图案化所述光刻胶层形成包括第一布线层和第二布线层的第三图案；和
    ·通过电镀铜，同时填充所述第一、第二和第三图案，形成第一、第二、第三和第四通孔柱以及第一布线层和第二布线层。
  13. 根据权利要求12所述的方法，其中所述感光型聚合物介电材料选自聚酰亚胺感光树脂或聚苯醚感光树脂。
  14. 根据权利要求12所述的方法，其中所述金属种子层包括Ti、W或Ti/W合金。
  15. 根据权利要求12所述的方法，其中所述第一布线层通过第一通孔柱导通 连接芯片端子触点，所述第二布线层通过第二通孔柱导通连接芯片的背面。
  16. 根据权利要求12所述的方法，其中所述框架通孔柱和第一、第二、第三和第四通孔柱的材料包括铜。
  17. 根据权利要求12所述的方法，还包括在电镀铜之后，移除光刻胶层并蚀刻掉暴露的金属种子层。
  18. 根据权利要求17所述的方法，还包括在所述第一和第二布线层上进行增层和重新布线以叠加构建附加布线层。
  19. 根据权利要求12所述的方法，还包括在第一和/或第二布线层上施加阻焊层。
  20. 根据权利要求12所述的方法，还包括将所述芯片插座阵列切割成单独的封装芯片。
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114361040A (zh) * 2021-11-18 2022-04-15 珠海越亚半导体股份有限公司 一种双面互联嵌入式芯片封装结构及其制造方法
TWI814612B (zh) * 2022-10-12 2023-09-01 創新服務股份有限公司 基板之電子元件植入方法及裝置

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111554639A (zh) * 2020-04-02 2020-08-18 珠海越亚半导体股份有限公司 嵌入式芯片封装及其制造方法
CN113053849B (zh) * 2021-03-04 2022-02-15 珠海越亚半导体股份有限公司 集成电感的嵌埋支撑框架、基板及其制作方法
CN113471347A (zh) * 2021-05-14 2021-10-01 南通越亚半导体有限公司 Led嵌埋封装基板及其制造方法
CN113451259B (zh) * 2021-05-14 2023-04-25 珠海越亚半导体股份有限公司 一种多器件分次嵌埋封装基板及其制造方法
US20230139175A1 (en) * 2021-11-01 2023-05-04 Micron Technology, Inc. Semiconductor device assemblies including monolithic silicon structures for thermal dissipation and methods of making the same
CN115103509A (zh) * 2022-05-06 2022-09-23 珠海越亚半导体股份有限公司 一体电感嵌埋基板及其制作方法
US20240021488A1 (en) * 2022-07-15 2024-01-18 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated Circuit Package and Method
CN117238894B (zh) * 2023-09-26 2024-07-09 江苏卓胜微电子股份有限公司 封装结构、芯片结构及其制备方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160307847A1 (en) * 2015-04-17 2016-10-20 Samsung Electro-Mechanics Co., Ltd. Electronic component package and method of manufacturing the same
CN106997870A (zh) * 2016-01-26 2017-08-01 珠海越亚封装基板技术股份有限公司 新型嵌入式封装
US20190035758A1 (en) * 2017-07-31 2019-01-31 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
CN110858548A (zh) * 2018-08-22 2020-03-03 深南电路股份有限公司 埋入式芯片及其制造方法
CN110867417A (zh) * 2018-08-27 2020-03-06 三星电子株式会社 半导体封装件
CN111554639A (zh) * 2020-04-02 2020-08-18 珠海越亚半导体股份有限公司 嵌入式芯片封装及其制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100867631B1 (ko) * 2007-02-01 2008-11-10 삼성전자주식회사 반도체 장치 및 그 제조 방법
US20110290540A1 (en) * 2010-05-25 2011-12-01 Samsung Electro-Mechanics Co., Ltd. Embedded printed circuit board and method of manufacturing the same
US20150279814A1 (en) * 2014-04-01 2015-10-01 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Embedded chips
US10381326B2 (en) * 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9666559B2 (en) * 2014-09-05 2017-05-30 Invensas Corporation Multichip modules and methods of fabrication
US9554469B2 (en) * 2014-12-05 2017-01-24 Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. Method of fabricating a polymer frame with a rectangular array of cavities
KR101952865B1 (ko) * 2016-10-10 2019-02-27 삼성전기주식회사 팬-아웃 반도체 패키지 및 감광성 수지 조성물
JP6858576B2 (ja) * 2017-01-30 2021-04-14 新光電気工業株式会社 半導体装置の製造方法
EP3478033A1 (en) 2017-10-25 2019-05-01 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Embedding component with pre-connected pillar in component carrier
KR102492796B1 (ko) * 2018-01-29 2023-01-30 삼성전자주식회사 반도체 패키지
KR102584960B1 (ko) * 2019-04-12 2023-10-05 삼성전기주식회사 반도체 패키지

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20160307847A1 (en) * 2015-04-17 2016-10-20 Samsung Electro-Mechanics Co., Ltd. Electronic component package and method of manufacturing the same
CN106997870A (zh) * 2016-01-26 2017-08-01 珠海越亚封装基板技术股份有限公司 新型嵌入式封装
US20190035758A1 (en) * 2017-07-31 2019-01-31 Samsung Electro-Mechanics Co., Ltd. Fan-out semiconductor package
CN110858548A (zh) * 2018-08-22 2020-03-03 深南电路股份有限公司 埋入式芯片及其制造方法
CN110867417A (zh) * 2018-08-27 2020-03-06 三星电子株式会社 半导体封装件
CN111554639A (zh) * 2020-04-02 2020-08-18 珠海越亚半导体股份有限公司 嵌入式芯片封装及其制造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114361040A (zh) * 2021-11-18 2022-04-15 珠海越亚半导体股份有限公司 一种双面互联嵌入式芯片封装结构及其制造方法
TWI814612B (zh) * 2022-10-12 2023-09-01 創新服務股份有限公司 基板之電子元件植入方法及裝置

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