TW201822317A - 整合扇出型封裝 - Google Patents

整合扇出型封裝 Download PDF

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Publication number
TW201822317A
TW201822317A TW106101817A TW106101817A TW201822317A TW 201822317 A TW201822317 A TW 201822317A TW 106101817 A TW106101817 A TW 106101817A TW 106101817 A TW106101817 A TW 106101817A TW 201822317 A TW201822317 A TW 201822317A
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Taiwan
Prior art keywords
antenna
integrated circuit
ground conductor
layer
integrated
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TW106101817A
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English (en)
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張守仁
蔡仲豪
王垂堂
吳凱強
劉明凱
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台灣積體電路製造股份有限公司
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Publication of TW201822317A publication Critical patent/TW201822317A/zh

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Abstract

一種整合扇出型封裝，其包括一絕緣包封體、一射頻積體電路、一天線、一接地導體以及一重配置線路結構。射頻積體電路包括多個導電端子。射頻積體電路、天線及接地導體嵌於絕緣包封體中，且接地導體位於射頻積體電路與天線之間。重配置線路結構配置於絕緣封包體上，且重配置線路結構與導電端子、天線以及接地導體電性連接。

Description

整合扇出型封裝
本發明的實施例是有關於一種半導體結構，且特別是有關於一種整合扇出型封裝(Integrated fan-out package)。
由於不同電子元件(例如是電晶體、二極體、電阻、電容等)的積體密度持續地增進，半導體工業經歷了快速成長。大部分而言，積集度的增進是來自於最小特徵尺寸(feature size)上不斷地縮減，這允許更多的較小元件能夠被整合到一預定區域內。較小的電子元件會需要比以往體積更小的封裝。一般而言，較小型的半導體元件封裝包括有四面扁平封裝(quad flat packages，QFPs)、接腳柵格陣列(pin grid array，PGA)封裝、球狀柵格陣列(ball grid array，BGA)封裝等等。目前，整合扇出型封裝由於其密實度(compactness)而趨於熱門，且整合扇出型封裝也逐漸被應用於射頻積體電路(RF-IC)。在射頻積體電路的封裝技術中，如何將射頻積體電路以及與射頻積體電路搭配的天線整合在單一整合扇出型封裝中，實為研發人員關注的議題之一。
本發明的一實施例提供一種整合扇出型封裝，其包括一絕緣包封體、一射頻積體電路、一天線、一接地導體以及一重配置線路結構。射頻積體電路包括多個導電端子。射頻積體電路、天線及接地導體嵌於絕緣包封體中，且接地導體位於射頻積體電路與天線之間。重配置線路結構配置於絕緣封包體上，且重配置線路結構與導電端子、天線以及接地導體電性連接。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
以下揭露內容提供用於實施所提供的標的之不同特徵的許多不同實施例或實例。以下所描述的構件及配置的具體實例是為了以簡化的方式傳達本揭露為目的。當然，這些僅僅為實例而非用以限制。舉例來說，於以下描述中，在第一特徵上方或在第一特徵上形成第二特徵可包括第二特徵與第一特徵形成為直接接觸的實施例，且亦可包括第二特徵與第一特徵之間可形成有額外特徵使得第二特徵與第一特徵可不直接接觸的實施例。此外，本揭露在各種實例中可使用相同的元件符號及/或字母來指代相同或類似的部件。元件符號的重複使用是為了簡單及清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
另外，為了易於描述附圖中所繪示的一個構件或特徵與另一組件或特徵的關係，本文中可使用例如「在...下」、「在...下方」、「下部」、「在…上」、「在…上方」、「上部」及類似術語的空間相對術語。除了附圖中所繪示的定向之外，所述空間相對術語意欲涵蓋元件在使用或操作時的不同定向。設備可被另外定向（旋轉90度或在其他定向），而本文所用的空間相對術語相應地作出解釋。
圖1至圖7為依照一些實施例所繪示的一種整合扇出型封裝的製造流程，圖8為圖1中圖案化導電層的立體示意圖，而圖9為圖4中圖案化導電層以及部分重配置線路結構的立體示意圖。
請參照圖1，提供一載板C，此載板C上具有剝離層DB以及介電層DI，其中剝離層DB與介電層DI依序堆疊於載板C上。意即，剝離層DB位於載板C以及介電層DI之間。在一些實施例中，載板C例如是玻璃基板，而剝離層DB例如是形成於玻璃基板上的光熱轉換(light-to-heat conversion, LTHC)釋放層，且介電層DI例如為形成於剝離層DB上的聚苯噁唑(PBO)層。然而，本發明不限定載板C、剝離層DB以及介電層DI的材質。在其他可行的實施例中，介電層DI可被省略；換言之，僅有剝離層DB形成於載板C上。
如圖1所示，接著，於介電層DI上形成一圖案化導電層110。在一些實施例中，前述的圖案化導電層110是藉由種子層濺鍍(seed layer sputtering)、微影、電鍍、蝕刻以及光阻移除製程所形成。詳言之，圖案化導電層110的製作方法包括下列步驟。首先，可於介電層DI的表面上以濺鍍方式形成一種子層（例如，鈦/銅種子層），之後進行光阻的塗佈，並以微影製程將特定圖案轉移至光阻上，以使種子層的部分區域能夠被光阻所暴露。隨後，以經圖案化後之光阻為罩幕進行電鍍製程，以使導電材料能夠被電鍍於被光阻所暴露出的種子層上。之後，再以電鍍形成之導電材料為罩幕，將未被導電材料所覆蓋的種子層移除以完成圖案化導電層110的製作。舉例來說，前述圖案化導電層110的材料包括銅或其他合適的金屬。
請參照圖1與圖8，圖案化導電層110至少包括相互電性絕緣的至少一個天線112以及至少一個接地導體114。圖1中繪示出二個天線112以及四個接地導體114作為示例，然而，本發明並不限定天線112與接地導體114的數量，前述天線112與接地導體114的數量可依據實際的設計需求而作出適當的更動。在一些實施例中，所述至少一個天線112例如為偶極天線(Dipole antenna)，而所述至少一個天線112包括相互分離的第一天線部112a以及一第二天線部112b，且第一天線部112a以及第二天線部112b例如皆為L形之天線部，如圖8所示。所述至少一個接地導體114例如為一個或是多個相互平行之板狀接地導體。然而，本發明並不限定第一天線部112a、第二天線部112b以及接地導體114的形狀，前述第一天線部112a、第二天線部112b以及接地導體114的形狀可依據實際的設計需求而作出適當的更動。所述至少一個接地導體114除了提供天線112所需的接地功能之外，所述至少一個接地導體114亦可具有反射電磁波的功能，以反射來自於天線112（即第一天線部112a以及一第二天線部112b）所發出的電磁波。換言之，所述至少一個接地導體114可被視為一電磁波反射件，且此電磁波反射件與天線112電性絕緣。在其他可行的實施例中，圖案化導電層110可進一步包括多個用以與重配置導電層144（繪示於圖4）電性連接的導電柱體(conductive vias)。
由於圖案化導電層110中的天線112與接地導體114是藉由同一電鍍製程所製作，因此天線112與接地導體114的材質與高度實質相同。
在其他可行的實施例中，圖案化導電層110除了包括相互電性絕緣的天線112以及接地導體114之外，圖案化導電層110可進一步包括導電柱體（未繪示）。值得注意的是，導電柱體可與天線112以及接地導體114一併製作。換言之，導電柱體、天線112以及接地導體114可藉由同一電鍍製程形成，且導電柱體、天線112以及接地導體114可為相同材質。
請參照圖2，將一射頻積體電路120拾取並且放置於介電層DI上，以使各個接地導體114分別位於射頻積體電路120與對應的天線112之間。射頻積體電路120具有多個導電端子122以及保護層124，其中導電端子122例如為銅柱體(copper pillars)或其他適合的導電柱體(conductive pillars)，導電端子122分佈於射頻積體電路120的主動表面120a上，而保護層124位於射頻積體電路120的主動表面120a上，以覆蓋住前述的導電端子122。舉例而言，射頻積體電路120是藉由晶粒附著膜(die attach film, DAF)、黏附膏等方式附著或黏附於介電層DI上。在其他可行的實施例中，可將多個射頻積體電路120拾取並且放置到介電層DI上，其中被拾取並且放置於介電層DI上的射頻積體電路120可排列成陣列。當被設置於介電層DI上的射頻積體電路120被排列成陣列時，天線112與接地導體114的使用數量為多個，且前述之天線112與接地導體114可被分成多個群組。射頻積體電路120的數目對應於天線112以及接地導體114的群組數目。
如圖2所示，保護層124的頂表面例如是低於天線112與接地導體114的頂表面，且保護層124的頂表面例如是高於導電端子122的頂表面。然而，本發明並不僅限於此。在另一些實施例中，保護層124的頂表面可以實質上對齊天線112與接地導體114的頂表面，且保護層124的頂表面可高於導電端子122的頂表面。
如圖2所示，一個或多個射頻積體電路120可在天線112與接地導體114形成之後才被設置於介電層DI上。然而，本發明並不僅限於此。在其他可行的實施例中，一個或多個射頻積體電路120可在天線112與接地導體114形成之前被設置於介電層DI上。
在完成射頻積體電路120的設置以及天線112與接地導體114的製作之後，於介電層DI上形成絕緣材料130以覆蓋住射頻積體電路120、天線112與接地導體114。在一些實施例中，絕緣材料130是由模製製程(molding process)所形成的封裝膠體 (molding compound)。射頻積體電路120的導電端子122以及保護層124被絕緣材料130所包覆或覆蓋。換言之，射頻積體電路120的導電端子122以及保護層124在此階段並不會被顯露出來而獲得一定程度的保護。在一些實施例中，前述之絕緣材料130例如為環氧化合物或其他合適的樹脂。
請參照圖2與圖3，接著，對絕緣材料130進行研磨直到天線112、接地導體114、導電端子122以及保護層124的頂表面被暴露出來。在一些實施例中，前述絕緣材料130的研磨製程包括機械研磨(mechanical grinding)及/或化學機械研磨(chemical mechanical polishing, CMP)。
在絕緣材料130被研磨之後，絕緣包封體130a會形成於介電層DI上，且在對絕緣材料130進行研磨製程期間，部分的保護層124會被研磨而形成保護層124a。在一些實施例中，在對絕緣材料130以及保護層124進行研磨製程期間，天線112與接地導體114也會被部分研磨而形成天線112’與接地導體114’。如圖3所示，經過研磨後的天線112’與接地導體114’即構成圖案化導電層110’。
如圖3所示，經過研磨後的絕緣包封體130a會包覆射頻積體電路120的側壁，且絕緣包封體130a被天線112’及接地導體114’所貫穿。換言之，射頻積體電路120、天線112’以及接地導體114’會嵌於絕緣包封體130a之中。值得注意的是，經過研磨後的天線112’與接地導體114’（或電磁波反射件）的高度與經過研磨後的絕緣包封體130a的高度實質上相同。
請參照圖4至圖5以及圖9，在形成絕緣包封體130a之後，於絕緣包封體130a、天線112’、接地導體114’以及保護層124a上形成重配置線路結構140。如圖4與圖5所示，本實施例之重配置線路結構140包括彼此交替堆疊的多個內介電層(inter-dielectric layers)142以及多個重配置導電層144，且重配置導電層144會與射頻積體電路120的導電端子122以及嵌於絕緣包封體130a中的天線112’及接地導體114’電性連接。如圖4與圖9所示，最底層的內介電層142局部覆蓋於絕緣包封體130a、天線112’、接地導體114’以及保護層124a上，以將天線112’、接地導體114’以及導電端子122的部分區域暴露，而最底層的重配置導電層144則配置於最底層的內介電層142上。最底層的內介電層142可具有多個暴露出天線112’、接地導體114’以及導電端子122的接觸開口。此外，嵌於絕緣包封體130a中的天線112’可透過最底層的重配置導電層144與射頻積體電路120的導電端子122電性連接，且嵌於絕緣包封體130a中的多個接地導體114’可透過最底層的重配置導電層144彼此相互連接。在其他可行的實施例中，嵌於絕緣包封體130a中的多個接地導體114’亦可透過最底層的重配置導電層144而與射頻積體電路120的導電端子122（即接地端子）電性連接。
圖10至圖14為依照不同實施例所繪示的圖案化導電層以及部分重配置導電層的立體示意圖。請參照圖10，本實施例之圖案化導電層110a包括多組天線112’以及多個接地導體114a，其中每個接地導體114a分佈於一組天線112’與射頻積體電路120之間，而天線112’透過部分的重配置導電層144與射頻積體電路120電性連接，且接地導體114a透過部分的重配置導電層144彼此電性連接。如圖10所示，四組天線112’分別分佈於射頻積體電路120的四側，且四個接地導體114a分別平行於射頻積體電路120的四個側邊而設置。然而，本實施例不限定天線112’與接地導體114a的數量。
請參照圖11，本實施例之圖案化導電層110b包括多組天線112’以及多個接地導體114b，其中每個接地導體114b分佈於一組天線112’與射頻積體電路120之間，而天線112’透過部分的重配置導電層144與射頻積體電路120電性連接，且接地導體114b透過部分的重配置導電層144彼此電性連接。如圖11所示，四組天線112’分別分佈於射頻積體電路120的四側，而四個接地導體114b分別具有朝向各組天線112’的凹口，且四個接地導體114b沿著射頻積體電路120的四個側邊設置。然而，本實施例不限定天線112’與接地導體114b的數量。
請參照圖12，本實施例之圖案化導電層110c包括多組天線112’、多個接地導體114a以及多個接地導體114c，其中每個接地導體114a分佈於一組天線112’與射頻積體電路120之間，接地導體114c對應於射頻積體電路120的角落分佈，且各個接地導體114c可用以分隔與其相鄰的兩組天線112’。天線112’透過部分的重配置導電層144與射頻積體電路120電性連接，且接地導體114a以及接地導體114c透過部分的重配置導電層144彼此電性連接。如圖12所示，四組天線112’分別分佈於射頻積體電路120的四側，四個接地導體114a分別平行於射頻積體電路120的四個側邊而設置。然而，本實施例不限定天線112’、接地導體114a以及接地導體114c的數量。
請參照圖13，本實施例之圖案化導電層110d包括多組天線112’、多個接地導體114a以及一遮蔽環(shielding ring)116，其中每個接地導體114a分佈於一組天線112’與射頻積體電路120之間，遮蔽環116環繞射頻積體電路120並且位於接地導體114a與射頻積體電路120之間，以遮蔽射頻積體電路120對於各組天線112’的干擾。天線112’透過部分的重配置導電層144與射頻積體電路120電性連接，且接地導體114a透過部分的重配置導電層144彼此電性連接。如圖13所示，四組天線112’分別分佈於射頻積體電路120的四側，四個接地導體114a分別平行於射頻積體電路120的四個側邊而設置，且遮蔽環116的尺寸略大於射頻積體電路120的尺寸。然而，本實施例不限定天線112’、接地導體114a以及遮蔽環116的數量。
請參照圖14，本實施例之圖案化導電層110e包括多組天線112’以及一遮蔽環116，其中遮蔽環116接地，遮蔽環116分佈於各組天線112’與射頻積體電路120之間，且遮蔽環116環繞射頻積體電路120以遮蔽射頻積體電路120對於各組天線112’的干擾。在圖14所繪示的實施例中，由於遮蔽環116接地，因此遮蔽環116可以被視為接地導體。天線112’透過部分的重配置導電層144與射頻積體電路120電性連接。如圖14所示，四組天線112’分別分佈於射頻積體電路120的四側，且接地的遮蔽環116的尺寸略大於射頻積體電路120的尺寸。然而，本實施例不限定天線112’以及遮蔽環116的數量。
如圖5所示，重配置線路結構140中最頂層的重配置導電層144包括多個接墊。在一些實施例中，前述之接墊包括用來植球(ball mount)的多個球底金屬層(under-ball metallurgy, UBM)圖案144a及/或用來設置被動元件的至少一個連接墊144b。本發明並不限制球底金屬層圖案144a以及連接墊144b的數目。
請參照圖6，在形成重配置線路結構140之後，將多個導電球150置於球底金屬層圖案144a上，並將至少一個被動元件160設置於連接墊144b上。在一些實施例中，導電球150可以植球製程的方式被設置於球底金屬層圖案144a上，而被動元件160可設置於連接墊144b上並且藉由焊料與連接墊144b電性連接。導電球150透過重配置線路結構140與多個天線112’、接地導體114’以及射頻積體電路120的導電端子122中的至少一者電性連接。此外，被動元件160透過重配置線路結構140與多個天線112’、接地導體114’以及射頻積體電路120的導電端子122中的至少一者電性連接。
參照圖6以及圖7，在將導電球150以及被動元件160設置於重配置線路結構140之後，將形成於絕緣包封體130a的表面上的介電層DI從剝離層DB上剝離，以使介電層DI與剝離層DB以及載板C分離。在一些實施例中，前述剝離層DB(例如光熱轉換釋放層)可被紫外光雷射照射而使介電層DI從載板C上剝離。如圖7所示，在形成導電球150與被動元件160之後，射頻積體電路120的整合扇出型封裝100便已初步完成。
在前述的實施例中，由於射頻積體電路120與天線112’是嵌於整合扇出型封裝100的絕緣包封體130a之中，因此天線112’不會佔據重配置線路結構140中的佈線面積，使得重配置線路結構140具有較佳的線路佈局彈性。此外，由於絕緣包封體130a具有一定的厚度及/或體積以容納天線112’以及射頻積體電路120，因此射頻積體電路120與天線112’的整合不會導致整合扇出型封裝的體積大幅增加。
本發明的一實施例提供一種整合扇出型封裝，其包括一絕緣包封體、一射頻積體電路、一天線、一接地導體以及一重配置線路結構。射頻積體電路包括多個導電端子。射頻積體電路、天線及接地導體嵌於絕緣包封體中，且接地導體位於射頻積體電路與天線之間。重配置線路結構配置於絕緣封包體上，且重配置線路結構與導電端子、天線以及接地導體電性連接。
在所述的整合扇出型封裝中，天線包括一偶極天線。
在所述的整合扇出型封裝中，天線與接地導體的高度實質相同。
在所述的整合扇出型封裝中，接地導體包括電磁波反射件。
在所述的整合扇出型封裝更包括多個導電球，導電球配置於重配置線路結構上且與重配置線路結構電性連接，其中導電球透過重配置線路結構與天線、接地導體以及射頻積體電路的導電端子中的至少一者電性連接。
在所述的整合扇出型封裝更包括至少一個被動元件，被動元件配置於重配置線路結構上且與重配置線路結構電性連接，其中被動元件透過重配置線路結構與天線、接地導體以及射頻積體電路的導電端子中的至少一者電性連接。
所述的整合扇出型封裝更包括一遮蔽環，其中遮蔽環環繞射頻積體電路，且遮蔽環位於接地導體與射頻積體電路之間。
所述的整合扇出型封裝中，接地導體包括遮蔽環以環繞射頻積體電路。
本發明的另一實施例提供一種整合扇出型封裝，其包括一絕緣包封體、一射頻積體電路、多個天線、多個電磁波反射件以及一重配置線路結構。射頻積體電路包括多個導電端子。射頻積體電路、天線及電磁波反射件嵌於絕緣包封體中，而各個電磁波反射件分別位於射頻積體電路與對應的天線之間以反射對應的天線所發出的電磁波。重配置線路結構配置於絕緣封包體上，重配置線路結構與導電端子、天線以及電磁波反射件電性連接，且多個電磁波反射件透過重配置線路結構彼此相連接。
在所述的整合扇出型封裝中，天線包括偶極天線。
在所述的整合扇出型封裝中，電磁波反射件與天線電性絕緣，且電磁波反射件係接地。
在所述的整合扇出型封裝中，天線、電磁波反射件以及絕緣包封體的高度實質相同。
在所述的整合扇出型封裝更包括多個導電球，導電球配置於重配置線路結構上且與重配置線路結構電性連接，其中導電球透過重配置線路結構與天線、接地導體以及射頻積體電路的導電端子中的至少一者電性連接。
在所述的整合扇出型封裝更包括至少一個被動元件，被動元件配置於重配置線路結構上且與重配置線路結構電性連接，其中被動元件透過重配置線路結構與天線、接地導體以及射頻積體電路的導電端子中的至少一者電性連接。
所述的整合扇出型封裝更包括一遮蔽環，其中遮蔽環環繞射頻積體電路，且遮蔽環位於電磁波反射件與射頻積體電路之間。
本發明的又一實施例提供一種整合扇出型封裝的製造方法，包括下列步驟：於一載板上形成一圖案化導電層，其中圖案化導電層包括相互電性絕緣的一天線以及一接地導體；於載板上設置一射頻積體電路，射頻積體電路包括多個導電端子，且接地導體位於射頻積體電路與天線之間；於載板上形成一絕緣包封體，以使射頻積體電路、天線以及接地導體嵌於絕緣包封體中；以及於絕緣封包體上形成一重配置線路結構，其中重配置線路結構與導電端子、天線以及接地導體電性連接，且天線透過重配置線路結構與導電端子電性連接。
在整合扇出型封裝的製造方法中，天線以及接地導體藉由同一電鍍製程所形成。
在整合扇出型封裝的製造方法中，射頻積體電路是在天線與接地導體形成之前被設置於載板上。
在整合扇出型封裝的製造方法中，射頻積體電路是在天線與接地導體形成之後被設置於載板上。
整合扇出型封裝的製造方法更包括：在形成重配置線路結構之後，令載板與絕緣封包體分離。
在本發明的實施例中，由於射頻積體電路與天線是嵌於整合扇出型封裝的絕緣包封體之中，因此天線的整合不會影響到整合扇出型封裝中的重配置線路結構的線路佈局彈性。
以上概述了多個實施例的特徵，使本領域具有通常知識者可更佳了解本發明的態樣。本領域具有通常知識者應理解，其可輕易地使用本發明作為設計或修改其他製程與結構的依據，以實行本文所介紹的實施例的相同目的及/或達到相同優點。本領域具有通常知識者還應理解，這種等效的配置並不悖離本發明的精神與範疇，且本領域具有通常知識者在不悖離本發明的精神與範疇的情況下可對本文做出各種改變、置換以及變更。
C‧‧‧載板
DB‧‧‧剝離層
DI‧‧‧介電層
100‧‧‧整合扇出型封裝
110、110’、110a~110e‧‧‧圖案化導電層
112、112’‧‧‧天線
112a‧‧‧第一天線部
112b‧‧‧第二天線部
114、114’、114a~114c‧‧‧接地導體
116‧‧‧遮蔽環
120‧‧‧射頻積體電路
120a‧‧‧主動表面
122‧‧‧導電端子
124、124a‧‧‧保護層
130‧‧‧絕緣材料
130a‧‧‧絕緣包封體
140‧‧‧重配置線路結構
142‧‧‧內介電層
144‧‧‧重配置導電層
144a‧‧‧球底金屬層圖案
144b‧‧‧連接墊
150‧‧‧導電球
160‧‧‧被動元件
圖1至圖7為依照一些實施例所繪示的一種整合扇出型封裝的製造流程。 圖8為圖1中圖案化導電層的立體示意圖。 圖9為圖4中圖案化導電層以及部分重配置線路結構的立體示意圖。 圖10至圖14為依照不同實施例所繪示的圖案化導電層以及部分重配置線路結構的立體示意圖。

Claims (1)

  1. 一種整合扇出型封裝，包括： 一絕緣包封體； 一射頻積體電路，包括多個導電端子； 一天線； 一接地導體，其中該射頻積體電路、該天線及該接地導體嵌於該絕緣包封體中，且該接地導體位於該射頻積體電路與該天線之間；以及 一重配置線路結構，配置於該絕緣封包體上，且該重配置線路結構與該些導電端子、該天線以及該接地導體電性連接。
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