CN109309080A - 集成电路封装 - Google Patents

集成电路封装 Download PDF

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Publication number
CN109309080A
CN109309080A CN201710784697.XA CN201710784697A CN109309080A CN 109309080 A CN109309080 A CN 109309080A CN 201710784697 A CN201710784697 A CN 201710784697A CN 109309080 A CN109309080 A CN 109309080A
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CN
China
Prior art keywords
layer
conductive
integrated circuit
circuit package
semiconductor element
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Pending
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CN201710784697.XA
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English (en)
Inventor
陈洁
陈宪伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN109309080A publication Critical patent/CN109309080A/zh
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Abstract

提供一种集成电路封装，所述集成电路封装包括至少一个集成电路组件、至少一个电磁干扰屏蔽层及绝缘包封体。所述至少一个集成电路组件包括有源表面、连接到所述有源表面的多个侧壁、以及从所述有源表面突出的多个导电柱。所述至少一个电磁干扰屏蔽层覆盖所述至少一个集成电路组件的所述侧壁，且所述至少一个电磁干扰屏蔽层为电接地。所述绝缘包封体包封所述至少一个集成电路组件及所述至少一个电磁干扰屏蔽层，且所述至少一个集成电路组件的所述导电柱能够被所述绝缘包封体暴露出。还提供制作集成电路封装的方法。

Description

集成电路封装
技术领域
本发明的实施例涉及一种集成电路封装。
背景技术
由于各种电子组件(即，晶体管、二极管、电阻器、电容器等)的集成密度的持续提高，半导体行业已经历快速增长。在很大程度上，集成密度的此种提高来自于最小特征大小(minimum feature size)的持续减小，此使得更多较小的组件能够集成到给定区域中。这些较小的电子组件也需要与先前的封装相比利用较小区域的较小的封装。半导体组件的一些较小类型的封装包括方形扁平封装(quad flat package，QFP)、引脚栅阵列(pin gridarray，PGA)封装、球栅阵列(ball grid array，BGA)封装等等。
当前，集成扇出型封装(integrated fan-out package)因其紧凑性而正变得日渐流行。在当前制作的集成扇出型封装中，可使用共形地形成在封装的外表上的电磁干扰(electromagnetic interference，EMI)屏蔽层来屏蔽来自环境的电磁干扰。
发明内容
根据本发明的一些实施例，提供一种集成电路封装，所述集成电路封装包括至少一个集成电路组件、至少一个电磁干扰屏蔽层及绝缘包封体。所述至少一个集成电路组件包括有源表面、连接到所述有源表面的多个侧壁、以及从所述有源表面突出的多个导电柱。所述至少一个电磁干扰屏蔽层覆盖所述至少一个集成电路组件的所述侧壁，且所述至少一个电磁干扰屏蔽层为电接地。所述绝缘包封体包封所述至少一个集成电路组件及所述至少一个电磁干扰屏蔽层，且所述至少一个集成电路组件的所述导电柱能够被所述绝缘包封体暴露出。
根据本发明的替代性实施例，提供一种制作集成电路封装的方法。所述方法包括：提供晶片，所述晶片包括形成在所述晶片上的多个导电柱；在所述晶片上形成保护材料层以覆盖所述导电柱；执行晶片切割工艺，以形成多个半导体管芯，其中所述半导体管芯中的每一者包括所述导电柱的部分及覆盖所述导电柱的所述部分的保护顶盖；形成电磁干扰屏蔽层以覆盖所述半导体管芯中的至少一个半导体管芯的侧壁；以及使用绝缘材料在侧向上包封所述半导体管芯中的所述至少一个半导体管芯及所述电磁干扰屏蔽层。
根据本发明的又一些替代性实施例，提供一种制作集成电路封装的方法。所述方法包括：提供晶片，所述晶片包括形成在所述晶片上的多个第一导电柱；在所述晶片上形成第一保护材料层以覆盖所述第一导电柱；执行晶片切割工艺，以形成多个第一半导体管芯，其中所述第一半导体管芯中的每一者包括所述第一导电柱的部分及覆盖所述第一导电柱的所述部分的第一保护顶盖；形成电磁干扰屏蔽层以覆盖所述第一半导体管芯中的至少一个第一半导体管芯的侧壁；在载体上提供第二半导体管芯及所述第一半导体管芯中的所述至少一个第一半导体管芯，其中所述第二半导体管芯包括多个第二导电柱及覆盖所述第二导电柱的第二保护顶盖；以及使用绝缘材料在侧向上包封所述电磁干扰屏蔽层、所述第一半导体管芯中的所述至少一个第一半导体管芯及所述第二半导体管芯。
附图说明
结合附图阅读以下详细说明，会最好地理解本发明的各个方面。应注意，根据本行业中的标准惯例，各种特征并非按比例绘制。事实上，为论述清晰起见，可任意增大或减小各种特征的尺寸。
图1至图5示意性地说明制作根据本发明一些实施例的半导体管芯的工艺流程。
图6至图13示意性地说明制作根据本发明一些实施例的集成扇出型封装的工艺流程。
图14是说明根据本发明一些实施例的叠层封装(package-on-package，POP)结构的剖视图。
图15至图25示意性地说明制作根据本发明一些替代性实施例的集成扇出型封装的工艺流程。
图26是说明根据本发明一些替代性实施例的叠层封装(POP)结构的剖视图。
图27至图33示意性地说明制作根据本发明又一些替代性实施例的集成扇出型封装的工艺流程。
[符号的说明]
100：集成电路组件
100a：半导体管芯
100a’：集成电路组件
100b：第二半导体管芯
100b’：第二集成电路组件
110：半导体衬底
110a：半导体衬底
110b：第二半导体衬底
120：内连线结构
120a：内连线结构
120b：第二内连线结构
122：层间介电层
124：图案化导电层
130：导电柱
130a：第一导电柱
130b：第二导电柱
140：保护材料层
140a：保护顶盖
140a’：保护顶盖
140b、140b’：第二保护顶盖
150、150a：导电层
150a1：顶盖层
150a2：电磁干扰屏蔽层
210：绝缘材料
210’：绝缘包封体
220：第一重布线路结构
222：介电层
224：重布线导电层
230：垫
230a：球下金属图案
230b：连接垫
240、260：导电球
250：无源组件
270：第二重布线路结构
272：介电层
274：重布线导电层
300：半导体装置
A：有源表面
AF：粘合膜
AR：容置凹槽
C：载体
CAP：导电顶盖
DAF：管芯贴合膜
DB：剥离层
DI：介电层
O1、O3、O4：开口
O2：接触开口
PR：图案化光刻胶
S：晶种层
S1：第一表面
S2：第二表面
SL：切割道
SW：侧壁
TIV：导电穿孔
TR：托盘
W：晶片
具体实施方式
以下公开内容提供用于实作所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及构造的具体实例以简化本公开内容。当然，这些仅为实例且不旨在进行限制。举例来说，以下说明中将第一特征形成在第二特征“之上”或第二特征“上”可包括其中第一特征及第二特征被形成为直接接触的实施例，且也可包括其中第一特征与第二特征之间可形成有附加特征、进而使得所述第一特征与所述第二特征可能不直接接触的实施例。另外，本公开内容可能在各种实例中重复使用参考编号及/或字母。这种重复使用是出于简洁及清晰的目的，而不是自身表示所论述的各种实施例及/或配置之间的关系。
此外，为易于说明，本文中可能使用例如“之下(beneath)”、“下面(below)”、“下部的(lower)”、“上方(above)”、“上部的(upper)”等空间相对性用语来阐述图中所示的一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设备可具有其他取向(旋转90度或处于其他取向)且本文中所用的空间相对性描述语可同样相应地进行解释。
还可包括其他特征及工艺。举例来说，可包括测试结构，以帮助对三维(3D)封装或三维集成电路(3DIC)装置进行验证测试。所述测试结构可例如包括在重布线层中或在衬底上形成的测试垫，所述测试垫使得能够对三维封装或三维集成电路进行测试、对探针及/或探针卡(probe card)进行使用等。可对中间结构以及最终结构执行验证测试。另外，本文中所公开的结构及方法可结合包括对已知良好管芯进行中间验证的测试方法而使用，以提高良率(yield)并降低成本。
图1至图5示意性地说明制作根据本发明一些实施例的半导体管芯的工艺流程。
参照图1，提供晶片W，晶片W包括排列成阵列的多个集成电路组件100。如图1中所示，在对晶片W执行晶片切割工艺(wafer dicing process)之前，晶片W中的集成电路组件100是彼此连接的。在一些实施例中，集成电路组件100中的每一者包括半导体衬底110及设置在半导体衬底110上的内连线结构120。半导体衬底110可为硅衬底，所述硅衬底包括形成在所述硅衬底中的有源组件(例如，晶体管等)及无源组件(例如，电阻器、电容器、电感器等)。内连线结构120可包括交替堆叠的多个层间介电层122及多个图案化导电层124。举例来说，层间介电层122可为氧化硅层、氮化硅层、氮氧化硅层或由其他适合的介电材料形成的介电层，且图案化导电层124可为图案化铜层或其他适合的图案化金属层。
如图1中所示，最顶部图案化导电层124被层间介电层120中的最顶部层间介电层122覆盖，且最顶部图案化导电层124被最顶部层间介电层122的多个开口O1暴露出。此外，晶片W具有前表面及与所述前表面相对的背表面，其中最顶部图案化导电层124在晶片W的前表面处暴露出，且粘合膜AF与晶片W的背表面粘合且整体地覆盖晶片W的所述背表面。在一些实施例中，为方便后续工艺(例如，导电柱的镀覆工艺(plating process)、单体化工艺(singulation process)等)，可通过粘合膜AF暂时将晶片W与支撑件(图中未示出)粘合在一起。
参照图2，在被开口O1暴露出的最顶部图案化导电层124上形成多个导电柱130。在一些实施例中，可通过镀覆工艺来形成导电柱130。在此种实施例中，首先，可将晶种层(例如，Ti/Cu晶种层)溅镀在晶片W的前表面上，接着，在所述晶种层上形成具有预定图案的图案化光刻胶(photoresist)。将其上具有所述晶种层及所述图案化光刻胶的晶片W浸入至镀覆槽(plating bath)中，进而使得导电柱130镀覆至所述晶种层的被所述图案化光刻胶暴露出的部分区域上。导电柱130对应于最顶部层间介电层122的开口O1。在将导电柱130镀覆至所暴露出的晶种层上之后，移除所述图案化光刻胶。此后，利用导电柱130作为硬掩模将所述晶种层图案化(例如，蚀刻)。导电柱130可为铜柱或其他适合的金属柱。
如图2中所示，为了检验导电柱130及/或集成电路组件100的电特性，可在导电柱130的顶表面上形成多个导电顶盖CAP。在一些实施例中，导电顶盖CAP可为焊料顶盖。举例来说，上述焊料顶盖可为无铅焊料顶盖。接着，在导电顶盖CAP上执行芯片探测工艺，以检验导电柱130及/或集成电路组件100的电特性。
参照图3，在晶片W的前表面之上形成保护材料层140，进而使得导电顶盖CAP及导电柱130被保护材料层140包封及保护。如图3中所示，保护材料层140例如具有实质上平坦的顶表面。在一些实施例中，保护材料层140可为被形成为整体覆盖晶片W的前表面以包封导电顶盖CAP及导电柱130的聚酰亚胺(polyimide，PI)层、聚苯并恶唑(polybenzoxazole，PBO)层或其他适合的聚合物(或有机)层。
参照图4，在晶片W的前表面之上形成保护材料层140之后，执行晶片切割工艺或晶片单体化工艺，以使晶片W沿切割道SL被切割而使晶片W单体化成多个半导体管芯100a。经单体化的半导体管芯100a中的每一者包括半导体衬底110a、设置在半导体衬底110a上的内连线结构120a、部份的导电柱130及保护顶盖140a。保护顶盖140a包封所述部份的导电柱130且覆盖内连线结构120a。在晶片切割工艺期间，导电柱130被保护顶盖140a保护而免受损坏。
在晶片切割工艺期间，还将与晶片W的背表面粘合的粘合膜AF切割成多个管芯贴合膜DAF且使管芯贴合膜DAF中的每一者分别与经单体化的半导体管芯100a的背表面粘合。如图4中所示，经单体化的半导体管芯100a被保护顶盖140a及管芯贴合膜DAF保护。
参照图5，在执行晶片切割工艺之后，从上述支撑件拾取经单体化的半导体管芯100a并放置在托盘TR上。在一些实施例中，可将放置在托盘TR上的半导体管芯100a排列成阵列且可通过管芯贴合膜DAF将半导体管芯100a与托盘TR粘合在一起。在此种实施例中，托盘TR可包括排列成阵列的多个容置凹槽AR且经单体化的半导体管芯100a中的每一者被分别放置在容置凹槽AR中的一个容置凹槽AR中。托盘TR的容置凹槽AR使得托盘TR可平稳地承载经单体化的半导体管芯100a。
在将半导体管芯100a放置在托盘TR上并且通过管芯贴合膜DAF暂时将半导体管芯100a与托盘TR粘合在一起之后，在每一半导体管芯100a的顶表面及侧壁上共形地形成(例如，沉积)导电层150。在一些实施例中，导电层150可进一步覆盖管芯贴合膜DAF的侧壁及托盘TR的顶表面。举例而言，可通过溅镀工艺或其他适合的沉积工艺来沉积导电层150。另外，导电层150的材料可包括铜、铝或能够屏蔽电磁干扰的其他适合的导电材料。导电层150的厚度可介于约1微米至约3微米范围内。应注意，导电层150能够屏蔽来自环境的电磁干扰(EMI)以确保半导体管芯100a的性能。
在一些实施例中，托盘TR与管芯贴合膜DAF之间的粘合小于半导体管芯100a与管芯贴合膜DAF之间的粘合，使得半导体管芯100a及管芯贴合膜DAF能够从托盘TR被拾取及从托盘TR剥离。
图6至图13示意性地说明制作根据本发明一些实施例的集成扇出型封装的工艺流程。
参照图6，提供其上形成有剥离层(de-bonding layer)DB及介电层DI的载体C，其中剥离层DB处于载体C与介电层DI之间。在一些实施例中，举例来说，载体C是玻璃衬底，剥离层DB是形成在所述玻璃衬底上的光-热转换(light-to-heat conversion，LTHC)释放层，且介电层DI是形成在剥离层DB上的聚苯并恶唑(PBO)层。在替代性实施例中，剥离层DB可为粘性(stickiness)通过光固化工艺(photo-curing process)而被降低的光固化释放膜(photo-curable release film)或粘性通过热固化工艺(thermal-curing process)而被降低的热固化释放膜(thermal curable release film)，且介电层DI可由其他感光性的或非感光性的介电材料制成。在提供其上形成有剥离层DB及介电层DI的载体C之后，在介电层DI上形成多个导电穿孔TIV。在一些实施例中，所述多个导电穿孔TIV是通过光刻胶涂布(photoresist coating)、光刻、镀覆及光刻胶剥除(photoresist stripping)工艺形成。举例来说，导电穿孔TIV包括铜杆(copper post)或其他适合的金属杆。
参照图5及图7，当从托盘TR(示出于图5中)剥离半导体管芯100a及管芯贴合膜DAF时，将自动地形成覆盖半导体管芯100a的顶表面及侧壁的多个导电层150a(示出于图7中)。导电层150中的每一者分别包括顶盖层150a1及连接到顶盖层150a1的电磁干扰屏蔽层150a2。导电层150a的顶盖层150a1覆盖半导体管芯100a的顶表面，且导电层150a的电磁干扰屏蔽层150a2覆盖半导体管芯100a的侧壁。如图7中所示，拾取并且在介电层DI上放置被导电层150a覆盖的至少一个上述经单体化的半导体管芯100a。将半导体管芯100a通过管芯贴合膜DAF贴合或粘合在介电层DI上。
在一些替代性实施例中，可从同一晶片W切割出其上覆盖有导电层150a的两个或更多个半导体管芯100a并且将所述两个或更多个半导体管芯100a放置在介电层DI上。可将放置在介电层DI上的半导体管芯100a排列成阵列。在此种实施例中，将放置在介电层DI上的半导体管芯100a排列成阵列，且可在半导体管芯100a周围排列导电穿孔TIV。
参照图7，在形成导电穿孔TIV之后，可拾取并且将其上覆盖有导电层150a的半导体管芯100a放置在介电层DI上。然而，本发明并不仅限于此。在一些替代性实施例中，在形成导电穿孔TIV之前，可拾取并且将其上覆盖有导电层150a的半导体管芯100a放置在介电层DI上。
如图7中所示，在介电层DI上形成绝缘材料210，以覆盖半导体管芯100a、导电层150a及导电穿孔TIV。在一些实施例中，绝缘材料210是通过包覆模制工艺(over-moldingprocess)(例如，压缩模塑工艺(compression molding process))形成的模制化合物。半导体管芯100a的导电柱130及保护顶盖140a不被绝缘材料210显露出且被绝缘材料210保护。在一些实施例中，绝缘材料210的材料包括环氧树脂或其他适合的介电材料。
参照图7及图8，局部地研磨绝缘材料210、导电层150a及保护顶盖140a以移除导电层150a的顶盖层150a1，直到暴露出导电柱130的顶表面为止，以形成集成电路组件100a’及绝缘包封体210’，其中绝缘包封体210’包封集成电路组件100a’及覆盖集成电路组件100a’的侧壁的电磁干扰屏蔽层150a2。换句话说，在执行上述研磨工艺之后，会形成剩余下来的电磁干扰屏蔽层150a2。在一些实施例中，通过机械研磨工艺及/或化学机械抛光(chemicalmechanical polishing，CMP)工艺来研磨绝缘材料210。在绝缘材料210的研磨工艺期间，研磨部分的保护顶盖140a、导电顶盖CAP及部分的导电柱130，直到暴露出导电柱130的顶表面为止。在执行绝缘材料210的研磨工艺之后，将形成经研磨的保护顶盖140a’。在一些实施例中，在绝缘材料210的研磨工艺期间，部分的导电穿孔TIV会一并被研磨。
如图8中所示，集成电路组件100a’包括有源表面A、连接到有源表面A的多个侧壁SW及从有源表面A突出的多个导电柱130。电磁干扰屏蔽层150a2为电接地，且电磁干扰屏蔽层150a2覆盖集成电路组件100a’的侧壁SW。绝缘包封体210’包封集成电路组件100a’及电磁干扰屏蔽层150a2。此外，导电柱130能够被绝缘包封体210’暴露出。在一些实施例中，集成电路组件100a’与绝缘包封体210'被电磁干扰屏蔽层150a2间隔开，且集成电路组件100a’被电磁干扰屏蔽层150a2环绕。
如图8中所示，绝缘包封体210’被导电穿孔TIV穿透。换句话说，集成电路组件100a’及导电穿孔TIV嵌于绝缘包封体210’中。应注意，导电穿孔TIV的顶表面、绝缘包封体210’的第一表面S1(即，顶表面)及导电柱130的顶表面与保护顶盖140a’的顶表面实质上共面。
参照图9，在形成集成电路组件100a’、电磁干扰屏蔽层150a2、绝缘包封体210’及保护顶盖140a’之后，在导电穿孔TIV的顶表面、绝缘包封体210’的第一表面S1(即，顶表面)、导电柱130的顶表面及保护顶盖140a’的顶表面上形成电连接到集成电路组件100a’的导电柱130的第一重布线路结构220。由于第一重布线路结构220被制作在集成电路组件100a’及绝缘包封体210’之上，因此第一重布线路结构220(即，第一重布线路结构)即为所谓的前侧重布线路结构(front side redistribution circuit structure)。
如图9中所示，第一重布线路结构220包括交替堆叠的多个介电层222及多个重布线导电层224。在一些实施例中，导电柱130的顶表面及导电穿孔TIV的顶表面接触第一重布线路结构220。导电柱130的顶表面及导电穿孔TIV的顶表面被最底部介电层222局部地覆盖。
参照图9，在形成第一重布线路结构220之后，接着在第一重布线路结构220的最顶部重布线导电层224上形成多个垫230。垫230包括用于球安装(ball mount)的多个球下金属(under-ball metallurgy，UBM)图案230a及用于安装无源组件的多个连接垫230b。将垫230电连接到第一重布线路结构220的最顶部重布线导电层224。换句话说，通过第一重布线路结构220将垫230电连接到集成电路组件100a’的导电柱130以及导电穿孔TIV。应注意，球下金属图案230a及连接垫230b的数目在本发明中并无限制。
参照图10，在形成球下金属图案230a及连接垫230b之后，在球下金属图案230a上放置多个导电球240，且在连接垫230b上安装多个无源组件250。在一些实施例中，可通过植球工艺(ball placement process)在球下金属图案230a上放置导电球240，且可通过焊接工艺(soldering process)或回焊工艺(reflowing process)在连接垫230b上安装无源组件250。在一些实施例中，举例来说，导电球240的高度大于无源组件250的高度。
参照图10及图11，在垫230上安装导电球240及无源组件250之后，从剥离层DB剥离形成在绝缘包封体210’的底表面上的介电层DI，以使介电层DI从载体C分离。在一些实施例中，可通过紫外(UV)激光照射剥离层DB(例如，所述光-热转换释放层(LTHC releaselayer))，使得介电层DI从载体C脱落(peel)。
如图12中所示，接着将介电层DI图案化，以在介电层DI中形成多个接触开口O2进而暴露出导电穿孔TIV的底表面。接触开口O2的数目及位置对应于导电穿孔TIV的数目。在一些实施例中，通过激光钻孔工艺(laser drilling process)或其他适合的图案化工艺形成介电层DI中的接触开口O2。在一些替代性实施例中，可从绝缘包封体210’的底表面整体地移除介电层DI，以全面性地暴露出导电穿孔TIV的底表面。
参照图13，在介电层DI中形成接触开口O2之后，在导电穿孔TIV的被接触开口O2暴露出的底表面上放置多个导电球260。并且，例如对导电球260进行回焊以使导电球260与导电穿孔TIV的底表面结合。如图13中所示，在形成导电球240及导电球260之后，具有双侧端子设计(即，导电球240及260)的集成电路组件100a’的集成扇出型封装便初步制作完成。
图14是说明根据本发明一些实施例的叠层封装(POP)结构的剖视图。参照图14，接着提供半导体装置300。半导体装置300为例如存储器装置或其他适合的半导体管芯。半导体装置300堆叠在图13中所示的集成扇出型封装之上并通过导电球260电连接到所述集成扇出型封装，以制作出叠层封装(POP)结构。
图15至图25示意性地说明制作根据本发明一些替代性实施例的集成扇出型封装的工艺流程；且图26是说明根据本发明一些替代性实施例的叠层封装(POP)结构的剖视图。
参照图15，提供其上形成有剥离层DB及介电层DI的载体C，其中剥离层DB处于载体C与介电层DI之间。在一些实施例中，举例来说，载体C是玻璃衬底，剥离层DB是形成在所述玻璃衬底上的光-热转换(LTHC)释放层，且介电层DI是形成在剥离层DB上的聚苯并恶唑(PBO)层。在替代性实施例中，剥离层DB可为粘性通过光固化工艺而被降低的光固化释放膜或粘性通过热固化工艺而被降低的热固化释放膜，且介电层DI可由其他感光性的或非感光性的介电材料制成。在提供其上形成有剥离层DB及介电层DI的载体C之后，在载体C上形成第二重布线路结构270(即，背侧重布线路结构)。第二重布线路结构270包括至少一个介电层272及至少一个重布线导电层274。所述至少一个介电层272覆盖所述至少一个重布线导电层274，且所述至少一个介电层272包括用于暴露出位于底下的重布线导电层274的多个开口O3。
参照图16，在载体C上形成第二重布线路结构270之后，在第二重布线路结构270上形成晶种层S。在一些实施例中，晶种层S可为在第二重布线路结构270上形成的溅镀Ti/Cu晶种层。如图16中所示，在晶种层S上形成包括多个开口O4的图案化光刻胶PR。图案化光刻胶PR的开口O4的位置及数目对应于介电层272的开口O3。此外，晶种层S被图案化光刻胶PR中的开口O4局部地暴露出。
参照图17，将具有第二重布线路结构270的载体C、晶种层S及位于晶种层S上的图案化光刻胶PR浸入至镀覆槽(plating bath)中，使得在开口O4中形成多个导电穿孔TIV。导电穿孔TIV局部地覆盖晶种层S。
参照图18，在通过镀覆将导电穿孔TIV形成至所暴露出的晶种层S上之后，移除图案化光刻胶PR。此后，利用导电穿孔TIV作为硬掩模将晶种层S图案化。在一些实施例中，导电穿孔TIV可为铜杆或其他适合的金属杆。
参照图19至图25，除了在形成绝缘材料210及绝缘包封体210’之前形成第二重布线路结构270、在与第一表面S1(示出在图20中)相对的第二表面S2(即，底表面)上设置第二重布线路结构270以及通过导电穿孔TIV将第一重布线路结构220电连接到第二重布线路结构270外，用于制作集成扇出型封装的工艺流程与图7至图13中所示的工艺流程相似。换句话说，集成电路组件100a’经由第一重布线路结构220及导电穿孔TIV而电连接到第二重布线路结构270。因此，此处省略了对图19至图25的详细说明。
参照图26，除在第二重布线路结构270上设置半导体装置300外，用于制作叠层封装(POP)结构的工艺流程与图14中所示的工艺流程相似，其中半导体装置300经由第二重布线路结构270、导电穿孔TIV及第一重布线路结构220而电连接到集成电路组件100a’。
图27至图33示意性地说明用于制作根据本发明又一些替代性实施例的集成扇出型封装的工艺流程。
参照图27，提供其上形成有剥离层DB及介电层DI的载体C，其中剥离层DB处于载体C与介电层DI之间。在一些实施例中，举例来说，载体C是玻璃衬底，剥离层DB是形成在所述玻璃衬底上的光-热转换(LTHC)释放层，且介电层DI是形成在剥离层DB上的聚苯并恶唑(PBO)层。在替代性实施例中，剥离层DB可为粘性通过光固化工艺而被降低的光固化释放膜或粘性通过热固化工艺而被降低的热固化释放膜，且介电层DI可由其他感光性的或非感光性的介电材料制成。在提供其上形成有剥离层DB及介电层DI的载体C之后，在介电层DI上形成多个导电穿孔TIV。在一些实施例中，所述多个导电穿孔TIV是通过光刻胶涂布、光刻、镀覆及光刻胶剥除工艺形成。举例来说，导电穿孔TIV包括铜杆或其他适合的金属杆。
如图27中所述，在由载体C所承载的介电层DI上提供被导电层150a覆盖的至少一个第一半导体管芯100a及至少一个第二半导体管芯100b。在一些实施例中，从托盘TR(示出在图5中)上拾取被导电层150a覆盖的第一半导体管芯100a。被导电层150a覆盖的第一半导体管芯100a可具有与图7中所示半导体管芯100a的结构相同的结构。不被导电层150a覆盖的第二半导体管芯100b可具有与图4中所示半导体管芯100a的结构相同的结构。在一些实施例中，可从同一晶片W(示出在图4中)切割出被导电层150a覆盖的第一半导体管芯100a及不被导电层150a覆盖的第二半导体管芯100b。在一些替代性实施例中，可从不同的晶片切割出被导电层150a覆盖的第一半导体管芯100a及不被导电层150a覆盖的第二半导体管芯100b。
第一半导体管芯100a包括第一半导体衬底110a、设置在第一半导体衬底110a上的第一内连线结构120a、多个第一导电柱130a及第一保护顶盖140a。第一保护顶盖140a包封第一导电柱130a且覆盖第一内连线结构120a。第二半导体管芯100b包括第二半导体衬底110b、设置在第二半导体衬底110b上的第二内连线结构120b、多个第二导电柱130b及第二保护顶盖140b。第二保护顶盖140b包封第二导电柱130b且覆盖第二内连线结构120b。
参照图27，在形成导电穿孔TIV之后，拾取并且在介电层DI上放置第一半导体管芯100a及第二半导体管芯100b。然而，本发明并不仅限于此。在一些替代性实施例中，在形成导电穿孔TIV之前，拾取并且在介电层DI上放置第一半导体管芯100a及第二半导体管芯100b。
如图27中所示，在介电层DI上形成绝缘材料210，以覆盖第一半导体管芯100a、第二半导体管芯100b、导电层150a及导电穿孔TIV。在一些实施例中，绝缘材料210是通过包覆模制工艺(例如，压缩模塑工艺)形成的模制化合物。导电柱130、第一半导体管芯100a的第一保护顶盖140a及第二半导体管芯100b的第二保护顶盖140b不被绝缘材料210显露出且被绝缘材料210保护。在一些实施例中，绝缘材料210的材料包括环氧树脂或其他适合的介电材料。
参照图27及图28，局部地研磨绝缘材料210、导电层150a、第一保护顶盖140a、第二保护顶盖140b以移除导电层150a的顶盖层150a1，直到暴露出第一导电柱130a的顶表面及第二导电柱130b的顶表面为止，以形成第一集成电路组件100a’、第二集成电路组件100b’及绝缘包封体210’，其中绝缘包封体210’包封第一集成电路组件100a’、第二集成电路组件100b’及覆盖第一集成电路组件100a’的侧壁的电磁干扰屏蔽层150a2。换句话说，在执行上述研磨工艺之后，会形成剩余下来的电磁干扰屏蔽层150a2。在一些实施例中，通过机械研磨工艺及/或化学机械抛光(CMP)工艺来研磨绝缘材料210。在绝缘材料210的研磨工艺期间，研磨部分的第一保护顶盖140a、部分的第二保护顶盖140b、导电顶盖CAP、部分的第一导电柱130a及部分的第二导电柱130b会一并被研磨，直到暴露出第一导电柱130a的顶表面及第二导电柱130b的顶表面为止。在执行绝缘材料210的研磨工艺之后，将形成第一保护顶盖140a’及第二保护顶盖140b’。在一些实施例中，在绝缘材料210的研磨工艺期间，部分的导电穿孔TIV会一并被研磨。
如图28中所示，第一集成电路组件100a’包括有源表面A、连接到有源表面A的多个侧壁SW及从有源表面A突出的多个导电柱130。电磁干扰屏蔽层150a2为电接地且覆盖第一集成电路组件100a’的侧壁SW。第二集成电路组件100b’具有与第一集成电路组件100a’的结构相似的结构。绝缘包封体210’在侧向上包封第一集成电路组件100a’、第二集成电路组件100b’及电磁干扰屏蔽层150a2。此外，第一导电柱130a及第二导电柱130b能够被绝缘包封体210’暴露出。在一些实施例中，第一集成电路组件100a’与绝缘包封体210’被电磁干扰屏蔽层150a2间隔开，且第一集成电路组件100a’被电磁干扰屏蔽层150a2环绕。此外，第二集成电路组件100b’接触绝缘包封体210’。第二集成电路组件100b’的侧壁不接触电磁干扰屏蔽层150a2。
如图28中所示，绝缘包封体210’被导电穿孔TIV穿透。换句话说，第一集成电路组件100a’、第二集成电路组件100b’及导电穿孔TIV嵌于绝缘包封体210’中。
如图28中所示，由于电磁干扰屏蔽层150a2是在芯片层级就已形成，因此在封装体制作完成之前，第一集成电路组件100a’与第二集成电路组件100b’之间的电磁干扰可被电磁干扰屏蔽层150a2屏蔽。
参照图29，在导电穿孔TIV的顶表面、绝缘包封体210’的第一表面S1(即，顶表面)、第一导电柱130a、第二导电柱130b、第一保护顶盖140a’及第二保护顶盖140b’上形成与第一集成电路组件100a’的第一导电柱130a及第二集成电路组件100b’的第二导电柱130b电连接的第一重布线路结构220。如图29中所示，第一重布线路结构220包括交替堆叠的多个介电层222及多个重布线导电层224。
参照图29，在形成第一重布线路结构220之后，接着在第一重布线路结构220的最顶部重布线导电层224上形成多个垫230。垫230包括用于球安装的多个球下金属(UBM)图案230a及用于安装无源组件的多个连接垫230b。将垫230电连接到第一重布线路结构220的最顶部重布线导电层224。
参照图30，在形成球下金属图案230a及连接垫230b之后，在球下金属图案230a上放置多个导电球240，并且在连接垫230b上安装多个无源组件250。在一些实施例中，可通过植球工艺在球下金属图案230a上放置导电球240，且可通过焊接工艺或回焊工艺在连接垫230b上安装无源组件250。在一些实施例中，举例来说，导电球240的高度大于无源组件250的高度。
参照图30及图31，在垫230上安装导电球240及无源组件250之后，从剥离层DB剥离形成在绝缘包封体210’的底表面上的介电层DI，以使介电层DI从载体C分离。在一些实施例中，可通过UV激光照射剥离层DB(例如，所述光-热转换释放层)，使得介电层DI从载体C脱落。
如图32中所示，接着将介电层DI图案化，以在介电层DI中形成多个接触开口O2进而暴露出导电穿孔TIV的底表面。接触开口O2的数目及位置对应于导电穿孔TIV的数目。在一些实施例中，通过激光钻孔工艺或其他适合的图案化工艺形成介电层DI的接触开口O2。在一些替代性实施例中，可从绝缘包封体210’的底表面整体地移除介电层DI，以全面性地暴露出导电穿孔TIV的底表面。
参照图33，在介电层DI中形成接触开口O2之后，在导电穿孔TIV的被接触开口O2暴露出的底表面上放置多个导电球260。并且，例如对导电球260进行回焊以使导电球260与导电穿孔TIV的底表面结合。如图33中所示，在形成导电球240及导电球260之后，第一集成电路组件100a’与第二集成电路组件100b’的集成扇出型封装便初步制作完成。
应注意，可通过图15至图25中所示工艺来封装第一集成电路组件100a’与第二集成电路组件100b’。
根据本发明的一些实施例，提供一种集成电路封装，所述集成电路封装包括至少一个集成电路组件、至少一个电磁干扰屏蔽层及绝缘包封体。所述至少一个集成电路组件包括有源表面、连接到所述有源表面的多个侧壁、以及从所述有源表面突出的多个导电柱。所述至少一个电磁干扰屏蔽层覆盖所述至少一个集成电路组件的所述侧壁，且所述至少一个电磁干扰屏蔽层为电接地。所述绝缘包封体包封所述至少一个集成电路组件及所述至少一个电磁干扰屏蔽层，且所述至少一个集成电路组件的所述导电柱能够被所述绝缘包封体暴露出。
根据本发明的一些实施例，所述至少一个集成电路组件进一步包括保护顶盖，所述保护顶盖覆盖所述有源表面且包封所述导电柱，所述导电柱的顶表面能够被所述保护顶盖暴露出且与所述保护顶盖的顶表面实质上共面，且所述至少一个电磁干扰屏蔽层进一步覆盖所述保护顶盖的侧壁。
根据本发明的一些实施例，所述至少一个集成电路组件与所述至少一个绝缘包封体被所述电磁干扰屏蔽层间隔开且所述至少一个集成电路组件被所述至少一个电磁干扰屏蔽层环绕。
根据本发明的一些实施例，集成电路封装进一步包括第一重布线路结构，所述第一重布线路结构设置在所述导电柱能够被所述绝缘包封体暴露出的所述顶表面上及所述绝缘包封体的第一表面上，其中所述第一重布线路结构电连接到所述至少一个集成电路组件的所述导电柱。
根据本发明的一些实施例，集成电路封装进一步包括：多个导电穿孔，其中所述导电穿孔穿透过所述绝缘包封体且电连接到所述第一重布线路结构。
根据本发明的一些实施例，集成电路封装进一步包括：第二重布线路结构，设置在所述绝缘包封体的第二表面上，其中所述第二表面与所述第一表面相对，且所述第二重布线路结构经由所述导电穿孔电连接到所述第一重布线路结构。
根据本发明的一些实施例，集成电路封装进一步包括：半导体装置，设置在所述第二重布线路结构上，其中所述半导体装置经由所述第二重布线路结构、所述导电穿孔及所述第一重布线路结构电连接到所述至少一个集成电路组件。
根据本发明的一些实施例，所述至少一个集成电路组件包括：第一集成电路组件，所述第一集成电路组件的侧壁被所述至少一个电磁干扰屏蔽层覆盖；以及第二集成电路组件，所述第二集成电路组件的侧壁不接触所述至少一个电磁干扰屏蔽层。
根据本发明的一些实施例，所述第一集成电路组件与所述绝缘包封体被所述至少一个电磁干扰屏蔽层间隔开，且所述第一集成电路组件被所述至少一个电磁干扰屏蔽层环绕。
根据本发明的一些实施例，所述第一集成电路组件与所述绝缘包封体被所述至少一个电磁干扰屏蔽层间隔开且所述第二集成电路组件接触所述绝缘包封体。
根据本发明的替代性实施例，提供一种制作集成电路封装的方法。所述方法包括：提供晶片，所述晶片包括形成在所述晶片上的多个导电柱；在所述晶片上形成保护材料层以覆盖所述导电柱；执行晶片切割工艺，以形成多个半导体管芯，其中所述半导体管芯中的每一者包括所述导电柱的部分及覆盖所述导电柱的所述部分的保护顶盖；形成电磁干扰屏蔽层以覆盖所述半导体管芯中的至少一个半导体管芯的侧壁；以及使用绝缘材料在侧向上包封所述半导体管芯中的所述至少一个半导体管芯及所述电磁干扰屏蔽层。
根据本发明的一些实施例，形成所述电磁干扰屏蔽层以覆盖所述半导体管芯的所述侧壁包括：形成导电层，所述导电层包括所述电磁干扰屏蔽层及连接到所述电磁干扰屏蔽层的顶盖层，其中所述顶盖层覆盖所述半导体管芯中的所述至少一个半导体管芯的顶表面且所述电磁干扰屏蔽层覆盖所述至少一个半导体管芯的所述侧壁；以及局部地研磨所述绝缘材料、所述导电层及所述保护顶盖以移除所述顶盖层，直到暴露出所述导电柱为止，以形成集成电路组件及绝缘包封体，其中所述绝缘包封体包封所述集成电路组件及覆盖所述集成电路组件的侧壁的所述电磁干扰屏蔽层。
根据本发明的一些实施例，前述的方法进一步包括：在所述绝缘包封体的第一表面及被所述绝缘包封体暴露出的所述导电柱上形成第一重布线路结构，其中所述第一重布线路结构电连接到所述集成电路组件的所述导电柱。
根据本发明的一些实施例，前述的方法进一步包括：形成穿透过所述绝缘包封体的多个导电穿孔。
根据本发明的一些实施例，前述的方法进一步包括：在载体上提供所述半导体管芯中的所述至少一个半导体管芯之前，在所述载体上形成第二重布线路结构，其中所述第二重布线路结构设置在所述绝缘包封体的第二表面上，所述第二表面与所述第一表面相对，且所述第二重布线路结构经由所述导电穿孔电连接到所述第一重布线路结构。
根据本发明的又一些替代性实施例，提供一种制作集成电路封装的方法。所述方法包括：提供晶片，所述晶片包括形成在所述晶片上的多个第一导电柱；在所述晶片上形成第一保护材料层以覆盖所述第一导电柱；执行晶片切割工艺，以形成多个第一半导体管芯，其中所述第一半导体管芯中的每一者包括所述第一导电柱的部分及覆盖所述第一导电柱的所述部分的第一保护顶盖；形成电磁干扰屏蔽层以覆盖所述第一半导体管芯中的至少一个第一半导体管芯的侧壁；在载体上提供第二半导体管芯及所述第一半导体管芯中的所述至少一个第一半导体管芯，其中所述第二半导体管芯包括多个第二导电柱及覆盖所述第二导电柱的第二保护顶盖；以及使用绝缘材料在侧向上包封所述电磁干扰屏蔽层、所述第一半导体管芯中的所述至少一个第一半导体管芯及所述第二半导体管芯。
根据本发明的一些实施例，形成所述电磁干扰屏蔽层以覆盖所述第一半导体管芯的所述侧壁包括：形成导电层，所述导电层包括所述电磁干扰屏蔽层及连接到所述电磁干扰屏蔽层的顶盖层，其中所述顶盖层覆盖所述第一半导体管芯中的所述至少一个第一半导体管芯的顶表面且所述电磁干扰屏蔽层覆盖所述第一半导体管芯中的所述至少一个第一半导体管芯的所述侧壁；以及局部地研磨所述绝缘材料、所述导电层、所述第一保护顶盖及所述第二保护顶盖以移除所述导电层的所述顶盖层，直到暴露出所述第一导电柱及所述第二导电柱为止，以形成至少一个第一集成电路组件、第二集成电路组件及绝缘包封体，其中所述电磁干扰屏蔽层覆盖所述至少一个第一集成电路组件的侧壁，且所述绝缘包封体包封所述至少一个第一集成电路组件、所述第二集成电路组件及所述电磁干扰屏蔽层。
根据本发明的一些实施例，前述的方法进一步包括：在所述绝缘包封体的第一表面及被所述绝缘包封体暴露出的所述第一导电柱及所述第二导电柱上形成第一重布线路结构，其中所述第一重布线路结构电连接到所述至少一个第一集成电路组件的所述第一导电柱及所述第二集成电路组件的所述第二导电柱。
根据本发明的一些实施例，前述的方法进一步包括：形成穿透过所述绝缘包封体的多个导电穿孔。
根据本发明的一些实施例，前述的方法进一步包括：在所述载体上提供所述第二半导体管芯及所述第一半导体管芯中的所述至少一个第一半导体管芯之前，在所述载体上形成第二重布线路结构，其中所述第二表面与所述第一表面相对，且所述第二重布线路结构经由所述导电穿孔电连接到所述第一重布线路结构。
以上概述了若干实施例的特征，以使所属领域中的技术人员可更好地理解本发明的各个方面。所属领域中的技术人员应理解，其可容易地使用本发明作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的及/或实现与本文中所介绍的实施例相同的优点。所属领域中的技术人员还应认识到，这些等效构造并不背离本发明的精神及范围，而且他们可在不背离本发明的精神及范围的条件下对其作出各种改变、代替及变更。

Claims (1)

1.一种集成电路封装，其特征在于，包括：
至少一个集成电路组件，所述至少一个集成电路组件包括有源表面、连接到所述有源表面的多个侧壁、以及从所述有源表面突出的多个导电柱；
至少一个电磁干扰屏蔽层，覆盖所述至少一个集成电路组件的所述侧壁，所述至少一个电磁干扰屏蔽层为电接地；以及
绝缘包封体，包封所述至少一个集成电路组件及所述至少一个电磁干扰屏蔽层，且所述至少一个集成电路组件的所述导电柱能够被所述绝缘包封体暴露出。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10804115B2 (en) * 2017-08-03 2020-10-13 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10741498B2 (en) * 2018-07-12 2020-08-11 Samsung Electronics Co., Ltd. Semiconductor package
US10825781B2 (en) * 2018-08-01 2020-11-03 Nxp B.V. Semiconductor device with conductive film shielding
GB2584106B (en) * 2019-05-21 2024-03-27 Pragmatic Printing Ltd Flexible electronic structure
US11127645B2 (en) * 2019-06-19 2021-09-21 Nxp Usa, Inc. Grounding lids in integrated circuit devices
USD920265S1 (en) * 2019-09-29 2021-05-25 China Chippacking Technology Co., Ltd. Integrated circuit package
USD920266S1 (en) * 2019-09-29 2021-05-25 China Chippacking Technology Co., Ltd. Integrated circuit package
CN114068493A (zh) * 2020-07-31 2022-02-18 华为技术有限公司 一种封装模组及其封装方法、电子设备
US11756896B2 (en) 2020-12-03 2023-09-12 Advanced Semiconductor Engineering, Inc. Semiconductor package structure including shielding layer contacting conductive contact

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8299595B2 (en) * 2010-03-18 2012-10-30 Stats Chippac Ltd. Integrated circuit package system with package stacking and method of manufacture thereof
US8258012B2 (en) * 2010-05-14 2012-09-04 Stats Chippac, Ltd. Semiconductor device and method of forming discontinuous ESD protection layers between semiconductor die
US9048233B2 (en) 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8797057B2 (en) 2011-02-11 2014-08-05 Taiwan Semiconductor Manufacturing Company, Ltd. Testing of semiconductor chips with microbumps
US8829676B2 (en) * 2011-06-28 2014-09-09 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure for wafer level package
US9000584B2 (en) 2011-12-28 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Packaged semiconductor device with a molding compound and a method of forming the same
US9111949B2 (en) 2012-04-09 2015-08-18 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus of wafer level package for heterogeneous integration technology
US20130307153A1 (en) 2012-05-18 2013-11-21 International Business Machines Corporation Interconnect with titanium-oxide diffusion barrier
US9711465B2 (en) * 2012-05-29 2017-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Antenna cavity structure for integrated patch antenna in integrated fan-out packaging
US9263511B2 (en) 2013-02-11 2016-02-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package with metal-insulator-metal capacitor and method of manufacturing the same
US9048222B2 (en) 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
US9368460B2 (en) 2013-03-15 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out interconnect structure and method for forming same
US9281254B2 (en) 2014-02-13 2016-03-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming integrated circuit package
US9496189B2 (en) 2014-06-13 2016-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor devices and methods of forming same

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