CN100454533C - 用于电子元件封装的emi屏蔽 - Google Patents

用于电子元件封装的emi屏蔽 Download PDF

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Publication number
CN100454533C
CN100454533C CNB2004800102048A CN200480010204A CN100454533C CN 100454533 C CN100454533 C CN 100454533C CN B2004800102048 A CNB2004800102048 A CN B2004800102048A CN 200480010204 A CN200480010204 A CN 200480010204A CN 100454533 C CN100454533 C CN 100454533C
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conductive layer
coated
chip
substrate
electronic package
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CN1774804A (zh
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罗基·R·阿诺德
约翰·C·扎尔加尼斯
法布里齐奥·蒙陶蒂
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Wavezero Inc
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Wavezero Inc
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Abstract

本发明提供用于屏蔽电子元件封装的方法和装置。在一个实施例中，EMI屏蔽(42)一体地形成在邻近芯片(12)的封装内并接地。EMI屏蔽(42)可以是金属化的成形的聚合物层(34)并且可以完全设置在封装内或者它可以延伸到封装的外面。

Description

用于电子元件封装的EMI屏蔽
相关申请的交叉引用
本申请要求2003年4月15提交的临时美国专利申请60/462,902的利益，其全部内容结合于此供参考。
本申请还涉及与此一道提交的名称为“用于印刷电路板的电磁干扰屏蔽”、同时待审并且共有的美国专利申请______(代理律师案卷号020843-002810US)，其全部内容也结合于此供参考。
技术领域
本发明通常涉及屏蔽的半导体电子元件封装和印刷电路板，更具体地，本发明提供一体地形成在半导体电子元件封装内的EMI屏蔽。
背景技术
根据微处理器的速度，半导体电子元件辐射大体在50MHz到3GHz的范围内的电磁辐射。正如能够理解的，随着高速微处理器设计的进步和高速联网及切换的快速增长的能力，电磁辐射常常在该范围以上。电子辐射的发射度的问题对于电子设备的设计师们不是新问题。实际上，为了减少电磁干扰(EMI)和射频干扰(RFI)已经做出了相当大的努力，并且每个县都有管理机构(例如美国的FCC)，管理无论电子设备发射的辐射或被其接受辐射(也称之为敏感度)没有通过EMI和RFI严格的要求的电子产品的销售和交易。
半导体器件封装或集成电路芯片载体在各种电子用途中得到应用。集成电路或半导体电子元件(这里统称为“电子元件封装”)通常通过在电子元件四周用诸如环氧树脂材料、传递模塑、热固或热塑树脂的敷形涂层进行封装与外部环境隔离而进行保护。这种封装对电子元件提供保护，使其不受尘土、湿汽和其他环境因素的影响，而这些因素能够对电子元件的电路造成毁坏或无可挽救的损坏。遗憾的是，与半导体电子元件的传统封装相关的一个问题是这种热塑封装对诸如RFI和EMI这样的电磁辐射不提供屏蔽。
说到印刷电路板或“元件级”的EMI屏蔽，一些常规的方案是通过如下的手段使EMI屏蔽的导电表面与表面接地迹线接触：(1)直接使金属罩与接地迹线(ground trace)接触，(2)直接使屏蔽表面金属化并将它放置成与接地迹线接触，或者(3)使“外侧”表面(从被屏蔽元件的视点)金属化并且然后用将该表面接地迹线连接于该金属化外侧表面的一些连接方法。这些方案用来保护半导体电子元件不受外部RFI和EMI信号的影响，并防止在该半导体电子封装内产生的RFI或EMI信号逃逸。
根据过去使用的焊接的金属罩，表面接地迹线的目的是提供该金属罩与印刷电路板之间的接触点，其能够经受标准的表面安装技术(SMT)焊接回流工艺，这种工艺在该金属罩屏蔽和印刷电路板之间最终提供紧密的永久的连接。
结果得到的屏蔽和元件的组件为许多用途提供充分的屏蔽。但是，随着芯片频率的增加(例如，高于3GHz)和数据传输速率的增加，某些无定的EMI辐射的产生变得非常容易，并且对附近的电路和元件更加有害。实际上，由于芯片密度的增加，(一个芯片相对于另一个芯片的)抗干扰性的问题变得愈加重要。因此，一般来说，常规的方案对于抗干扰性的目的逐渐变得不相适应，实际上，辐射的发射也可能成为愈加突出的问题。而且，对于微波设备而言，特别是那些谐波频率在10GHz以上的设备，辐射的发射将会成为非常关心的问题。
在实际的所有情况下，现有的方案费用高并且增加制造电子设备如移动电话、个人数字助理、膝上型计算机、机顶盒、电缆调制解调器、包括开关、桥接器和跨接器的联网设备的成本。而且，由于印刷电路板上的电子元件的密度增加，在印刷电路板上找到安装EMI/RFI屏蔽的空间变得十分困难。
因此，仍然需要一种方法，对印刷电路板上的集成电路封装提供不引人注目的EMI/RFI屏蔽。
发明内容
本发明提供一种屏蔽的封装、屏蔽的电子元件和印刷电路板，以及制造方法。
一方面，本发明提供屏蔽的电子元件封装。该电子元件封装包括芯片和包括多个迹线的基底。多个引线(例如布线、焊球等)将该芯片的有源表面电连接于该基底中的多个迹线。外部焊球触点连接于该基底中的多个迹线。该焊球触点从该基底的表面延伸并且构造成连接在印刷电路板上的导电引线上。导电地涂敷的聚合物屏蔽形成围绕该芯片和该多个引线的至少一部分的凹腔。该导电地涂敷的聚合物屏敝可电连接于接地迹线。绝缘的敷形涂层设置在导电地涂敷的聚合物屏蔽上，以便封装该芯片和多个引线。该绝缘的敷形涂层使外部焊球触点暴露在外。
在一个实施例中，接地迹线设置在电子元的基底上。这种接地迹线可以与一些外部焊球触点电连通。然后被接触的焊球触点可以电接触在印刷电路板中/上的接地的元件。
在另一个实施例中，该接地迹线可以直接设置在印刷电路板上。在这样的实施例中，该导电地涂敷的聚合物屏蔽的端部可以延伸超过敷形涂层和基底的外表面，并且可以构造成接触印刷电路板上的表面接地迹线。
本发明的导电地涂敷的聚合物屏蔽可以采取各种不同的形式。在一个实施例中，导电地涂敷的聚合物屏蔽包括顶表面和从该顶表面以一定角度延伸的多个侧壁。凸缘在基本平行于该基底第一表面的平面中以一定角度从侧壁延伸。
导电地涂敷的聚合物屏蔽通常包括至少一个热塑树脂层和在该每个树脂层的至少一个表面上的至少一个金属层。在一种结构中，该树脂层包括高温热成形薄膜并且具有一个设置在内表面上面向芯片和基底的金属层。金属层可以具有任何厚度，但通常在约1微米和约50微米之间，优选小于约3微米。
虽然金属层可以用任何常规的方法施加于树脂层，一种优选的方法是通过真空金属化。申请人业已发现真空金属化在整个成形的树脂层上提供相当均匀厚度的金属。
选择地，该导电地涂敷的聚合物屏蔽包括多个小孔。这些小孔通常设置成使多个引线能够电连接于在基底中的多个迹线。
该导电地涂敷的聚合物屏蔽可以用于在敷形涂层和芯片之间形成间隔。这种间隔可以减少在敷形涂层和芯片之间的机械应力和热失配应力。选择地，在邻近芯片的间隔中可以设置填充材料。该填充材料可以具有类似于它所封装的电子芯片的热膨胀系数的热膨胀系数。可选地，填充材料可以具有高于或低于该芯片的热膨胀系数(例如类似于敷形涂层的热膨胀系数)。
在一些实施例中，散热装置或散热器可以设置在间隔中并接触该芯片。该散热装置/散热器用于耗散由芯片产生的热。在一些结构中，小孔或通道可以形成在散热装置/散热器和导电地涂敷的聚合物屏蔽中。这种小孔可以用敷形涂层填充，以便固定该屏蔽和散热器。正如可以理解的，该小孔具有足够小的尺寸，以防止电磁干扰逃逸。
另一方面，本发明提供屏蔽的封装，其包括具有有源表面的芯片和包括多个迹线的基底。多个引线将该芯片的有源表面电连接于该基底中的多个迹线。外部触点连接于该基底中的迹线。该外部触点构造成连接在印刷电路板上的导电引线上。导电地涂敷的聚合物屏蔽形成围绕该芯片的至少一部分的凹腔。该导电地涂敷的聚合物屏蔽可电连接于该基底中的接地迹线。填充材料设置在由该导电地涂敷的聚合物屏蔽形成的凹腔中。敷形涂层设置在导电地涂敷的聚合物屏蔽上，以便封装该芯片和多个引线，其中该绝缘的敷形涂层使外部焊球触点暴露在外。
该导电地涂敷的聚合物屏蔽通常包括热塑树脂层和在该树脂层的至少一个表面上的至少一个金属层。在一种结构中，该聚合物屏蔽包括顶表面和从该顶表面以一定角度延伸的多个侧壁。凸缘在基本平行于该基底第一表面的平面中以一定角度从该侧壁延伸。
在又一方面，本发明提供制造该屏蔽封装的方法。该方法包括提供包括多个引线的基底。芯片的有源表面电连接于该多个引线。导电地涂敷的树脂层连接于该基底，以便该芯片设置在该基底和该导电地涂敷的树脂层之间的凹腔中。该导电地涂敷的树脂层是接地的并且敷形涂层施加在该导电地涂敷的树脂层的至少一部分上，以便封装该芯片和该基底的至少一部分。
该方法还可以包括通过使树脂层成形并且在该成形的树脂层的至少一个表面上淀积至少一个导电层来形成该导电地涂敷的树脂层。在优选的实施例中，该导电层是被真空金属化在该成形的树脂层上的金属层。
选择地，该凹腔可以用填充材料填充。散热装置或散热器可以连接于该芯片，以帮助耗散由芯片产生的热。
在一种结构中，围绕该导电地涂敷的树脂层包括使该导电地涂敷的树脂层的一部分延伸出敷形涂层，并且使该导电地涂敷的树脂层接触印刷电路板上的接地迹线。
本发明还提供印刷电路板。该印刷电路板包括这里所描述的任何屏蔽的电子元件封装，电子元件封装具有一体地形成在该封装内的EMI屏蔽。该印刷电路板包括电连接于封装内的屏蔽的接地元件。
本发明还提供包括本发明印刷电路板的电子器件。该电子器件包括计算机、移动电话、个人数字助理、联网装置和路由器等。
通过参考本说明书的其余部分和附图，进一步理解本发发明的性质和优点将变得很显然。
附图说明
图1是本发明的电子元件封装的剖面图；
图2是本发明的另一种电子元件封装的剖面图；
图3是本发明的又一种电子元件封装的剖面图；
图4是本发明的再一种电子元件封装的剖面图；
图5和图6示出包括一体的第一和第二EMI屏蔽的电子元件封装；
图7和图8示出两种电子元件封装，其设置在印刷电路板上并通过一系列关键地形成的通道接地于接地层；
图9示出本发明的另一种EMI屏蔽方案。
具体实施方式
图1示出本发明的电子元件封装10。封装10包括设置在基底14的芯片焊盘(pad)上的芯片12。芯片12通常用粘接层16连接于芯片焊盘。芯片用诸如布线阵列或焊球阵列的多个导电元件20电连接于基底14上的导电迹线(未示出)。如果该导电元件20是焊球。这样的焊球通常设置在该芯片的下侧21(其可能会是有源面)并且可以用于将芯片12连接于基底14的迹线。在这样的实施例中，通常不需要粘结剂16，但是不导电的粘结剂或其他材料可以用于使导电元件相互绝缘并且为芯片提供机械支撑。
间隔元件插入件22可以设置在芯片12上方并连接于基底14的一部分。敷形涂层24施加在间隔元件22的上面以封装并密封该芯片12和导电元件20，以避免环境污染物，例如水、尘土等。敷形涂层一般是环氧树脂，其通常包括基于乙烯聚合物化学性质的树脂和增强线性聚合作用和环氧树脂的交连作用的反应硬化剂。树脂组织的粘度较低并包含用于改进物理性能的低损耗的填充剂，根据本领域已知的方法很容易制造不收缩、无孔隙和低热膨胀的环氧树脂铸件。
间隔元件插入件22在模制树脂或敷形涂层24与芯片12和导电元件20之间可以形成空气腔或空间26。由于芯片12和导电元件20与敷形涂层间隔开，可以减小所关心的在该芯片和敷形涂层之间的机械应力和热失配应力。选择地，可以在该空气腔26中设置填充材料、散热装置或底层填料(未示出)，该底层材料通常是以环氧树脂为基的材料，这种以环氧树脂为基的材料容易进入亚密耳级间隙中并提供良好的温度稳定性和化学稳定性。该填充材料可以是比敷形涂层24更具柔性(例如具有接近于该芯片的热膨胀系数)，或它可以具有基本类似于敷形图涂层24的柔性。该填充材料可以选择成使得热膨胀系数接近于该芯片12的热膨胀系数，以便减少与芯片12的热膨胀系数的失配。根据在底层填料中使用的与各种添加剂相联的基础聚合物树脂和能够与该树脂组合的插入物，具有各种热膨胀系数的底层填料可以化学地制造以适合大多数的任何应用。
外部引线28的阵列连接于基底14上的迹线/焊盘30并且从封装10中露出并且构造成与印刷电路板(未示出)上的引线的阵列电接触。引线28的阵列可以采取任何形式——例如表面安装引线或插入型引线。例如，在所示的实施例中，该多个引线28包括多个焊盘30，该焊盘包括焊球或焊接凸起32。在另一些实施例中，引线28可以采取具有端部的引线形式，该端部是鸥翼形(L形)或J形。
图2示出本发明的间隔元件插入件的简化截面剖面图。间隔元件可以被形成为一个或多个接纳并屏蔽基底上的芯片的小室的形状。在间隔元件插入件具有用于多个芯片的多个小室的实施例中，每个小室的尺寸和形状通常做成使该多个芯片相互分开并与敷形涂层分开。由此，间隔元件插入件可以采取各种形状、尺寸和形式，以便符合该封装的特定形状和构造。选择地，间隔元件插入件可以包括多个小孔。该小孔可以用于通风、散热或使引线能够通过该插入件伸出。
间隔元件插入件通常包括至少一个聚合物层34，例如能够通过各种塑料处理方法形成为所希望的形状以部分或全部封闭芯片12的热塑树脂层或热固树脂层。在示例性的实施例中，聚合物层34是用热成形技术(例如，真空、压力或机械力)形成其形状的可热成形的塑料。但是，应当理解，该聚合物层34可以用任何常规的或专利的方法成形。聚合物层34可以用任何聚合物构成，包括但不限于，PBT、聚碳酸酯、Ultem
Figure C20048001020400141
、teflon
Figure C20048001020400142
、Kapton、聚吡咯(polypyrroyle)、碳氟化合物、用玻璃或其他物质填充的聚合物、未填充的聚合物等。
在一个优选实施例中，该聚合物层包括热塑树脂。热塑树脂是加热时能够软化或熔融并且在冷却时再变硬的聚合物材料。热塑性材料一般比较刚性或在成形阶段熔化，这将提供各种处理和成形技术，例如真空成形或注塑模制。这使得热塑性材料较好地适合于形成诸如EMI屏蔽的外壳。
在可选的实施例中，热固性材料是当加热或固化时变成永久性刚性的聚合物材料。热固性材料的优点是在加热或固化之前具有液态形式。结果，热固化材料较好地适合用作罩封材料，用于填充孔隙或封装其他实施例，这就是通常为什么热固性材料被选作底层填料或用于封装芯片的原因。热固性材料经常能够经受比热塑性材料高的高温。
如果希望有屏蔽EMI，那么间隔元件插入件22可以包括在该聚合物层34的内表面36和外表面38中的至少一个上的诸如金属层(例如铝、铜等)的至少一个导电层40。作为对金属层的一种替代，导电层40可以包括导电粘结剂，例如填充银的环氧树脂或硅树脂、填充碳的环氧树脂或硅树脂，或导电涂料(填充有导电颗粒的涂料)等。在示例性的实施例中，导电层40是金属层，其厚度足以阻挡EMI的传输，厚度通常在约1微米到约50微米之间，优选小于约3微米，但是如果希望，它可以更多或更少。例如，如果使用导电涂料，该层经常具有约7微米到约10微米之间的厚度，或更厚。在所示的实施例中，第一导电层40设置在聚合物层34的内表面36上。在这里，热塑树脂层34与一个或多个导电层40的结合被称之为“EMI屏蔽”42。
虽然没有示出，但是能够理解，EMI屏蔽42可以具有设置在内表面36和外表面38两者上的导电层。该两个导电层可以包括同样或不同的材料并且可以具有相同的或不同的厚度。另外，如果希望，每个表面36、38可以具有设置在其上的多于一层的材料。这些不同的层可以具有相同的或不同的厚度，并且可以包括相同的或不同的材料。
EMI屏蔽42可以选择地包括一个或多个通风孔(未示出)，以能够通风和散热。正如能够理解的，这种孔通常足够小以便基本防止目标电磁辐射通过该孔传输。
本发明的导电层40通常在聚合物层34成形之后施加于该聚合物层34。如果该导电层40在热塑树脂层34成形之前施加，那么该成形工艺(例如热成形)往往拉伸并消弱该导电层40的一些部分。业已发现这种拉伸和变薄使该导电层40的EMI屏蔽能够变弱并且在有些时候破坏其屏蔽能力。本发明的EMI屏蔽42一般具有足以阻挡EMI通过的相当均匀的导电层厚度。可与本发明一起使用的EMI屏敝42的一些实施例较详细的说明描述在下述美国专利中：共有美国专利5,811,050和2001年2月16日提交的共有美国专利申请09/788,263，2001年9月4日提交的美国专利申请09/947,299，2000年10月10日提交的美国专利申请09/685,969，以及2000年10月6日提交的PCT专利申请00/27610，这些专利的全部内容结合于此供参考。
通常，利用真空金属化将导电层40淀积在聚合物层的一个或多个表面上。真空金属化是一种优选的方法，因为相当均匀的金属层能够施加在成形的树脂层34上以形成EMI屏蔽42。但是应当理解，只要不脱离本发明的范围，也可以使用将导电层形成在聚合物层上的其他方法。例如，代替真空金属化，诸如沉淀随机层(mat)或纤维织物、溅射镀、涂抹、电镀、沉淀涂覆、无电镀、层压导电层等方法均可以用于将金属层淀积在已成形的树脂薄膜层上。
在EMI屏蔽42的所示实施例中，EMI屏蔽包括顶表面44和多个侧壁46，凸缘48从多个侧壁46横向延伸并且在基本上与基底14的顶表面50平行的平面内延伸。在优选实施例中，该顶表面、侧壁和凸缘在至少一个表面上金属化。虽然侧壁46与顶面44以非正交的角度示出，但是，应当理解，该顶表面44、侧壁46和凸缘48相互可以成任何所希望的角度。而且，在一些实施例中，甚至没有顶表面，该EMI屏蔽42可以是形成半球形空间26的形状。
再参考图1，如果金属罩EMI屏蔽(未示出)用来代替导电地涂覆的聚合物EMI屏蔽42，该金属罩可以通过通道53用焊接回流工艺连接于该基底14上的接地引线51。但是由于聚合物层34的熔化温度通常低于该焊料的回流温度，该回流工艺一般不应用于以树脂为基的EMI屏蔽。因此，导电的粘结剂可以用于使EMI屏蔽42的导电层40接地于基底14上的接地引线51。该导电的粘结剂一般包括但不限于，填充银、铜、碳或其他导电颗粒的环氧树脂，或填充银、铜、碳或其他导电颗粒的硅树脂。
虽然没有示出，但是，如果EMI屏蔽42包括凸缘48，则孔可以选择地被选择成设置在凸缘48上，在那里或导电的或不导电的粘结剂或类似的导电材料(甚至焊料)可以设置在该孔上方以便将凸缘48电连接于通道53、基底14上的接地引线51，或在印刷电路板中/上的接地层。当金属层设置在EMI屏蔽42的外表面38上时这种结构是特别有利的，使得导电的粘结剂形成到该EMI屏蔽42的外表面38上的金属层，再到接地迹线的电通路。
图3示出本发明的另一个封装10。所示的实施例是面向下的球栅阵列(BGA)封装。在这个实施例中，EMI屏蔽42通常是金属化的热成形的形式并且至少部分地封装在敷形涂层24中。散热装置或散热板54可以选择地设置在EMI屏蔽42和芯片12之间并且在由EMI屏蔽42形成的小室内。散热板54可以用于耗散在芯片12的正常工作期间所产生的热。虽然芯片12产生的热在许多应用中可以达到超过70℃的温度，但是应当理解，EMI屏蔽42可以用任何数目的聚合物制造，包括但不限于，PBT、聚碳酸酯、Ultem
Figure C20048001020400171
、用玻璃或其他物质填充的聚合物、或适于经受在焊接阶段该封装10经常经受的升高到超过70℃甚至往往高达160℃的温度的未填充的聚合物等。散热板54通常用铜、镍、锡或其组合制造。散热板54应当设置成直接与该电子芯片接触，以便最有效地将热从该芯片传输出。
在所示的实施例中，散热板54和EMI屏蔽42在基底14上用敷形涂层24可以选择地被保持在位，该涂层24进入在散热板54和EMI屏蔽42中的固定孔。在这个实施例中，EMI屏蔽42可以构造成延伸出敷形涂层24和基底14的外表面或周边。EMI屏蔽可以选择地包括现有的转折点58，其允许EMI屏蔽的延伸部分60朝着在封装10下面的折叠结构偏移，以便从EMI屏蔽的视点部分地或全部地封装芯片10。折叠的下部延伸部分60可以通过焊球触点引线32在焊盘30上保持在位。焊球引线32可以设置在类似于填充孔56的延伸部分60的孔62内，以便露出焊盘30。正如可以理解的，焊球32将被露出并且通常不与EMI屏蔽42的金属层电连接。焊球引线32可以由金属(例如，锡及其合金、铅及其合金、银及其合金、镍及其合金，或其组合)构成。可选地，焊球引线32可以包括粘结剂(填充银的环氧树脂和硅树脂、填充铜的环氧树脂和硅树脂等等)或能够在封装10和印刷电路板(PCB，未示出)的焊盘30和该印刷电路板通常包含的电迹线之间保持机械和电结合的其他材料。
在图3所示的实施例中，EMI屏蔽42通过电连接到焊球接地迹线51可以接地于基底上的接地迹线。在另一个实施例中，与其他的焊球32不同，接地迹线焊球51通过制造孔可以与EMI屏蔽的金属层接触，该孔足够小以允许在EMI屏蔽42上的导电层与焊盘30和接地迹线焊球51中的至少一个之间有接触。在另一个实施例中，可以通过散热板54使EMI屏蔽42与基底14上的接地迹线电接触。在这个实施例中，EMI屏蔽42的金属层直接与导电的散热板54接触，而该散热板又可以以选择性地接触基底14上露出的接地迹线的方式构造。
虽然没有示出，但是可以使延伸部分60具有在所有侧面基本上封装芯片12的长度。在这样的实施例中，延伸部分60将围绕封装10的底表面一直延伸并在芯片的下面相互接触。而且，虽然敷形涂层24示作完全封装EMI屏蔽42的顶表面，为了减少该封装10的垂直尺寸，该敷形涂层也可以只覆盖EMI屏蔽的侧面和部分凸缘。在这个实施例中，EMI屏蔽42的顶表面可以形成该封装10的顶表面。
图4示出本发明的封装10的另一个实施例。在图4所示的实施例中，EMI屏蔽42设置在芯片12之上并部分地被敷形涂层24所封装。EMI屏蔽42形成围绕该芯片12的凹腔以便将敷形涂层24与芯片12和多个布线20分开。芯片12用不导电的粘结剂16连接于基底14。焊球凸起32可以连接于基底14的焊盘30，以便为连接于印刷电路板64提供电接触。
虽然没有示出，但是不用布线20和粘结剂16，芯片12可以反转，使得芯片12的有源面邻接基底14并且该有源面可以通过焊球凸起连接于基底14上的迹线。
在图4所示的实施例中，EMI屏蔽42的端部63可以横向延伸超过基底14和敷形涂层24的外周边。EMI屏蔽42的端部63的尺寸和形状可以做成与印刷电路板62上的接地迹线52接触。接地迹线52可以是基本围绕该印刷电路板上的封装10的环形接地迹线，或接地迹线52可以是向下延伸至印刷电路板64中的内部接地平面的触点或通孔。EMI屏蔽42的端部可以采取各种形状。在一个实施例中，该端部是“J”形、鸥翼形(L形)。可选地，端部63可以包括导电的粘结剂或焊球凸起。
图5和图6示出本发明的另一种封装10的实施例。不具有焊球端子32，所示的实施例具有引线支架66，该引线支架66具有从封装10横向离开并向印刷电路板的表面延伸的导电引线。类似于前面的实施例，封装10包括连接于基底14的芯片12的有源面。在图5中，芯片12的有源面通过焊球导电元件20电地并且机械地连接于基底的导电迹线。虽然没有示出，但是不导电的封装填充材料可以设置在相邻的焊球导电元件20之间以防止焊球导电元件之间的电连接并改善芯片12和基底14之间的机械连接。封装填充材料可以是与敷形涂层24相同或不相同的材料。在图6中，芯片12的有源面通过延长的布线导电元件20电连接于基底14的导电迹线并且用粘结剂16机械地连接于基底14。
在该所示的实施例中，有两个设置在封装10中的EMI屏蔽42、42′。类似于图1、图3和图4的实施例，第一EMI屏蔽42围绕芯片12和导电元件20设置在其上，以便包围该该凹腔26中的芯片和导电元件。第一EMI屏蔽42可以如上所述通过通道或其他接地元件接地于接地迹线。通常，EMI屏蔽42的导电涂层40接触基底上的接地通道或接地引出头。在另一个实施例中，指定的布线连接可以从芯片12延伸以在EMI屏蔽42、42′和芯片12之间提供必要的接地接接触。
第二种屏蔽42′可以相对于芯片设置在基底14的相对侧上，并且机械、电地连接于接地元件(例如接地迹线、通道或引出触点)。在这个实施例中，芯片12将既在顶表面又在底表面上被屏蔽。
在图5和图6中，敷形涂层24施加在基底14两个侧面上，以便封装该基底14、芯片12、导电元件20和EMI屏蔽42、42′。选择地，填充材料(例如，散热装置、散热器等)可以设置在邻近芯片的凹腔26中。
图7和图8示出与改进的印刷电路板64结合的电子元件封装10。印刷电路板64包括叠加或印刷在一个或两个表面(未示出)上的导电迹线并且可以包括内部信号层(未示出)、电源平面(未示出)和一个或多个接地平面68。印刷电路板64包括包含导电迹线图形的一层或多层绝缘的有机或无机材料。当封装10(例如电子元件)连接于并且焊接于印刷电路板的表面之一并且来自电子元件的引线与该印刷电路板64的导电迹线接触时，印刷电路板64变成电路。
虽然印刷电路板64可以用单层环氧树脂板构成，但是本发明的大多数印刷电路板包括两个或更多个环氧树脂层，并且通常在两层到十六层之间，或更多。正如能够理解的，如果希望的话，本发明的印刷电路板64可以包括几百层或更多。
印刷电路板64的基片通常包括绝缘的并且基本上非柔性的基片。设置在印刷电路板64的至少一些基片层的表面上的薄导电迹线或布线可以用起初覆盖该印刷电路板64表面的部分铜箔形成。该铜箔可以部分地蚀刻掉，并且保留的铜箔形成薄布线网，该布线网形成导电迹线并且在安装在印刷电路板64的表面上的各个封装10之间提供电连接。正如能够理解的，该导电引线可以用任何可接受的方法形成在印刷电路板的基片表面上。
一些印刷电路板64具有仅仅安装在印刷电路板64的第一表面上的电子元件封装10和安装在第二表面上的导电迹线。双面印刷电路板64在印刷电路板64的第一和第二表面两面具有导电迹线。如果在印刷电路板64的两面具有导电迹线，那么在该两个表面之间需要电桥接件。这种电桥接件可以包括通道。通道70是在该印刷电路板64中用金属或其他导电材料填充或镀上的并通过印刷电路板64的至少一层的孔。虽然在图7和图8中没有示出，当具有多层导电迹线时，印刷电路板64可以包括不是延伸通过印刷电路板所有层的埋入通道或盲通道。
为了增加印刷电路板64上的导电迹线的数量，两个或更多个双面层可以用在这些层之间的绝缘层连接在一起。为了更加清楚地示出本发明的新颖性，附图中仅仅示出单面板，但是应当理解，本发明同样可用于双面印刷电路板。
在多层印刷电路板64中，一层或多层可以专用于接地平面68和电源平面(未示出)。在一些实施例中，可以具有多于一个电源平面和/或接地平面68。多个导电地涂覆或填充的通道70可以选择地形成在印刷电路板64中，使得至少一些通道70从接地层(即接地平面68)延伸到印刷电路板64的第一外表面72。正如能够理解的，不是印刷电路板64中所有的通道70需要延伸到第一外表面72。而且一些通道70可以用于将一个接地层(未示出)互连到诸如接地平面68的另一个接地层。还有，根据印刷电路板的构造，多个通道70可以电连接于不同的接地层。通道70不是与任何导电引线接触，而是在内部接地层70和EMI屏蔽42之间提供电连接。
通常，通道70从印刷电路板64的第一表面72的平面基本垂直延伸到接地层68并且用常规方法形成。通道70可以形成在印刷电路板64的层中以使得该通道的一端延伸到第一表面72，以提供能够电连接于EMI屏蔽42的顶侧表面。至少该通道70的一部分可以与接地层68接触。因此，当EMI屏蔽42与第一外表面68上的通道70导电接触时，该EMI屏蔽42将被接地。
通道70优选以构图方式形成在印刷电路板64中，以减少通过通道网逃逸出的电磁辐射的量。该通道网通常设置在少至4个多至数百个通道之间，这些通道围绕每个电子元件封装10从第一表面72向下延伸到接地层68。通常，该通道以对应于该屏蔽的周边的形状的形状形成，以便提供沿着延伸到封装10的外面的EMI屏蔽42的周边的通道屏蔽接地接触。因此，通道网和接地平面的形状和位置将取决于相应的EMI屏蔽42的形状和印刷电路板上的封装的布局(例如，如果屏蔽周边是圆形，该通道将围绕该电子元件设置成圆形；如果屏蔽周边是矩形，那么该通道将围绕该电子元件设置成矩形)。
通常，所用的通道的数目由电子元件封装10的工作频率或其谐波频率确定。在工作频率较高的情况下，太少的通道潜在地允许辐射通过通道70之间泄漏。频率越高，辐射的波长越短并且越能够从较小的空间之间泄漏出。因此，如果存在太少的通道，那么通道70将相互间隔得越开，并且将允许更多的电磁辐射泄漏通过。
另一方面，通道是固有的电容性的并且能够改变印刷电路板上的导电迹线的所希望的阻抗。太多的通道70会使通过导电迹线的数据或传输失真或者可能会影响上升时间(例如，脉冲从低压电平的到高压电平变化所需要的时间)。但是，一些试验已经表明，附加的第一通道的影响很大，但是当较多的通道附加于该印刷电路板时，随后的通道的影响趋向于消失。
因此，通道70的数目和位置取决于设置在被屏蔽的印刷电路板上的电子元件封装的工作频率。优选地，通道设置成相互间隔开的距离大约等于最高频率的波长或其谐波波长的约1/2和约1/4之间，以便形成有效的EMI屏蔽并防止辐射从该通道70之间泄漏出。例如，在一些实施例中，相邻的通道可以设置成相互分开在约1mm和约100mm之间。正如能够理解的，对于不同的频率，该间隔可更大或更小。
通常，通道用铜、镍、金、银、锡或焊料(例如锡/铅组合)等来镀。通道可以用无电或电解镀工艺来镀。该镀层可以通过该通道70延伸并暴露在该印刷电路板的外部平表面上，其允许该通道70的导电表面的小的小环被露出并与EMI屏蔽42或接地迹线52接触。
该通道的直径在某些情况下可以在约0.015″和约0.040″之间。正如能够理解的，该通道的直径越小，制造该印刷电路板通常越贵。此外，如果该孔的直径太小，电镀该通道的整个深度将变得非常困难。如果该孔的直径太大，当对PCB进行焊接时，它可能流出并在该板上形成焊接凸起，这是不希望的。
沿着EMI屏蔽42每侧设置的通道的数目取决于被屏蔽的电子元件封装的工作频率。频率越高，越近的通道将被设置在一起，并且因此沿着该屏蔽的每侧将设置越多的通道。
正如能够理解的，通道70的高度取决于印刷电路板的层数和通道将需要通过多少层以到达该接地平面68。例如，4层印刷电路板通常总共是0.064″厚(每层约0.016)。通道70能够通过一层之间或所有4层之间。这对于具有较多层数的印刷电路板同样如此。
通道70可以电连接于一层或多层接地层68。接地层68可以是印刷电路板的接地平面或者它可以是电连接于接地平面的层、迹线或层的一部分。该接地层可以用任何常规的或专利的方法接地(例如，用埋入通道或盲通道连接于接地平面)。例如，在接地平面连接于底部基片层(或其他基片层)的实施例中，印刷电路板64可以包括中间接地层56，一些或全部通道70被连接于该中间接地层中。因此，一个或多个通道可以将中间接地层56电连接于接地平面。
如图7所示，多个通道70形成间隔开的导电元件的互连接的网络，导电元件遍及该印刷电路板64的内部结构延伸，从而为电子元件封装10形成开口的网状的底部EMI屏蔽。当与外部的EMI屏蔽42连接时，该组合提供基本上整个地围绕芯片12和导电引线20的EM I屏蔽，并减少对周围的电子元件的电磁辐射。该EMI屏蔽的顶部(例如EMI屏蔽42)是连续的，而底部是开放的(例如，导电通道70和接地层68更像是网状的或笼状的)。通道之间的间隔足够小以便基本上减少其可能逃逸的电磁辐射干扰的量。
选择地，印刷电路板64可以包括设置在该印刷电路板64的第一表面72上的表面接地迹线52，以便基本上围绕该电子元件封装10。EMI屏蔽42可以连接于外部接地迹线52以便通过通道70将该EMI屏蔽42电连接于接地层68。对于许多小型电子器件来说(移动电话、PDA等)，表面接地迹线一般在1mm和2mm宽之间(约0.040”到0.080”)。但是在一些大型电子器件的情况下，接地迹线可以是4mm(0.160”)宽或更宽。虽然通道一般是沿着该接地迹线的宽度的中心的，但是通道70可以沿着接地迹线52的宽度设置在任何位置。
如图8所示，本发明还包括印刷电路板64，在该印刷电路板中，表面接地迹线被去掉，而EMI屏蔽42直接接地于该通道70的上端。这种实施例减少了在该印刷电路板的表面68上的元件数目。例如，去掉了宽度为0.040”-0.080”之间的表面接地迹线，而直接接触该通道(其直径为约0.028”)的EMI屏蔽14节省了约0.012”到0.52”印刷电路板的面积，其可以用于其他元件的设置或减少印刷电路板和电子器件的整个尺寸。
在示出图1实施例的这个具体的例子中，电连接于EMI屏蔽42的接地的焊球52应当直接接触该通道70的金属化表面，该金属化表面一般具有延伸到该印刷电路板的平表面68上的被镀上的金属涂层的部分。
正如能够被本领域的普通技术人员所理解的，虽然图1的封装10示为与没有表面接地迹线的印刷电路板64一起使用(图8)，而图4的封装10示为与具有表面接地迹线52的印刷电路板64一起使用(图7)，但是本发明所有的实施例均可以用于这两种情况。
例如，如果图4的封装10与没有表面接地迹线52的印刷电路板64一起使用，为了加强该金属化端部63和该通道之间的电连接，小的凹坑或凹陷(未示出)可以形成在该EMI屏蔽的凸缘48上并且向印刷电路板突出以便与通道位置对齐并配合。该凹坑将延伸进该通道的内径中。使EMI屏蔽42连接并接地于通道的另一种方法是利用导电材料或粘结剂以适当的取向和位置连接该EMI屏蔽42的端部63，以对通道70形成适当的电连接。这样能够在通道的位置上使用粘结剂小滴并将该屏蔽放置在该小滴中，从而在EMI屏蔽42和该通道之间形成电连接。可选地，粘结剂的小滴可以以对应于通道70的构图的方式设置在EMI屏蔽42上，并且然后将该封装10和涂覆粘结剂的EMI屏蔽42放置在印刷电路板64上。
通过使用在印刷电路板上战略地形成的通道将EMI屏蔽接地于接地平面的更完全的说明描述在与此一道提交的名称为“用于印刷电路板的电磁干扰屏蔽”、同时待审并且共有的美国专利申请______(代理律师案卷号020843-002810US)，其整个内容结合于此供参考。
图9示出本发明的另一种屏蔽方案。示于图9的屏蔽方案可附加于通道的网络使用，还可作为对通道的网络的一种替换。如图9所示，在该电子元件封装10的下面并围绕该电子元件封装10的印刷电路板的表面的一部分用诸如铜、镍、金、银、锡、铅或其组合等的导电材料74镀上。
在这种结构中，电子元件封装10用敷形涂层24封装，该敷形涂层24通常是绝缘的，因此防止电子元件封装与导电材料74短路。从电子元件封装10向外延伸的布线连接将延伸到特定的单个引线焊盘76以便为封装10形成所希望的电通路。如果不使用敷形涂层来隔离电子元件封装10的底部，用于防止该封装10短路的另一种方法是施加绝缘材料，例如PBT、聚碳酸酯、Ultem
Figure C20048001020400261
、teflon
Figure C20048001020400262
、Kapton、聚芘咯(polypyrroyle)、碳氟化合物等，以保护封装10不与暴露的导电材料74短路。
优选地，导电材料74可以是与接地迹线52相同的材料。正如可以看到的，单个的引线焊盘76可以设置在印刷电路板64的表面上并且被非导电表面78(例如印刷电路板或另外的绝缘材料)围绕。因此，电子元件封装10的引线支架66可以仍然接触印刷电路板64上的引线焊盘76，而导电材料74将不影响信号通路或信号质量。虽然没有示出，导电材料74可以与通道或其他导电元件电接触，这使得导电材料能够接地于诸如接地平面的接地层。
如果希望，该EMI屏蔽可以直接连接于导电材料74以使该EMI屏蔽接地。在这样的实施例中，将不需要接地迹线52。但是在其他实施例中，该EMI屏蔽可以接地于接地迹线52并且将不与导电材料74接触。在这样的实施例中，用绝缘空间80将导电材料74与接地迹线52分开。
虽然本发明的附图示出了多个不同的电子元件封装结构，但是应当理解，本发明的构思可以应用于其他类型的芯片和封装结构。例如，本发明可以很容易地适于与下述封装一起使用：小外廓封装(SOP)、薄形小外廓封装(TSOP)、小外廓J形引线封装(SOJ)、四边扁平封装(QFP)、四边扁平J形引线封装(QFJ)、四边扁平无引线封装(QFN)、插片载体封装(TFP)、或诸如倒装芯片球栅格阵列(FC-BGA)、插片自动连接球栅格阵列(TAB-BGA)、增强的球栅格阵列(EBGA)、精细间距球栅格阵列(FBGA)、面向下的并且热增强的球栅格阵列(FDB-BGA)这样的球栅格阵列。
虽然已经描述了本发明的优选实施例，但是本领域的普通技术人员应当认识到，在不脱离本发明的精神实质和范围的情况下可以使用各种修改、替代和等同物。例如，可以用成形的金属罩代替导电地涂覆的聚合物屏蔽。而且，上述任何芯片封装可以选择地包括连接于芯片非有源表面的散热装置或散热器(未示出)。

Claims (33)

1.一种有屏蔽的电子元件封装，包括：
芯片；
包括多个迹线的基底；
多个引线，其将芯片的有源表面电连接于基底中的所述多个迹线；
连接于基底中的所述迹线的外部焊球触点，其中所述焊球触点从基底的表面延伸并且被构造成连接于印刷电路板上的导电引线；
涂敷有导电层的聚合物屏蔽，其形成围绕所述芯片和所述多个引线的至少一部分的凹腔，其中所述涂敷有导电层的聚合物屏蔽可电连接于接地迹线；以及
设置在所述涂敷有导电层的聚合物屏蔽上的绝缘的敷形涂层，以便封装所述芯片和多个引线，其中所述绝缘的敷形涂层使所述外部焊球触点露出。
2.如权利要求1的有屏蔽的电子元件封装，其中所述接地迹线设置在所述基底中，并且与一些外部焊球触点电连通。
3.如权利要求2的有屏蔽的电子元件封装，其中所述涂敷有导电层的聚合物屏蔽的一部分可以用导电粘结剂连接于所述接地迹线。
4.如权利要求1的有屏蔽的电子元件封装，其中所述接地迹线设置在印刷电路板表面上，其中所述涂敷有导电层的聚合物屏蔽的端部可以延伸超过所述敷形涂层和所述基底的外表面，并且被构造成接触所述印刷电路板上的表面接地迹线。
5.如权利要求1的有屏蔽的电子元件封装，其中所述涂敷有导电层的聚合物屏蔽包括顶表面和多个侧壁，
其中凸缘在基本平行于所述基底第一表面的平面中以一定角度从所述侧壁延伸。
6.如权利要求5的有屏蔽的电子元件封装，其中所述涂敷有导电层的聚合物屏蔽包括热塑树脂层和在所述树脂层的至少一个表面上的至少一个金属层。
7.如权利要求6的有屏蔽的电子元件封装，其中所述金属层的厚度在1微米和50微米之间。
8.如权利要求6的有屏蔽的电子元件封装，其中所述金属层包括真空淀积的金属涂层。
9.如权利要求6的有屏蔽的电子元件封装，其中所述金属层设置在面向所述芯片和所述基底的热塑树脂层的表面上，其中所述金属层电接触所述接地迹线。
10.如权利要求6的有屏蔽的电子元件封装，其中所述热塑树脂层包括高温热成形薄膜。
11.如权利要求1的有屏蔽的电子元件封装，其中所述涂敷有导电层的聚合物屏蔽包括多个小孔。
12.如权利要求11的有屏蔽的电子元件封装，其中所述小孔被定位并且其尺寸被做成使所述多个引线被电连接于基底中的所述多个迹线。
13.如权利要求1的有屏蔽的电子元件封装，其中所述涂敷有导电层的聚合物屏蔽产生在敷形涂层和所述芯片之间的间隔。
14.如权利要求1的有屏蔽的电子元件封装，还包括设置在所述芯片和所述涂敷有导电层聚的合物屏蔽之间的填充材料。
15.如权利要求14的有屏蔽的电子元件封装，其中所述填充材料具有类似于它所封装的电子芯片的热膨胀系数的热膨胀系数。
16.如权利要求14的有屏蔽的电子元件封装，其中所述填充材料具有类似于所述敷形涂层的热膨胀系数的热膨胀系数。
17.如权利要求13的有屏蔽的电子元件封装，其中所述凹腔的尺寸做成接纳与所述芯片连接的散热装置。
18.如权利要求17的有屏蔽的电子元件封装，还包括延伸通过所述涂敷有导电层的聚合物屏蔽和所述散热装置的多个通道，其中，所述敷形涂层填充所述多个通道。
19.如权利要求1的有屏蔽的电子元件封装，其中所述涂敷有导电层的聚合物屏蔽包括多个分层的涂敷有导电层的聚合物层。
20.如权利要求1的有屏蔽的电子元件封装，其中将所述芯片的有源表面电连接于所述基底中的所述多个迹线的所述多个引线包括焊接凸起阵列。
21.如权利要求1的有屏蔽的电子元件封装，其中将所述芯片的有源表面电连接于所述基底中的所述多个迹线的所述多个引线包括多个延长的的布线。
22.一种有屏蔽的封装，包括：
包含有源表面的芯片；
包含多个迹线的基底；
将所述芯片的有源表面电连接于所述基底中的多个迹线的多个引线；
连接于所述基底中的迹线的外部触点，其中所述外部触点被构造成连接于印刷电路板上的导电引线；
形成围绕所述芯片的至少一部分的凹腔的涂敷有导电层的聚合物屏蔽，其中所述涂敷有导电层的聚合物屏蔽电连接于所述基底中的接地迹线；
设置在由所述涂敷有导电层的聚合物屏蔽形成的凹腔中的填充材料；以及
设置在所述涂敷有导电层的聚合物屏蔽上的敷形涂层，用于封装所述芯片和多个引线，其中所述绝缘的敷形涂层使外部焊球触点露出。
23.如权利要求22的有屏蔽的封装，其中，所述填充材料包括散热器。
24.如权利要求23的有屏蔽的封装，其中所述散热器和所述涂敷有导电层的聚合物屏蔽包括多个通道，其中，所述敷形涂层填充所述多个通道。
25.如权利要求22的有屏蔽的封装，其中所述外部触点包括焊盘和焊球凸起。
26.如权利要求22的有屏蔽的封装，其中所述涂敷有导电层的聚合物屏蔽包括顶表面和多个侧壁，
其中凸缘在基本平行于所述基底第一表面的平面中以一定角度从所述侧壁延伸。
27.如权利要求26的有屏蔽的封装，其中所述涂敷有导电层的聚合物屏蔽包括热塑树脂层和在所述树脂层的至少一个表面上的至少一个金属层。
28.一种制造有屏蔽的封装的方法，包括：
提供包括多个引线的基底；
将芯片的有源表面电连接于所述多个引线；
将涂敷有导电层的树脂层连接于所述基底，以便所述芯片被定位在所述基底和所述涂敷有导电层的树脂层之间的凹腔中；
使所述涂敷有导电层的树脂层接地；以及
在所述涂敷有导电层的树脂层的至少一部分上施加敷形涂层，以便封装所述芯片和所述基底的至少一部分。
29.如权利要求28的方法，还包括通过使树脂层成形并且在所述成形的树脂层的至少一个表面上淀积至少一个导电层来形成所述涂敷有导电层的树脂层。
30.如权利要求28的方法，还包括用填充材料填充所述凹腔。
31.如权利要求28的方法，还包括将焊球凸起阵列连接于所述基底的露出的焊盘上。
32.如权利要求28的方法，其中接地所述涂敷有导电层的树脂层包括延伸在所述敷形涂层外面的所述涂敷有导电层的树脂层，并且使所述涂敷有导电层的树脂层接触印刷电路板上的接地迹线。
33.如权利要求28的方法，还包括将散热装置连接于所述芯片。
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WO2004093505A3 (en) 2004-12-09
US7109410B2 (en) 2006-09-19
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US20040240191A1 (en) 2004-12-02

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