CN102194769A - 芯片封装结构及方法 - Google Patents

芯片封装结构及方法 Download PDF

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CN102194769A
CN102194769A CN2010101222862A CN201010122286A CN102194769A CN 102194769 A CN102194769 A CN 102194769A CN 2010101222862 A CN2010101222862 A CN 2010101222862A CN 201010122286 A CN201010122286 A CN 201010122286A CN 102194769 A CN102194769 A CN 102194769A
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chip
substrate
weld pad
packaging
packaging structure
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肖俊义
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AMBIT ELECTRONICS (ZHONGSHAN) Co Ltd
Hon Hai Precision Industry Co Ltd
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AMBIT ELECTRONICS (ZHONGSHAN) Co Ltd
Hon Hai Precision Industry Co Ltd
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Priority to CN2010101222862A priority Critical patent/CN102194769A/zh
Priority to US13/034,616 priority patent/US20110221046A1/en
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Abstract

一种芯片封装结构，包括基板、芯片、封胶体、屏蔽层及保护层。芯片与基板电性连接，封胶体将芯片和基板封装于其内以形成封装体。基板包括至少部分裸露于封装体侧边的接地层。屏蔽层用于给芯片防电磁干扰，其覆盖封胶体并与接地层电性连接。保护层由绝缘材料制成，其覆盖屏蔽层以防止芯片封装结构与其它零件发生短路。本发明还提供一种芯片封装方法。本发明提供的芯片封装结构及方法，通过屏蔽层覆盖封胶体并与接地层电性连接以实现防电磁干扰，缩小了产品体积并降低了成本。

Description

芯片封装结构及方法
技术领域
本发明涉及半导体封装技术，特别涉及一种能防电磁干扰的芯片封装结构及方法。
背景技术
现有的芯片封装结构安装在电路板上，再将金属屏蔽盖罩住芯片封装结构以防电磁干扰。然而，这种防电磁干扰方式导致产品体积增大，不能满足电子产品小型化的发展趋势，且成本较高。
发明内容
有鉴于此，需提供一种能防电磁干扰的芯片封装结构。
还需提供一种能防电磁干扰的芯片封装方法。
一种芯片封装结构，包括基板、芯片、封胶体、屏蔽层及保护层。所述芯片与所述基板电性连接，所述封胶体将所述芯片和所述基板封装于其内以形成封装体。所述基板包括至少部分裸露于封装体侧边的接地层。屏蔽层用于给所述芯片防电磁干扰，其覆盖所述封胶体并与所述接地层电性连接。保护层由绝缘材料制成，其覆盖所述屏蔽层以防止所述芯片封装结构与其它零件发生短路。
一种芯片封装方法，包括：提供基板，所述基板包括至少部分裸露于侧边的接地层；将芯片固定于所述基板；电性连接所述芯片和所述基板；用封胶体将所述芯片和所述基板封装于其内以形成封装体；切割封装体以形成单个芯片封装结构；用屏蔽层覆盖所述封胶体并与所述接地层电性连接；及用保护层覆盖所述屏蔽层；其中，所述保护层由绝缘材料制成。
本发明的芯片封装结构及方法，通过屏蔽层覆盖所述封胶体并与所述接地层电性连接以实现防电磁干扰，缩小了产品体积并降低了成本。
附图说明
图1是本发明的芯片封装结构的剖视示意图。
图2是本发明的芯片封装方法。
主要元件符号说明
封胶体                            10
基板                              20
第一表面                          21
第二表面                          22
芯片座                            23
第一焊垫                          24
第二焊垫                          25
过孔                              26
金属层                            27
芯片                              30
连接线                            40
屏蔽层                            50
保护层                            60
黏着剂                            70
具体实施方式
图1是本发明的芯片封装结构100的剖视示意图。本发明的芯片封装结构100包括封胶体10、基板20、芯片30、多个连接线40、屏蔽层50及保护层60。
基板20包括第一表面21、与第一表面21相对的第二表面22、芯片座23、多个第一焊垫24、多个第二焊垫25及多个过孔26。芯片座23和所述第一焊垫24均位于第一表面21，所述第二焊垫25位于第二表面22。所述过孔26贯穿第一表面21和第二表面22，用于电性连接所述第一焊垫24和所述第二焊垫25。芯片封装结构100通过所述第二焊垫25焊接于电路板(未图示)。
基板20还包括多个金属层，其中一个金属层27位于基板20的第一表面21并裸露于侧边。金属层27与所述第一焊垫24电性连接。在本实施方式中，金属层27为基板20中的接地层。
芯片30通过黏着剂70固定于芯片座23。
连接线40电性连接芯片30和所述第一焊垫24，这样芯片30便与基板20电性连接。在本实施方式中，连接线40为金线。
封胶体10用于将连接线40、芯片30及基板20的第一表面21进行封装以形成封装体。在本实施方式中，封胶体10为黑胶。
屏蔽层50喷涂于封胶体10的外表面和基板20的侧边并与金属层27电性连接，以防电磁干扰。屏蔽层50与所述第二焊垫25相隔一定的距离，即屏蔽层50与所述第二焊垫25之间绝缘，从而有效避免屏蔽层50在焊接过程中的粘锡问题，即避免芯片封装结构100在焊接的过程中的粘锡问题。在其它实施方式中，屏蔽层50也可只喷涂于封胶体10的外表面并与金属层27电性连接而不覆盖基板20的侧边。在本实施方式中，屏蔽层50为金属层或其它能防电磁干扰的屏蔽材料。
保护层60由绝缘材料制成，喷涂于屏蔽层50的外表面，从而防止芯片封装结构100与相邻的其它零件发生短路，同时避免了屏蔽层50在焊接过程中的粘锡问题。在本实施方式中，保护层60为透明绝缘材料。
因芯片封装结构100本身具有屏蔽层50，即不需在电路板上安装屏蔽盖就能防电磁干扰，从而减少了电路板的尺寸，即缩小了产品体积并节约了成本。
图2为本发明的芯片封装方法的流程示意图。
步骤210：提供基板20。在本实施方式中，基板20包括第一表面21、与第一表面21相对的第二表面22、芯片座23、多个第一焊垫24、多个第二焊垫25及多个过孔26。芯片座23和所述第一焊垫24均位于第一表面21，所述第二焊垫25位于第二表面22。所述过孔26贯穿第一表面21和第二表面22，用于电性连接所述第一焊垫24和所述第二焊垫25。芯片封装结构100通过所述第二焊垫25焊接于电路板(未图示)。基板20还包括多个金属层，其中一个金属层27位于基板20的第一表面21并裸露于侧边。金属层27为接地层并与所述第一焊垫24电性连接。
步骤211：将芯片30固定于基板20的芯片座23上。
步骤212：通过连接线40电性连接芯片30和基板20的第一焊垫24。
步骤213：用封胶体10将连接线40、芯片30及基板20的第一表面21进行封装以形成封装体。在本实施方式中，封胶体10为黑胶。
步骤214：切割封装体以形成单个芯片封装结构。
步骤215：将屏蔽层50喷涂于封胶体10的外表面和基板20的侧边并与金属层27电性连接，以防电磁干扰。在其它实施方式中，屏蔽层50也可只喷涂于封胶体10的外表面并与金属层27电性连接而不覆盖基板20的侧边。
步骤216：将保护层60喷涂于屏蔽层50的外表面，以防止芯片封装结构100与相邻的其它零件发生短路，同时避免屏蔽层50在焊接过程中的粘锡问题。在本实施方式中，保护层60为透明绝缘材料。

Claims (10)

1.一种芯片封装结构，包括基板、芯片及封胶体，所述芯片与所述基板电性连接，所述封胶体封装所述芯片和所述基板以形成封装体，其特征在于，所述基板包括接地层，所述接地层至少部分裸露于所述封装体侧边，所述芯片封装结构还包括：
屏蔽层，用于给所述芯片防电磁干扰，所述屏蔽层覆盖所述封胶体并与所述接地层电性连接；及
保护层，由绝缘材料制成并覆盖所述屏蔽层，用于防止所述芯片封装结构与其它零件发生短路。
2.如权利要求1所述的芯片封装结构，其特征在于，所述基板还包括第一表面、与所述第一表面相对的第二表面、多个位于所述第一表面的第一焊垫及多个位于所述第二表面的第二焊垫，所述接地层位于所述第一表面。
3.如权利要求2所述的芯片封装结构，其特征在于，所述屏蔽层与所述第二焊垫之间绝缘。
4.如权利要求2所述的芯片封装结构，其特征在于，还包括多个连接线，所述连接线电性连接所述芯片和所述第一焊垫。
5.如权利要求2所述的芯片封装结构，其特征在于，所述接地层与所述第一焊垫电性连接。
6.一种芯片封装方法，其特征在于，包括：
提供基板，所述基板包括至少部分裸露于侧边的接地层；
将芯片固定于所述基板；
电性连接所述芯片和所述基板；
将所述芯片和所述基板封装于封胶体内以形成封装体；
切割封装体以形成单个芯片封装结构；
用屏蔽层覆盖所述封胶体并与所述接地层电性连接；及
用保护层覆盖所述屏蔽层；
其中，所述保护层由绝缘材料制成。
7.如权利要求6所述的芯片封装方法，其特征在于，所述基板还包括第一表面、与所述第一表面相对的第二表面、多个位于所述第一表面的第一焊垫及多个位于所述第二表面的第二焊垫，所述接地层位于所述第一表面。
8.如权利要求7所述的芯片封装方法，其特征在于，所述屏蔽层与所述第二焊垫之间绝缘。
9.如权利要求7所述的芯片封装方法，其特征在于，所述连接线电性连接所述芯片和所述第一焊垫。
10.如权利要求7所述的芯片封装方法，其特征在于，所述接地层与所述第一焊垫电性连接。
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