CN105514090A - 具电磁干扰屏蔽的半导体封装体及其制造方法 - Google Patents

具电磁干扰屏蔽的半导体封装体及其制造方法 Download PDF

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CN105514090A
CN105514090A CN201610059551.4A CN201610059551A CN105514090A CN 105514090 A CN105514090 A CN 105514090A CN 201610059551 A CN201610059551 A CN 201610059551A CN 105514090 A CN105514090 A CN 105514090A
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邱基综
欧英德
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Advanced Semiconductor Engineering Inc
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Abstract

本发明公开一种具电磁干扰屏蔽的半导体封装体及其制造方法。半导体封装体包括一屏蔽物，其连接多个配置在一晶片上的导电件。多个导电件被配置而分别地围住在晶片上的多个微结构件，而这些微结构件位在前述的导电件所形成的多个凹穴中以提供较佳的屏蔽效果。屏蔽物与多个导电件具电磁干扰屏蔽的作用。一种形成半导体封装体的方法包括下列步骤。提供一具有多个子单元的半导体晶片，设置至少一微结构件在各子单元，电连接微结构件与半导体晶片。形成多个导电件在半导体晶片上，各导体件环绕微结构件且形成多个凹穴，且微结构件在凹穴中。配置一屏蔽物在导体件上以将微结构件封闭在凹穴内。

Description

具电磁干扰屏蔽的半导体封装体及其制造方法
本发明是中国发明专利申请(申请号：201310180814.3，申请日：2013年5月16日，发明名称：具电磁干扰屏蔽的半导体封装体及其制造方法)的分案申请。
技术领域
本发明涉及一种半导体封装，且特别是涉及一种晶片级封装结构及其制造方法。
背景技术
对于大部分的电子元件或系统而言，电磁干扰(Electro-magneticinterference,EMI)是一个严重且具有挑战性的问题。由于电磁干扰通常会中断、降低或是限制电子元件或是电子系统的所有电路的有效性能，因此，电子元件或系统需具有有效的电磁干扰防护以确保可有效且安全的运作。
电磁干扰防护对于小尺寸且高密度的封装体或是高频运作的敏感性电子元件特别地重要。现有技术中，电磁干扰的防护方式是使用一金属片，并随之在半导体封装体上贴附或固定此金属片。
发明内容
为解决上述问题，在本发明的一实施例包括一半导体封装体。半导体封装体包括一半导体芯片及配置在半导体芯片的一上表面上的一微结构件。半导体封装体还包括一导电件配置在半导体芯片的上表面上。导电件围绕微结构件而划分出微结构件的范围，且导电件形成一凹穴，而微结构件在凹穴中。半导体封装体还包括一屏蔽物配置在导电件、凹穴、微结构件上以提供微结构件电磁干扰屏蔽。
在本发明的另一实施例包括一半导体封装体。半导体封装体包括一半导体芯片及配置在半导体芯片的一上表面上的一微结构件。半导体封装体还包括一导电件配置在半导体芯片的上表面上，围绕微结构件而划分出微结构件的范围。半导体封装体还包括一屏蔽物在微结构件上以提供微结构件电磁干扰屏蔽。屏蔽物包括一第一厚度及一第二厚度。第一厚度位在覆盖第一微结构件及第二微结构件的区域，且第二厚度位在未覆盖第一微结构件及第二微结构件的区域，其中第一厚度小于第二厚度。
在本发明的又一实施例包括一种形成半导体封装体的方法。本方法包括提供一具有多个子单元的半导体晶片。本方法还包括设置至少一微结构件在各子单元。本方法还包括电连接微结构件与半导体晶片。本方法还包括形成多个导电件在半导体晶片上，各导体件环绕至少一微结构件且形成多个凹穴，且微结构件在凹穴中。本方法还包括配置一屏蔽物在导体件上以将微结构件封闭在凹穴内。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附附图作详细说明如下。
附图说明
图1A是依照本发明的一实施例的多个半导体封装体的一阵列在晶片预分割形式的剖视图；
图1B是图1A中的椭圆1B的细部图；
图1C是图1A的多个半导体封装体的一阵列在设置屏蔽物之前的上视图；
图2A是依照本发明的另一实施例在预分割形式的阵列的多个半导体封装体的剖视图；
图2B是图2A的多个半导体封装体的一阵列在安装电磁干扰屏蔽之前的上视图；
图3A是依照本发明的其中一实施例的多个半导体封装体的一阵列在晶片预分割形式的剖视图；
图3B是图3A中其中一个半导体封装体的剖视图；
图4A是依照本发明的其中一实施例的多个半导体封装体的一阵列在晶片预分割形式的剖视图；
图4B是图4A中其中一个半导体封装体的剖视图。
符号说明
10、20、30、40、42：阵列
100、200、300、32、400、402：半导体封装体
101：接地垫
102：半导体晶片
102a、202a：上表面
102b、202b：下表面
102c、202c：周围
103：保护层
106：硅穿孔(TSV)结构
106a：金属插塞
106b：绝缘环
108：外部接触点
110：导电件
120、120a、120b：微结构件
125：电连接物
130：屏蔽物
130a：基层
130b：屏蔽层
132：凹穴
132a：第一凹穴
132b：第二凹穴
134：开口
220：半导体元件
220a：第一半导体元件
220b：第二半导体元件
具体实施方式
现在，将详细参照本发明的较佳实施例，此等较佳实施例的范例绘示于附图中。在附图及说明中，将尽可能使用相同的参考编号来表示相同或相似的部件。
请参考图1A，图1A绘示出根据本发明的一实施例的多个半导体封装体100的一阵列10在晶片预分割(pre-singulated)形式。阵列10包括一半导体晶片102，其具有多个芯片(以虚线在图示中指出)，这些芯片可以是具有一或多个集成电路的主动芯片，或是不具有主动电路，以做为载体或封装基板的非作用/虚拟芯片两者其一，多个硅穿孔(TSV)结构106，多个外部接触点108，多个导电件110，多个微结构件(micro-structureelement)120a、120b及一屏蔽件130。微结构件120a、120b在此共同地称为微结构件120，且配置于半导体晶片102的一上表面102a上。外部接触点108配置在半导体晶片102的一下表面102b上。半导体晶片102可以是晶片或是其他半导体材料例如砷化镓(GaAs)。在之后的分割制作工艺，半导体晶片102被切割为多个单独的芯片100(由多条以垂直虚线表示的切割线所定义)。分割并不会切过导电件110。
导电件110位在半导体晶片102的上表面102a上。导电件110的材料可以是例如导电粘着剂或是焊料。屏蔽物130位在导电件110上，在半导体晶片102上且覆盖微结构件120，但并非直接接触微结构件120。经由屏蔽物130的连结，导电件110、半导体晶片102及被围住的微结构件120被密封(seal)以抑止电磁干扰。
微结构件120可以是例如一集成电路或微机电(micro-electromechanicalsystem)元件。微机电元件可能包括微小尺寸的机电零件，例如马达、泵、阀、开关、电容器、加速度计、感应器、像素、扩音器、扬声器、陀螺仪或致动器等。微结构件120a、120b可能包括两种不同类型的微机电元件。微结构件120可以经由TSV结构106电连接于外部接触点108。外部接触点108可以是例如锡球或是金凸块。
图1B是图1A中的椭圆1B的局部放大剖视图。半导体晶片102还包括多个接地垫101及一保护层(passivationlayer)103，图1B中仅绘示出其中一个接地垫101。保护层103覆盖半导体晶片102的上表面但暴露出接地垫101及暴露出安装微结构件120的位置。TSV结构106包括一金属插塞106a及一环绕于金属插塞106a中央的绝缘环106b，且绝缘环106b与金属插塞106a电性绝缘。
在本实施例中，屏蔽物130包括一基层130a及一屏蔽层130b，且屏蔽层130b配置在基层130a之下。外部接触点108电连接于一外部电路件的接地端(图1B中未绘示)，此外部电路件例如是一印刷电路板。屏蔽层130b经由导电件110、TSV结构106及外部接触点108电连接于接地端。
基层130a可以是硅、玻璃或其他材料，而屏蔽层130b可以是例如铜、铬、金、银、镍、铝及其合金，或其他材料。屏蔽层130b可以具有例如约1到10微米的厚度，且由网板印刷法(screen-printing)、溅镀(sputtering)、电镀或其他方法形成。屏蔽层130b降低微机电元件的干扰与噪音，特别是像微机电扩音器、微机电加速度计及微积电陀螺仪。屏蔽层130b还可由例如化镍钯金(electrolessnickelelectrolesspalladiumimmersiongold,ENEPIG)制作工艺涂上一表面处理层(surfacefinishlayer)(例如镍、钯、金的叠层)。当导电件110是以焊料制成，表面处理层可加强与导电件110的接合。
与例如单层的薄铜层相比，屏蔽物130的两层配置有助益地提供更大的刚性。单层屏蔽物在中央处可能因为其自身的重量而下陷，并导致其接触到微结构件120，且可能损坏微结构件120使其短路等。然而，在其他实施例中，屏蔽层130b可包括一单层的金属。
请继续参考图1B，导电件110配置在接地垫101上，在保护层103上且在屏蔽层130b之下。当导电件110由焊料制成，其具有约15到30微米的高度，此高度较微结构件120的高度较高，其中微结构件120的高度约1到5微米。导电件110以此方式作用为间隔物或作为屏蔽层130b及半导体晶片102之间的支撑构件。屏蔽物130提供电磁干扰屏蔽，且屏蔽层130b经由导电件110、接地垫101、TSV结构106及外部接触点108而接地。
图1C是图1A的多个半导体封装体100的一阵列10在设置屏蔽物130之前的上视图。各导电件110围绕至少一微结构件120而划分出至少一微结构件120的范围，因此形成一凹穴132(请参考图1A)，且微结构件120在此凹穴132中，而屏蔽物130闭合此凹穴132。各导电件110可以是形状连续的结构，例如是正方形、矩形、圆形或其他多边形。各半导体封装体100的导电件110可能延伸至半导体封装体100的一部分的晶片102的周围120c，或可能如图1c的实施例所绘示，设置在周围120c。
请参考图2A，图2A绘示出根据本发明的另一实施例的多个半导体封装体200的一阵列20的剖视图。半导体封装体200与前述图1A至图1C的半导体封装体100相似，然而半导体封装体200是通过导电件110而分割。因此，请参考图2B，各导电件110围绕至少一微结构件120而划分出至少一微结构件120的范围，且导电件110延伸至封装200的一部分的晶片102的周围202c。
请参考图3A，图3A绘示出根据本发明的另一实施例的多个半导体封装体300的一阵列30的剖视图。半导体封装体300与图1A至图1C所描述的半导体封装体100相似。然而，各半导体封装体300包括相应于第一及第二微结构件120a、120b的第一及第二凹穴132a及132b。就各封装300而言，两个导电件110分别地围住微结构件120a、120b两者其中之一。
相比较于图1与图2的实施例，各凹穴132a及132b包括较高的高度，这是由于屏蔽物130在覆盖微结构件120a、120b的区域减少其厚度。此外，屏蔽物130包括一开口134，其暴露凹穴132到外界环境。第一微结构件120a可以是例如一微机电开关，而第二微结构件120b可以是例如一微机电扬声器，其具有一振膜以产生声音。开口134帮助声音由第二微结构件120b传送至凹穴132b之外。第一及第二凹穴132a及132b的大小可以不同，且可调整以符合不同型式或不同需求的微机电元件。
请参考图3B，图3B绘示出根据本发明的另一实施例的一半导体封装体32的剖视图。半导体封装体32包括一半导体元件220b及一电连接物125，如焊线。在本实施例中，半导体晶片102例如是一已切割的特殊应用集成电路(ApplicationSpecificIntegratedCircuit,ASIC)芯片，且被放置在一晶片上。为清楚表示图示，已切割的ASIC芯片上只有一部分的半导体封装体结构。
就各封装体32而言，两个导电件110分别地围住半导体元件220a、220b。第一凹穴132a容纳第一半导体元件220a，且第二凹穴132b容纳第二半导体元件220b。第一半导体元件220a可以是例如一微机电元件，如一微机电致动器，而第二半导体元件220b可以是一具有感测膜以感测声音震动的压力的微机电扩音器。第二凹穴132b具有开口134，使第二半导体元件220b(扩音器的膜)可感测环境的震动。第一及第二凹穴132a及132b的大小可以不同，且可调整以符合不同型式或不同需求的微机电元件。
请参考图4A，图4A绘示出根据本发明的另一实施例的多个半导体封装体400的一阵列40在晶片预分割形式。半导体封装体400经由导电件110分割。各导电件110围绕至少一微结构件120而划分出至少一微结构件120的范围。就各封装体400(在图示中由分割虚线所定义)而言，各导电件110以类似于一对一的方式围住一微结构件120。然而，在本实施例中，相邻的封装体400的导电件110是相互连接的，且沿虚线在分割制作工艺中被切割。取决于需要屏敝的微机电元件，屏蔽物130可具有或不具有凹穴132且/或具有或不具有开口134。
请参考图4B，图4B绘示出根据本发明的另一实施例的多个半导体封装体402的一阵列42在晶片预分割形式。半导体封装体402包括一半导体元件220及一电连接物125，如焊线。屏蔽物130包括凹穴132配置在半导体元件220上。屏蔽物130还可包括对齐记号(图示中未绘示)，其相应于晶片102上的对齐记号(图示中未绘示)，以帮助精确的对准与防止屏蔽物130相对于晶片102的偏移。屏蔽物130经由导电件110、TSV结构106、接地垫101及半导体晶片102的外部接触点108而接地。
屏蔽物130的形成可通过提供一具有多个凹穴132的硅平板或玻璃平板(基层130a)，并共形地(conformally)覆盖一金属层在硅平板或玻璃平板130a的底面。前述的金属层是通过溅镀或电镀形成。屏蔽层130b的材料可以是任何前述于图1B的材料。取决于半导体元件220高度，凹穴132的深度可以是例如约20至30微米。然而，屏蔽层130b的厚度及/或凹穴132的尺寸及/或凹穴132的形状可修改以符合设计需求。
一分割制作工艺随之执行于晶片102以形成单独的封装体402。分割制作工艺可以是例如一刀片切割制作工艺。分割制作工艺沿虚线的切割线切割，且可能切过导电件110或切割在导电件110的旁边。在本实施例中的半导体封装体402，屏蔽物130的屏蔽层130b及导电件110配置在晶片120上，共同作用为一种电磁干扰屏蔽以防护各半导体元件220受任何环境发射源的电磁干扰。
本实例中的封装结构用的电磁干扰屏蔽的设计，较佳地可根据产品需求而弹性地调整，因为凹穴的形状及/或位置可相应地修改。此外，相较于其他具有单一电磁干扰屏蔽的多个阵列排列的半导体元件，本实施例中的屏蔽层及环绕于元件的导电件在此提供电磁干扰屏蔽于单独的元件。在这样的方式中，可降低邻近元件的射频干扰且加强电磁干扰屏蔽的效果。
虽然已参考本发明的特定实施例描述和说明本发明，但这些描述和说明并不限制本发明。所属领域的技术人员应了解，可在不脱离由所附权利要求书界定的本发明的真实精神和范围的前提下作各种改变并替换等效物。这些说明可能并没有必要按比例绘制。由于制造技术和制造公差，本发明中的艺术表达方式与实际结构之间可能存在着差别。可能存在着本发明并未具体说明的其他实施例。说明书和附图被认为是说明性而不是限制性的。可作修改以使特定情况、材料、物质的组合物、方法或技术适合本发明的目的、精神和范围。所有所述修改均希望包含在本发明所附权利要求书的范围内。虽然已参考按特定顺序执行的特定操作描述本发明中揭示的方法，但应了解，这些操作可经组合、再分次或重新排序以形成不脱离本发明的教义的等效方法。因此，除非本发明中特别指示，这些操作的顺序和分组并不限制本发明。

Claims (10)

1.一种半导体封装体，其特征在于，包括:
半导体芯片，该半导体芯片包括至少一穿孔，该至少一穿孔的每一者包括一金属插塞及环绕于该金属插塞的一绝缘环，该绝缘环与该金属插塞电性绝缘；
微结构件，配置在该半导体芯片的一上表面上；
至少一导电件，配置在该半导体芯片的该上表面上，进而形成一凹穴，其中该微结构件在该凹穴中，且该至少一导电件电连接该至少一穿孔；以及
屏蔽物，配置在该导电件、该凹穴以及该微结构件上以提供该微结构件电磁干扰屏蔽，且该屏蔽物电连接于该导电件。
2.如权利要求1所述的半导体封装体，其中该屏蔽物包括基层以及金属屏蔽层，该金属屏蔽层覆盖在该基层。
3.如权利要求1所述的半导体封装体，其中该屏蔽物在覆盖该微结构件的区域包括第一厚度，而在未覆盖该微结构件的区域包括第二厚度，且该第一厚度小于该第二厚度。
4.如权利要求3所述的半导体封装体，其中该微结构件包括第一微结构件及第二微结构件，该屏蔽物包括该第一厚度，该第一厚度位在覆盖该第一微结构件及该第二微结构件的区域，且该第二厚度位在未覆盖该第一微结构件及该第二微结构件的区域。
5.如权利要求4所述的半导体封装体，其中该屏蔽物包括开口，该开口暴露一空间于外在环境，该空间在该屏蔽物之下而环绕该微结构件。
6.一种半导体封装体，其特征在于，包括:
半导体芯片，该半导体芯片包括至少一穿孔，且该半导体芯片是由半导体材料所制成；
微结构件，配置在该半导体芯片的一上表面上；
至少一导电件，配置在该半导体芯片的该上表面上，，且该至少一导电件电连接该至少一穿孔；以及
屏蔽物，配置在该微结构件上以提供该微结构件电磁干扰屏蔽，且该屏蔽物电连接于该导电件，其中该屏蔽物在覆盖该微结构件的区域包括第一厚度，而在未覆盖该微结构件的区域包括第二厚度，且该第一厚度小于该第二厚度。
7.如权利要求6所述的半导体封装体，其中该屏蔽物包括开口，该开口暴露一空间于外在环境，该空间在该屏蔽物之下而环绕该微结构件。
8.如权利要求6所述的半导体封装体，其中该屏蔽物包括基层以及金属屏蔽层，该金属屏蔽层覆盖在该基层。
9.如权利要求8所述的半导体封装体，其中该基层可以是硅或玻璃。
10.如权利要求6所述的半导体封装体，其中该至少一穿孔的每一者更包括环绕于该金属插塞的一绝缘环，该绝缘环与该金属插塞电性绝缘。
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