TWI492360B - 具電磁干擾屏蔽的半導體元件及其製造方法 - Google Patents

具電磁干擾屏蔽的半導體元件及其製造方法 Download PDF

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TWI492360B
TWI492360B TW102114395A TW102114395A TWI492360B TW I492360 B TWI492360 B TW I492360B TW 102114395 A TW102114395 A TW 102114395A TW 102114395 A TW102114395 A TW 102114395A TW I492360 B TWI492360 B TW I492360B
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microstructure
shield
microstructure member
thickness
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TW201351601A (zh
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Chi Tsung Chiu
Ying Te Ou
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Advanced Semiconductor Eng
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Description

具電磁干擾屏蔽的半導體元件及其製造方法
本發明是有關於一種半導體封裝，且特別是有關於一種晶圓級封裝結構及其製造方法。
對於大部分的電子元件或系統而言，電磁干擾(Electro-magnetic interference,EMI)是一個嚴重且具有挑戰性的問題。由於電磁干擾通常會中斷、降低或是限制電子元件或是電子系統的所有電路的有效性能，因此，電子元件或系統需具有有效的電磁干擾防護以確保可有效且安全的運作。
電磁干擾防護對於小尺寸且高密度的封裝體或是高頻運作的敏感性電子元件特別地重要。習知技術中，電磁干擾的防護方式是使用一金屬片，並隨之在半導體封裝體上貼附或固定此金屬片。
在本發明之一實施例包括一半導體封裝體。半導體封裝 體包括一半導體晶片及配置在半導體晶片的一上表面上的一微結構件。半導體封裝體更包括一導電件配置在半導體晶片的上表面上。導電件圍繞微結構件而劃分出微結構件的範圍，且導電件形成一凹穴，而微結構件在凹穴中。半導體封裝體更包括一屏蔽物配置在導電件、凹穴、微結構件上以提供微結構件電磁干擾屏蔽。
在本發明之另一實施例包括一半導體封裝體。半導體封裝體包括一半導體晶片及配置在半導體晶片的一上表面上的一微結構件。半導體封裝體更包括一導電件配置在半導體晶片的上表面上，圍繞微結構件而劃分出微結構件的範圍。半導體封裝體更包括一屏蔽物在微結構件上以提供微結構件電磁干擾屏蔽。屏蔽物包括一第一厚度及一第二厚度。第一厚度位在覆蓋第一微結構件及第二微結構件的區域，且第二厚度位在未覆蓋第一微結構件及第二微結構件的區域，其中第一厚度小於第二厚度。
在本發明之又一實施例包括一種形成半導體封裝體的方法。本方法包括提供一具有多個子單元的半導體晶圓。本方法更包括設置至少一微結構件在各子單元。本方法更包括電性連接微結構件與半導體晶圓。本方法更包括形成多個導電件在半導體晶圓上，各導體件環繞至少一微結構件且形成多個凹穴，且微結構件在凹穴中。本方法更包括配置一屏蔽物在導體件上以將微結構件封閉在凹穴內。
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
10、20、30、40、42‧‧‧陣列
100、200、300、32、400、402‧‧‧半導體封裝體
101‧‧‧接地墊
102‧‧‧半導體晶圓
102a、202a‧‧‧上表面
102b、202b‧‧‧下表面
102c、202c‧‧‧周圍
103‧‧‧保護層
106‧‧‧矽穿孔(TSV)結構
106a‧‧‧金屬插塞
106b‧‧‧絕緣環
108‧‧‧外部接觸點
110‧‧‧導電件
120、120a、120b‧‧‧微結構件
125‧‧‧電性連接物
130‧‧‧屏蔽物
130a‧‧‧基層
130b‧‧‧屏蔽層
132‧‧‧凹穴
132a‧‧‧第一凹穴
132b‧‧‧第二凹穴
134‧‧‧開口
220‧‧‧半導體元件
220a‧‧‧第一半導體元件
220b‧‧‧第二半導體元件
圖1A是依照本發明之一實施例的多個半導體封裝體的一陣列在晶圓預分割形式的剖面圖。
圖1B是圖1A中的橢圓1B的細部圖。
圖1C是圖1A的多個半導體封裝體的一陣列在設置屏蔽物之前的上視圖。
圖2A是依照本發明之另一實施例在預分割形式的陣列的多個半導體封裝體的剖面圖。
圖2B是圖2A的多個半導體封裝體的一陣列在安裝電磁干擾屏蔽之前的上視圖。
圖3A是依照本發明之其中一實施例的多個半導體封裝體的一陣列在晶圓預分割形式的剖面圖。
圖3B是圖3A中其中一個半導體封裝體的剖面圖。
圖4A是依照本發明之其中一實施例的多個半導體封裝體的一陣列在晶圓預分割形式的剖面圖。
圖4B是圖4A中其中一個半導體封裝體的剖面圖。
現在，將詳細參照本發明之較佳實施例，此等較佳實施例之範例繪示於附圖中。在附圖及說明中，將盡可能使用相同之參考編號來表示相同或相似之部件。
請參考圖1，圖1繪示出根據本發明之一實施例之多個半導體封裝體100的一陣列10在晶圓預分割(pre-singulated)形式。 陣列10包括一半導體晶圓102，其具有多個晶片(以虛線在圖示中指出)，這些晶片可以是具有一或多個積體電路的主動晶片，或是不具有主動電路，以做為載體或封裝基板的非作用/虛擬晶片兩者其一，多個矽穿孔(TSV)結構106，多個外部接觸點108，多個導電件110，多個微結構件(micro-structure element)120a、120b及一屏蔽件130。微結構件120a、120b在此共同地稱為微結構件120，且配置於半導體晶圓102的一上表面102a上。外部接觸點108配置在半導體晶圓102的一下表面102b上。半導體晶圓102可以是晶圓或是其他半導體材料例如砷化鎵(GsAs)。在之後的分割製程，半導體晶圓102被切割為多個單獨的晶片100(由多條以垂直虛線表示的切割線所定義)。分割並不會切過導電件110。
導電件110位在半導體晶圓102的上表面102a上。導電件110的材料可以是例如導電黏著劑或是焊料。屏蔽物130位在導電件110上，在半導體晶圓102上且覆蓋微結構件120，但並非直接接觸微結構件120。經由屏蔽物130的連結，導電件110、半導體晶圓102及被圍住的微結構件120被密封(seal)以抑止電磁干擾。
微結構件120可以是例如一積體電路或微機電(micro-electromechanical system)元件。微機電元件可能包括微小尺寸的機電零件，例如馬達、泵、閥、開關、電容器、加速度計、感應器、畫素、擴音器、揚聲器、陀螺儀或致動器等。微結構件120a、120b可能包括兩種不同類型的微機電元件。微結構件 120可以經由TSV結構106電性連接於外部接觸點108。外部接觸點108可以是例如錫球或是金凸塊。
圖1B是圖1A中的橢圓1B的局部放大剖面圖。半導體晶圓102更包括多個接地墊101及一保護層(passivation layer)103，圖1B中僅繪示出其中一個接地墊101。保護層103覆蓋半導體晶圓102的上表面但暴露出接地墊101及暴露出安裝微結構件120的位置。TSV結構106包括一金屬插塞106a及一環繞於金屬插塞106a中央的絕緣環106b，且絕緣環106b與金屬插塞106a電性絕緣。
在本實施例中，屏蔽物130包括一基層130a及一屏蔽層130b，且屏蔽層130b配置在基層130a之下。外部接觸點108電性連接於一外部電路件的接地端(圖1B中未繪示)，此外部電路件例如是一印刷電路板。屏蔽層130b經由導電件110、TSV結構106及外部接觸點108電性連接於接地端。
基層130a可以是矽、玻璃或其他材料，而屏蔽層130b可以是例如銅、鉻、金、銀、鎳、鋁及其合金，或其他材料。屏蔽層130b可以具有例如約1到10微米的厚度，且由網板印刷法(screen-printing)、濺鍍(sputtering)、電鍍或其他方法形成。屏蔽層130b降低微機電元件的干擾與噪音，特別是像微機電擴音器、微機電加速度計及微積電陀螺儀。屏蔽層130b更可由例如化鎳鈀金(electroless nickel electroless palladium immersion gold,ENEPIG)製程塗上一表面處理層(surface finish layer)(例如鎳、 鈀、金的疊層)。當導電件110是以焊料製成，表面處理層可加強與導電件110的接合。
與例如單層的薄銅層相比，屏蔽物130的兩層配置有助益地提供更大的剛性。單層屏蔽物在中央處可能因為其自身的重量而下陷，並導致其接觸到微結構件120，且可能損壞微結構件120使其短路等。然而，在其他實施例中，屏蔽層130b可包括一單層的金屬。
請繼續參考圖1B，導電件110配置在接地墊101上，在保護層103上且在屏蔽層130b之下。當導電件110由焊料製成，其具有約15到30微米的高度，此高度較微結構件120的高度較高，其中微結構件120的高度約1到5微米。導電件110以此方式作用為間隔物或作為屏蔽層130b及半導體晶圓102之間的支撐構件。屏蔽物130提供電磁干擾屏蔽，且屏蔽層130b經由導電件110、接地墊101、TSV結構106及外部接觸點108而接地。
圖1C是圖1A的多個半導體封裝體100的一陣列10在設置屏蔽物130之前的上視圖。各導電件110圍繞至少一微結構件120而劃分出至少一微結構件120的範圍，因此形成一凹穴132(請參考圖1A)，且微結構件120在此凹穴132中，而屏蔽物130閉合此凹穴132。各導電件110可以是形狀連續的結構，例如是正方形、矩形、圓形或其他多邊形。各半導體封裝體100的導電件110可能延伸至半導體封裝體100的一部分的晶圓102的周圍120c，或可能如圖1c的實施例所繪示，設置在周圍120c。
請參考圖2A，圖2A繪示出根據本發明之另一實施例之多個半導體封裝體200的一陣列20的剖面圖。半導體封裝體200與前述圖1A至圖1C的半導體封裝體100相似，然而半導體封裝體200是藉由導電件110而分割。因此，請參考圖2B，各導電件110圍繞至少一微結構件120而劃分出至少一微結構件120的範圍，且導電件110延伸至封裝200的一部分的晶圓102的周圍202c。
請參考圖3A，圖3A繪示出根據本發明之另一實施例之多個半導體封裝體300的一陣列30的剖面圖。半導體封裝體300與圖1A至圖1C所描述的半導體封裝體100相似。然而，各半導體封裝體300包括相應於第一及第二微結構件120a、120b的第一及第二凹穴132a及132b。就各封裝300而言，兩個導電件110分別地圍住微結構件120a、120b兩者其中之一。
相較於圖1與圖2的實施例，各凹穴132a及132b包括較高的高度，這是由於屏蔽物130在覆蓋微結構件120a、120b的區域減少其厚度。此外，屏蔽物130包括一開口134，其暴露凹穴132到外界環境。第一微結構件120a可以是例如一微機電開關，而第二微結構件120b可以是例如一微機電揚聲器，其具有一振膜以產生聲音。開口134幫助聲音由第二微結構件120b傳送至凹穴132b之外。第一及第二凹穴132a及132b的大小可以不同，且可調整以符合不同型式或不同需求的微機電元件。
請參考圖3B，圖3B繪示出根據本發明之另一實施例之一半導體封裝體32的剖面圖。半導體封裝體32包括一半導體元 件220b及一電性連接物125，如焊線。在本實施例中，半導體晶圓102例如是一已切割的特殊應用積體電路(Application Specific Integrated Circuit,ASIC)晶片，且被放置在一晶圓上。為清楚表示圖示，已切割的ASIC晶片上只有一部分的半導體封裝體結構。
就各封裝體32而言，兩個導電件110分別地圍住半導體元件220a、220b。第一凹穴132a容納第一半導體元件220a，且第二凹穴132b容納第二半導體元件220b。第一半導體元件220a可以是例如一微機電元件，如一微機電致動器，而第二半導體元件220b可以是一具有感測膜以感測聲音震動的壓力的微機電擴音器。第二凹穴132b具有開口134，使第二半導體元件220b(擴音器的膜)可感測環境的震動。第一及第二凹穴132a及132b的大小可以不同，且可調整以符合不同型式或不同需求的微機電元件。
請參考圖4A，圖4A繪示出根據本發明之另一實施例之多個半導體封裝體400的一陣列40在晶圓預分割形式。半導體封裝體400經由導電件110分割。各導電件110圍繞至少一微結構件120而劃分出至少一微結構件120的範圍。就各封裝體400(在圖示中由分割虛線所定義)而言，各導電件110以類似於一對一的方式圍住一微結構件120。然而，在本實施例中，相鄰的封裝體400的導電件110是相互連接的，且沿虛線在分割製程中被切割。取決於需要屏敝的微機電元件，屏蔽物130可具有或不具有凹穴132且/或具有或不具有開口134。
請參考圖4B，圖4B繪示出根據本發明之另一實施例之 多個半導體封裝體402的一陣列42在晶圓預分割形式。半導體封裝體402包括一半導體元件220及一電性連接物125，如焊線。屏蔽物130包括凹穴132配置在半導體元件220上。屏蔽物130更可包括對齊記號(圖示中未繪示)，其相應於晶圓102上的對齊記號(圖示中未繪示)，以幫助精確的對準與防止屏蔽物130相對於晶圓102的偏移。屏蔽物130經由導電件110、TSV結構106、接地墊101及半導體晶圓102的外部接觸點108而接地。
屏蔽物130的形成可藉由提供一具有多個凹穴132的矽平板或玻璃平板(基層130a)，並共形地(conformally)覆蓋一金屬層在矽平板或玻璃平板130a的底面。前述的金屬層是藉由濺鍍或電鍍形成。屏蔽層130b的材料可以是任何前述於圖1B的材料。取決於半導體元件220高度，凹穴132的深度可以是例如約20至30微米。然而，屏蔽層130b的厚度及/或凹穴132的尺寸及/或凹穴132的形狀可修改以符合設計需求。
一分割製程隨之執行於晶圓102以形成單獨的封裝體402。分割製程可以是例如一刀片切割製程。分割製程沿虛線的切割線切割，且可能切過導電件110或切割在導電件110的旁邊。在本實施例中的半導體封裝體402，屏蔽物130的屏蔽層130b及導電件110配置在晶圓120上，共同作用為一種電磁干擾屏蔽以防護各半導體元件220受任何環境發射源的電磁干擾。
本實例中的封裝結構用的電磁干擾屏蔽的設計，較佳地可根據產品需求而彈性地調整，因為凹穴的形狀及/或位置可相應 地修改。此外，相較於其他具有單一電磁干擾屏蔽的多個陣列排列的半導體元件，本實施例中的屏蔽層及環繞於元件的導電件在此提供電磁干擾屏蔽於單獨的元件。在這樣的方式中，可降低鄰近元件的射頻干擾且加強電磁干擾屏蔽的效果。
雖然已參考本發明的特定實施例描述和說明本發明，但這些描述和說明並不限制本發明。所屬領域的技術人員應瞭解，可在不脫離由所附權利要求書界定的本發明的真實精神和範圍的前提下作各種改變並替換等效物。這些說明可能並沒有必要按比例繪製。由於製造技術和製造公差，本發明中的藝術表達方式與實際結構之間可能存在著差別。可能存在著本發明並未具體說明的其他實施例。說明書和圖式被認為是說明性而不是限制性的。可作修改以使特定情況、材料、物質的組合物、方法或技術適合本發明的目的、精神和範圍。所有所述修改均希望包含在本發明所附權利要求書的範圍內。雖然已參考按特定順序執行的特定操作描述本發明中揭示的方法，但應瞭解，這些操作可經組合、再分次或重新排序以形成不脫離本發明的教義的等效方法。因此，除非本發明中特別指示，這些操作的順序和分組並不限制本發明。
10‧‧‧陣列
100‧‧‧半導體封裝體
102‧‧‧半導體晶圓
102a‧‧‧上表面
102b‧‧‧下表面
106‧‧‧矽穿孔結構
108‧‧‧外部接觸點
110‧‧‧導電件
120a、120b‧‧‧微結構件
130‧‧‧屏蔽物
132‧‧‧凹穴

Claims (10)

  1. 一種半導體封裝體，包括：一半導體晶片；一微結構件，配置在該半導體晶片的一上表面上；一導電件，配置在該半導體晶片的該上表面上，該導電件圍繞該微結構件而劃分出該微結構件的範圍，且該導電件形成一凹穴，該微結構件在該凹穴中；以及一屏蔽物，配置在該導電件、該凹穴以及該微結構件上以提供該微結構件電磁干擾屏蔽，該屏蔽物包括一開口，該開口暴露該凹穴於外在環境，其中該微結構件為可通過該開口與外在環境傳輸信號的微機電元件。
  2. 如申請專利範圍第1項所述之半導體封裝體，其中該導電件延伸至該晶片的一周圍。
  3. 如申請專利範圍第1項所述之半導體封裝體，其中該導電件設置在該晶片的一周圍。
  4. 如申請專利範圍第1項所述之半導體封裝體，其中該屏蔽物包括一基層以及一金屬屏蔽層，該金屬屏蔽層覆蓋在該基層。
  5. 如申請專利範圍第1項所述之半導體封裝體，其中該屏蔽物在覆蓋該微結構件的區域包括一第一厚度，而在未覆蓋該微結構件的區域包括一第二厚度，且該第一厚度小於該第二厚度。
  6. 如申請專利範圍第5項所述之半導體封裝體，其中該微結構件包括一第一微結構件及一第二微結構件，該屏蔽物包括該第 一厚度，該第一厚度位在覆蓋該第一微結構件及該第二微結構件的區域，且該第二厚度位在未覆蓋該第一微結構件及該第二微結構件的區域。
  7. 如申請專利範圍第1項所述之半導體封裝體，其中該半導體晶片包括至少一穿孔，且該屏蔽物電性連接於該導電件及該至少一穿孔。
  8. 一種半導體封裝體，包括：一半導體晶片；一微結構件，配置在該半導體晶片的一上表面上；一導電件，配置在該半導體晶片的該上表面上，該導電件圍繞該微結構件而劃分出該微結構件的範圍；以及一屏蔽物，配置在該微結構件上以提供該微結構件電磁干擾屏蔽，其中該屏蔽物在覆蓋該微結構件的區域包括一第一厚度，而在未覆蓋該微結構件的區域包括一第二厚度，且該第一厚度小於該第二厚度，該屏蔽物包括一開口，該開口暴露一空間於外在環境，該空間在該屏蔽物之下而環繞該微結構件，其中該微結構件為可通過該開口與外在環境傳輸信號的微機電元件。
  9. 如申請專利範圍第8項所述之半導體封裝體，其中該微結構件包括馬達、泵、閥、開關、電容器、加速度計、感應器、畫素、擴音器、揚聲器、陀螺儀或致動器等微機電元件。
  10. 一種形成半導體封裝體的方法，包括：提供一半導體晶圓，該半導體晶圓具有多個子單元；設置至少一微結構件在各該子單元；電性連接該微結構件與該半導體晶圓；形成多個導電件在該半導體晶圓上，各該導體件環繞至少一 該微結構件且形成多個凹穴，該些微結構件在該凹穴中；以及配置一屏蔽物在該些導體件上並在該屏蔽物形成一開口以暴露該凹穴於外在環境，其中該微結構件為可通過該開口與外在環境傳輸信號的微機電元件。
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