CN101317268B - 具有emi屏蔽的叠层多芯片封装 - Google Patents
具有emi屏蔽的叠层多芯片封装 Download PDFInfo
- Publication number
- CN101317268B CN101317268B CN2007800003883A CN200780000388A CN101317268B CN 101317268 B CN101317268 B CN 101317268B CN 2007800003883 A CN2007800003883 A CN 2007800003883A CN 200780000388 A CN200780000388 A CN 200780000388A CN 101317268 B CN101317268 B CN 101317268B
- Authority
- CN
- China
- Prior art keywords
- chip
- substrate
- ground plane
- solder sphere
- encapsulation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
一种具有EMI屏蔽元件的叠层多芯片封装,包括第一和第二基板,它们通过一个栅阵列金属连接结点,如球栅阵列,被安装在一起。每个基板有一个与之相连的导电层。电子元件被安装在第一和第二基板之间,并被一组金属连接结点包围住,金属连接结点也被电连接到此两个基板的导电层,以形成一个此元件的导电法拉第笼。
Description
技术领域
本发明涉及多芯片封装,特别是叠层多芯片封装。更特别地,本发明涉及一种具有EMI屏蔽的叠层多芯片封装,以避免封装里的芯片受到电磁干扰、或对封装里的其它元件产生电磁干扰。
背景技术
电磁干扰(EMI),也被称为射频干扰(RFI),是由电磁辐射引起,在电子电路设计里是一个重要的考虑因素。电磁辐射是由带有变化电信号的电子电路和元件发出。有三种主要技术用来改善或消除EMI。第一种技术是将敏感元件与电磁辐射源物理隔离。第二种技术是使用旁路或去藕电容和过滤器将不要的干扰信号接地。最后,第三种技术是使用法拉第笼(Faraday cage)或阻隔外壳来屏蔽敏感元件或产生EMI的元件。
当前电子电路设计的重点是趋向尺寸更小且功率更大的设备。相当大量的工作都在多芯片封装领域进行,其中多个集成电路(IC)芯片被紧密封装在一个小封装内。在这种封装内,物理隔离敏感设备和电磁辐射源是不可行的,且去藕也仅是部分有效。所以,在这些多芯片封装内屏蔽是一种重要的解决方案。
在当前芯片封装内最流行的屏蔽方式是通过使用导电罩壳来密封敏感元件或产生EMI的元件。元件被安装在支撑基板的一个区域上,在支撑基板下有一个接地层,一个金属盒、或其它形状的罩壳,被安装在元件上面,将元件密封在导电外壳内。但是,这种类型的金属罩壳在基板表面上占用了相当大的空间,并往往不是很坚固,由于固定罩壳在基板上的焊接点上的交变应力(cyclic stress),经常导致罩壳从基板表面移位。这同样阻碍了成型环氧树脂的流动,且如果电子设备所在环境条件突然发生变化,水蒸气可能在罩壳内积聚。
发明概述
所以,本发明的目的是提供一种具有EMI屏蔽空间的叠层多芯片封装,该屏蔽空间用于在封装内必须被隔离的敏感元件和产生EMI的元件。
鉴于前述,在此披露一种具有EMI屏蔽空间的叠层多芯片封装,其包括第一基板:包括第一面、第二面和在第一基板的绝缘层之间的第一接地层;第一芯片,安装在第一基板的第一面;第二芯片安装在第一基板的第二面、并与第一芯片电连接;第一焊接球阵列,位于第一基板的第一面并围绕第一芯片,位于第一焊接球阵列最里面的第一焊接球形成了围绕第一芯片的周界并电连接到所述第一接地层;第二基板:包括安装面和在第二基板的绝缘层之间的第二接地层及第二焊盘阵列;所述第二焊盘阵列位于第二基板的安装面、与第一焊接球阵列相对;通过与第一焊盘阵列和第二焊盘阵列相邻的栅阵列金属连接结点、第一基板被安装在第二基板上、使所述第一芯片夹在第一基板和第二基板之间;位于第二焊盘阵列最里面的第二电焊盘与第二接地层相连,所述第一接地层、第二接地层、第一焊接球、第二焊盘形成了对第一芯片的导电屏蔽。
优选地,所述第一芯片被密封在一个树脂罩壳内,该罩壳与第二基板接触。
优选地,所述第一芯片是一射频集成电路芯片。
优选地,所述射频集成电路芯片厚度为5到7密尔之间。
优选地,所述第一焊接球通过第一基板的第一接地层过孔电连接到第一接地层,所述第二电焊盘通过第二基板的第二接地层过孔电连接到第二接地层。
优选地,第一和第二基板机械支撑并电连接多个电子元件。
优选地,所述第一芯片用于控制第二芯片。
从以下的描述,本发明将变得更加清楚。
附图说明
现通过例子并结合附图描述本发明的典型实施例,其中:
图1是依照本发明的一个具有EMI屏蔽的叠层多芯片封装的典型实施例的横截面图,
图2是图1叠层多芯片封装的第二截面图,
图3是图2区域III的截面图,
图4是EMI屏蔽外壳的切开的透视图,
图5描述一个典型球栅阵列的覆盖区,
图6描述用于典型实施例的球栅阵列覆盖区,
图7描述典型实施例的第一变化,和
图8描述典型实施例的第二变化。
具体实施例描述
在本说明书和权利要求里,1密尔(mil)=25.4微米(1×10-6m)。
通常,本发明是一个叠层多芯片封装,其具有第一和第二基板,第一和第二基板通过栅格阵列的金属连接结点,如焊球栅阵列,被安装在一起。每个基板有一个接地层,其处于基板绝缘层之间。一个敏感元件或产生EMI的元件被安装在第一和第二基板之间,并被一组金属连接结点围住,金属连接结点也被电连接到此两个基板的接地层,以形成一个此元件的导电法拉第笼。
在附图里,描述了本发明在多芯片集成封装里实施的一个典型实施例,多芯片集成封装具有射频(RF)和数字集成电路(IC)芯片,其被一起封装在一个叠层基板排列里。这种排列经常被称为叠层多芯片模块(MCM)。 但是,这个典型的例子不是意在限制本发明适用的范围或功能。本领域有经验的技术人员将会明白,本发明也可以适用于其它类型的叠层基板排列,比如其中期望隔离一个或多个元件以免噪音干扰或避免产生噪音干扰到封装的其它部分。而且,典型实施例是一个单层封装,只具有一个支撑基板,其被连接到系统基板或母板。有经验的技术人员将会明白,本发明可以等同地应用到多叠层基板,并可以被应用在与系统基板分离的两个或多个互连基板之间。一种特别的IC芯片构造也被描述用来说明本发明,这也不是意在限制本发明的使用范围或功能。其它芯片类型、元件和/或其组合也可以与本发明一起使用。本发明通常应用于任何敏感电子元件或产生EMI的元件,它们必须被隔离在一个分层的基板封装内。
参考附图,在典型实施例里,MCM 1被安装在主系统板或母板2上,通过球栅阵列(BGA)3相互连接。MCM 1包括一个支撑基板10,其有两个数字IC芯片11、12安装在其第一面,和一个RF芯片13安装在其第二面。数字IC芯片11、12是一个存储芯片和一个逻辑芯片,用来控制RF模块1。RF芯片13必须足够薄以便被安装在RF模块1和主板2之间的BGA3支起空间33内。一个典型的RF芯片是15-25密尔厚:对一个稳固的BGA支起距离而言太厚了。但是,芯片能够变薄到5-7密尔之间。在IC技术和制造领域内变薄芯片是惯用方法。,RF模块支撑基板10在其一个或多个表面上有印刷电路,也有焊盘并使用互连线14来安装芯片11、12、13到支撑基板10上。数字IC和RF芯片11、12、13通过基板上的电镀通孔(过孔)而互相连接。对本发明而言,印刷电路和芯片互连过孔不是决定性的,所以在此不作详细说明。
RF模块支撑基板10有一个或多个导电接地层15位于绝缘层16、17之间,绝缘层由环氧树脂或其它合适的非导电材料制成。这种类型的基板在印刷电路板技术和制造领域是惯常使用的。模块基板10通过球栅阵列(BGA)3被安装和连接到系统基板20上。在RF模块基板10的第二面上有许多以栅格样式排列的焊接球30、31围住RF芯片13。一个典型的BGA栅格样式如图5所示。参照图6,依照本发明,在BGA 3里,形成RF芯片空间32的周边的最里面的焊接球31(如图6实线所示)是电连接到在模块基板10内的接地层15的。通过基板10第二面和接地层15之间 的接地层过孔34,提供这种电连接。接地层过孔34与模块基板10第二面上的过孔焊盘35或凸点下金属(UBM)焊头连接,它们又与内周边的焊接球31附着在一起。
通过相应的栅格样式排列的电焊盘21、37或UBM点,承受RF模块1的BGA 3的焊接球30、31,从而使得RF模块1连接在系统基板20的表面。在焊盘21、37栅格的中央,是一个对应的RF芯片空间。系统基板20也具有一个或多个导电接地层22位于绝缘层23、24之间。形成系统基板RF芯片空间周边的最里面的焊盘37,和模块支撑基板10上的内边界的焊接球31一样,被同样电连接到系统基板接地层22。即,接地层过孔36是在系统基板的内边界焊盘37和接地层22之间。所以,当RF模块1被安装在系统基板2上时,通过球栅阵列BGA 3,就形成了关于RF芯片13的法拉第笼,用于芯片的EMI屏蔽。法拉第笼包括RF模块基板10和系统基板的上接地层和下接地层15、22,上下接地层又通过多个接地层过孔34、36和内边界的BGA焊接球31在被屏蔽的芯片空间32周围互连。BGA3的其余焊接球30(图6虚线所示)提供RF模块1和系统2之间的电连接。RF模块1和系统2之间的电连接与模块基板10和系统基板20的接地层15、22是电隔离的。
法拉第笼在RF芯片13周围提供一个接地导电外壳,以避免其受到由邻近数字芯片11、12和变化的电子信号引起的电子和EMI干扰。尽管在形成笼边缘的内边界的焊接球31之间有空隙,但是这基本上不影响笼的屏蔽效果,因为电磁波不会穿透尺寸小于其波长的过孔太远。大多数现代电子设备,如手机、无线网络适配器和电信设备,在从300MHz到10GHz的超高频(UHF)频道上运作。这是一个1米到100毫米的波长范围。通常,焊接球31之间的空隙仅有几百微米,远远小于EMI波的波长,其通常不会穿过焊接球31之间的空隙。
为了使设计更加稳固,避免使用中的震动,芯片和互连线都被塑封在环氧树脂罩壳40、41里。这在电路板和MCM组件里是惯常使用的,这些方法都是本领域技术人员所熟知的。但是,在本发明里,被屏蔽的RF芯片13或其它元件,位于基板10、20之间的BGA支起空间33里。所以, 密封RF芯片13的环氧树脂铸件40的厚度,需要被控制和调整以作为一个用于BGA支起空间33的隔离物。RF芯片13的树脂铸件40与系统基板20接触,以协助支撑模块基板10,防止BGA焊接球30、31在再流热过程期间破裂。在焊膏印刷过程期间,可以增加在每个铸造焊盘上的焊膏量,以增强焊接球高度和基板翘曲的变化容差。
应该理解,对本领域技术人员显而易见的修改和替换不能被认为超出本发明的范围。例如,BGA互连应用在叠层基板之间,但是,显而易见的是,技术人员可以使用针脚栅阵列(PGA)、引脚栅阵列(LGA)或其它栅类型互连系统来包围互连基板之间屏蔽空间。
在典型实施例里,屏蔽笼(即法拉第笼)的上和下导电表面,是由基板的接地层15、22提供。但是,应该理解,这些导电层不需要延伸到基板的整个区域,也不需要在基板的层之间。参照图7,在其中一个基板(例如系统基板20)的一个表面上可以有一个大导电层或焊盘25,用来承接内边界的焊接球31,并形成屏蔽笼的一边。另外,参照图9,在安装有屏蔽电子元件的基板的另一面,可以有一个类似的导电层或焊盘26,并通过电镀通孔27而连接到焊接球31。
Claims (7)
1.一种具有EMI屏蔽空间的叠层多芯片封装,包括:
第一基板(10):包括第一面、第二面和在第一基板的绝缘层之间的第一接地层(15);第二芯片(13),安装在第一基板的第一面;第一芯片(11、12)安装在第一基板的第二面、并与第二芯片电连接;第一焊接球阵列,位于第一基板的第二面并围绕第二芯片,位于第一焊接球阵列最里面的第一焊接球(31)形成了围绕第二芯片的周界并电连接到所述第一接地层(15);
第二基板(20):包括安装面和在第二基板的绝缘层之间的第二接地层(22)及第二焊盘阵列;所述第二焊盘阵列位于第二基板的安装面、与第一焊接球阵列相对,通过栅阵列金属连接结点(3)、第一基板被安装在第二基板上、使所述第二芯片(13)夹在第一基板和第二基板之间;位于第二焊盘阵列最里面的第二焊盘(37)与第二接地层(22)相连,所述第一接地层(15)、第二接地层(22)、第一焊接球(31)、第二焊盘(37)形成了对第二芯片(13)的导电屏蔽。
2.根据权利要求1所述的叠层多芯片封装,其中所述第二芯片(13)被密封在一个树脂罩壳内,该罩壳与第二基板接触。
3.根据权利要求1所述的叠层多芯片封装,其中所述第二芯片(13)是一射频集成电路芯片。
4.根据权利要求3所述的叠层多芯片封装,其中所述射频集成电路芯片厚度为5到7密尔之间。
5.根据权利要求1所述的叠层多芯片封装,其中该所述第一焊接球(31)通过第一基板(10)的第一接地层过孔(34)电连接到第一接地层(10),所述第二电焊盘(37)通过第二基板(20)的第二接地层过孔(36)电连接到第二接地层(20)。
6.根据权利要求1所述的叠层多芯片封装,其中第一和第二基板机械支撑并电连接多个电子元件。
7.根据权利要求1-6任一所述的叠层多芯片封装,其中所述第一芯片用于控制第二芯片。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/521,753 | 2006-09-15 | ||
US11/521,753 US7514774B2 (en) | 2006-09-15 | 2006-09-15 | Stacked multi-chip package with EMI shielding |
PCT/CN2007/070614 WO2008040200A1 (en) | 2006-09-15 | 2007-09-04 | Stacked multi-chip package with emi shielding |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101317268A CN101317268A (zh) | 2008-12-03 |
CN101317268B true CN101317268B (zh) | 2011-06-22 |
Family
ID=39187723
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2007800003883A Active CN101317268B (zh) | 2006-09-15 | 2007-09-04 | 具有emi屏蔽的叠层多芯片封装 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7514774B2 (zh) |
CN (1) | CN101317268B (zh) |
WO (1) | WO2008040200A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103094256A (zh) * | 2011-11-08 | 2013-05-08 | 中国科学院微电子研究所 | 一种封装系统 |
Families Citing this family (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7191516B2 (en) * | 2003-07-16 | 2007-03-20 | Maxwell Technologies, Inc. | Method for shielding integrated circuit devices |
US7550853B2 (en) * | 2007-10-10 | 2009-06-23 | Itt Manufacturing Enterprises, Inc. | Electrical isolation of monolithic circuits using a conductive through-hole in the substrate |
US7808101B2 (en) * | 2008-02-08 | 2010-10-05 | Fairchild Semiconductor Corporation | 3D smart power module |
TWI467729B (zh) * | 2008-07-07 | 2015-01-01 | Advanced Semiconductor Eng | 射頻模組之封裝結構及其製造方法 |
FI20095110A0 (fi) | 2009-02-06 | 2009-02-06 | Imbera Electronics Oy | Elektroniikkamoduuli, jossa on EMI-suoja |
US8710634B2 (en) * | 2009-03-25 | 2014-04-29 | Stats Chippac Ltd. | Integrated circuit packaging system with an integral-interposer-structure and method of manufacture thereof |
US20100244223A1 (en) * | 2009-03-25 | 2010-09-30 | Cho Namju | Integrated circuit packaging system with an integral-interposer-structure and method of manufacture thereof |
US8148813B2 (en) * | 2009-07-31 | 2012-04-03 | Altera Corporation | Integrated circuit package architecture |
US8008121B2 (en) * | 2009-11-04 | 2011-08-30 | Stats Chippac, Ltd. | Semiconductor package and method of mounting semiconductor die to opposite sides of TSV substrate |
US9082762B2 (en) * | 2009-12-28 | 2015-07-14 | International Business Machines Corporation | Electromigration-resistant under-bump metallization of nickel-iron alloys for Sn-rich solder bumps in Pb-free flip-clip |
US8569869B2 (en) * | 2010-03-23 | 2013-10-29 | Stats Chippac Ltd. | Integrated circuit packaging system with encapsulation and method of manufacture thereof |
WO2012023332A1 (ja) * | 2010-08-18 | 2012-02-23 | 株式会社 村田製作所 | 電子部品及びその製造方法 |
TWM411098U (en) | 2011-01-28 | 2011-09-01 | Chunghwa Picture Tubes Ltd | Circuit board assembly |
JP5693710B2 (ja) * | 2011-04-14 | 2015-04-01 | 三菱電機株式会社 | 高周波パッケージ |
US9018904B2 (en) | 2011-08-12 | 2015-04-28 | GM Global Technology Operations LLC | Wireless battery charging apparatus mounted in a vehicle designed to reduce electromagnetic interference |
US9096177B2 (en) | 2011-08-12 | 2015-08-04 | GM Global Technology Operations LLC | Apparatus for securing a rechargeable electronic device with respect to a surface of a wireless battery charging apparatus of a vehicle |
US8637963B2 (en) | 2011-10-05 | 2014-01-28 | Sandisk Technologies Inc. | Radiation-shielded semiconductor device |
US20130134553A1 (en) | 2011-11-30 | 2013-05-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interposer and semiconductor package with noise suppression features |
US9295157B2 (en) * | 2012-07-13 | 2016-03-22 | Skyworks Solutions, Inc. | Racetrack design in radio frequency shielding applications |
CN102779811B (zh) | 2012-07-20 | 2015-02-04 | 华为技术有限公司 | 一种芯片封装及封装方法 |
CN103137609B (zh) * | 2013-03-04 | 2015-12-09 | 华进半导体封装先导技术研发中心有限公司 | 带有电磁屏蔽结构的集成电路封装结构 |
US8987872B2 (en) | 2013-03-11 | 2015-03-24 | Qualcomm Incorporated | Electromagnetic interference enclosure for radio frequency multi-chip integrated circuit packages |
US20140291818A1 (en) * | 2013-03-26 | 2014-10-02 | Broadcom Corporation | Integrated Circuit Device Facilitating Package on Package Connections |
CN103579202B (zh) * | 2013-11-20 | 2016-06-01 | 华进半导体封装先导技术研发中心有限公司 | 有机基板半导体器件电磁屏蔽结构及制作方法 |
CN104797124B (zh) * | 2014-01-20 | 2018-07-03 | 联想(北京)有限公司 | 一种屏蔽方法及电子设备 |
CN106464218B (zh) * | 2014-02-25 | 2019-05-10 | 天工方案公司 | 关于改进的射频模块的系统、设备和方法 |
JP6356450B2 (ja) * | 2014-03-20 | 2018-07-11 | 株式会社東芝 | 半導体装置および電子回路装置 |
CN104837327A (zh) * | 2015-05-21 | 2015-08-12 | 小米科技有限责任公司 | 电路保护结构及电子装置 |
WO2017033564A1 (ja) * | 2015-08-27 | 2017-03-02 | 株式会社村田製作所 | 高周波モジュール |
US9824979B2 (en) | 2015-12-29 | 2017-11-21 | Stmicroelectronics, Inc. | Electronic package having electromagnetic interference shielding and associated method |
JP2018088629A (ja) | 2016-11-29 | 2018-06-07 | ソニーセミコンダクタソリューションズ株式会社 | 高周波モジュール、および通信装置 |
US11233014B2 (en) * | 2017-01-30 | 2022-01-25 | Skyworks Solutions, Inc. | Packaged module having a ball grid array with grounding shielding pins for electromagnetic isolation, method of manufacturing the same, and wireless device comprising the same |
TWI663701B (zh) * | 2017-04-28 | 2019-06-21 | 矽品精密工業股份有限公司 | 電子封裝件及其製法 |
US10784213B2 (en) | 2018-01-26 | 2020-09-22 | Hong Kong Applied Science and Technology Research Institute Company Limited | Power device package |
DE212019000228U1 (de) * | 2018-03-23 | 2020-10-30 | Murata Manufacturing Co., Ltd. | Hochfrequenzmodul und Kommunikationsgerät |
DE212019000227U1 (de) * | 2018-03-23 | 2020-11-02 | Murata Manufacturing Co., Ltd. | Hochfrequenzmodul und Kommunikationsgerät |
GB2584106B (en) * | 2019-05-21 | 2024-03-27 | Pragmatic Printing Ltd | Flexible electronic structure |
CN111128908B (zh) * | 2019-11-22 | 2024-04-16 | 中国电子科技集团公司第十三研究所 | 三维堆叠电路结构及其制备方法 |
CN111029324A (zh) * | 2019-11-22 | 2020-04-17 | 中国电子科技集团公司第十三研究所 | 三维微波模块电路结构及其制备方法 |
JP2021106341A (ja) * | 2019-12-26 | 2021-07-26 | 株式会社村田製作所 | 高周波モジュールおよび通信装置 |
JP2022092959A (ja) * | 2020-12-11 | 2022-06-23 | 株式会社村田製作所 | 高周波モジュール |
CN117501442A (zh) * | 2021-10-12 | 2024-02-02 | 华为技术有限公司 | 一种封装结构、电路板组件及电子设备 |
CN115119487A (zh) * | 2022-04-15 | 2022-09-27 | 平头哥(上海)半导体技术有限公司 | 电磁干扰屏蔽组件、制造方法以及电磁干扰屏蔽方法 |
CN117202481A (zh) * | 2023-09-08 | 2023-12-08 | 中国电子科技集团公司第二十六研究所 | 基于三维堆叠结构的模组及其制备方法 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5796170A (en) * | 1996-02-15 | 1998-08-18 | Northern Telecom Limited | Ball grid array (BGA) integrated circuit packages |
US5955789A (en) * | 1997-04-16 | 1999-09-21 | International Business Machines Corporation | Ball grid array module |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5136366A (en) * | 1990-11-05 | 1992-08-04 | Motorola, Inc. | Overmolded semiconductor package with anchoring means |
US5233504A (en) * | 1990-12-06 | 1993-08-03 | Motorola, Inc. | Noncollapsing multisolder interconnection |
US5056215A (en) * | 1990-12-10 | 1991-10-15 | Delco Electronics Corporation | Method of providing standoff pillars |
US5166772A (en) * | 1991-02-22 | 1992-11-24 | Motorola, Inc. | Transfer molded semiconductor device package with integral shield |
US6734539B2 (en) * | 2000-12-27 | 2004-05-11 | Lucent Technologies Inc. | Stacked module package |
US6486534B1 (en) * | 2001-02-16 | 2002-11-26 | Ashvattha Semiconductor, Inc. | Integrated circuit die having an interference shield |
US6740959B2 (en) * | 2001-08-01 | 2004-05-25 | International Business Machines Corporation | EMI shielding for semiconductor chip carriers |
US7049691B2 (en) * | 2002-10-08 | 2006-05-23 | Chippac, Inc. | Semiconductor multi-package module having inverted second package and including additional die or stacked package on second package |
JP3858854B2 (ja) * | 2003-06-24 | 2006-12-20 | 富士通株式会社 | 積層型半導体装置 |
US7279786B2 (en) * | 2005-02-04 | 2007-10-09 | Stats Chippac Ltd. | Nested integrated circuit package on package system |
US7271496B2 (en) * | 2005-02-04 | 2007-09-18 | Stats Chippac Ltd. | Integrated circuit package-in-package system |
US7759782B2 (en) * | 2006-04-07 | 2010-07-20 | Tessera, Inc. | Substrate for a microelectronic package and method of fabricating thereof |
US7732907B2 (en) * | 2006-05-30 | 2010-06-08 | Stats Chippac Ltd. | Integrated circuit package system with edge connection system |
-
2006
- 2006-09-15 US US11/521,753 patent/US7514774B2/en active Active
-
2007
- 2007-09-04 WO PCT/CN2007/070614 patent/WO2008040200A1/en active Application Filing
- 2007-09-04 CN CN2007800003883A patent/CN101317268B/zh active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5796170A (en) * | 1996-02-15 | 1998-08-18 | Northern Telecom Limited | Ball grid array (BGA) integrated circuit packages |
US5955789A (en) * | 1997-04-16 | 1999-09-21 | International Business Machines Corporation | Ball grid array module |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103094256A (zh) * | 2011-11-08 | 2013-05-08 | 中国科学院微电子研究所 | 一种封装系统 |
CN103094256B (zh) * | 2011-11-08 | 2015-12-02 | 华进半导体封装先导技术研发中心有限公司 | 一种封装系统 |
Also Published As
Publication number | Publication date |
---|---|
WO2008040200A1 (en) | 2008-04-10 |
US7514774B2 (en) | 2009-04-07 |
US20080067656A1 (en) | 2008-03-20 |
CN101317268A (zh) | 2008-12-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101317268B (zh) | 具有emi屏蔽的叠层多芯片封装 | |
CN110767613B (zh) | 半导体封装件和包括该半导体封装件的天线模块 | |
US8241966B2 (en) | Methods of making an electronic component package and semiconductor chip packages | |
KR100282027B1 (ko) | 적층기판및볼그리드어레이모듈 | |
US6515870B1 (en) | Package integrated faraday cage to reduce electromagnetic emissions from an integrated circuit | |
US7242092B2 (en) | Substrate assembly with direct electrical connection as a semiconductor package | |
CN108987378B (zh) | 微电子装置 | |
KR20130076899A (ko) | 상부 ic 패키지와 결합하여 패키지-온-패키지 (pop) 어셈블리를 형성하는 하부 ic 패키지 구조체 및 그러한 하부 ic 패키지 구조체를 포함하는 pop 어셈블리 | |
CN108701681A (zh) | 屏蔽emi的集成电路封装和及其制造方法 | |
US6956285B2 (en) | EMI grounding pins for CPU/ASIC chips | |
CN100527412C (zh) | 电子电路模块及其制造方法 | |
CN101142678B (zh) | 模块板 | |
US20060214278A1 (en) | Shield and semiconductor die assembly | |
KR102451167B1 (ko) | 반도체 패키지 | |
US6943436B2 (en) | EMI heatspreader/lid for integrated circuit packages | |
CN103858227A (zh) | 晶圆级应用的rf屏蔽部 | |
KR20140083084A (ko) | 전자파 차폐층을 갖는 반도체 패키지 및 그 제조방법 | |
CN111653551B (zh) | 一种具有高抗电磁脉冲干扰能力的bga芯片封装结构 | |
KR20110029541A (ko) | 전자파 차폐수단을 갖는 반도체 패키지 | |
US6355978B1 (en) | Package for accommodating electronic parts, semiconductor device and method for manufacturing package | |
KR101741648B1 (ko) | 전자파 차폐 수단을 갖는 반도체 패키지 및 그 제조 방법 | |
CN211238248U (zh) | 半导体封装 | |
CN111081696A (zh) | 半导体封装和制造半导体封装的方法 | |
CN211879381U (zh) | 一种具有高抗电磁脉冲干扰能力的倒装焊芯片封装结构 | |
KR20090039407A (ko) | 반도체 패키지 및 그 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |