JP5684349B1 - 半導体装置および半導体装置の検査方法 - Google Patents
半導体装置および半導体装置の検査方法 Download PDFInfo
- Publication number
- JP5684349B1 JP5684349B1 JP2013187132A JP2013187132A JP5684349B1 JP 5684349 B1 JP5684349 B1 JP 5684349B1 JP 2013187132 A JP2013187132 A JP 2013187132A JP 2013187132 A JP2013187132 A JP 2013187132A JP 5684349 B1 JP5684349 B1 JP 5684349B1
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- ground
- semiconductor device
- layer
- conductive shield
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2853—Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
- H01L2224/48228—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
Claims (5)
- 第1の面および第2の面を有する配線基板と、
前記第1の面上に設けられた半導体チップと、
前記第2の面上に設けられ、第1のグランド端子と第2のグランド端子とを備えた外部接続端子と、
前記半導体チップを封止するように前記第1の面上に設けられた封止樹脂層と、
前記配線基板の側面の少なくとも一部と前記封止樹脂層とを覆う導電性シールド層と、
を具備する半導体装置であって、
前記半導体装置は、
前記導電性シールド層に電気的に接続された第1のグランド配線と、
前記導電性シールド層に電気的に接続され、かつ前記導電性シールド層との間を除き前記第1のグランド配線と電気的に分離された第2のグランド配線と、をさらに備え、
前記第1のグランド端子は前記第1のグランド配線に電気的に接続され、
前記第2のグランド端子は前記第2のグランド配線に電気的に接続されることを特徴とする半導体装置。 - 前記配線基板は、
前記第1の面と前記第2の面との間に設けられた絶縁層と、
前記絶縁層を貫通して設けられ、前記第1のグランド配線または前記第2のグランド配線に電気的に接続されたビアと、をさらに備え、
前記第1のグランド配線または前記第2のグランド配線、および前記ビアの少なくとも一つは、前記配線基板の側面に露出し、かつ前記導電性シールド層に接する請求項1に記載の半導体装置。 - 前記配線基板の接続パッドまたは前記半導体チップと前記第1のグランド配線または前記第2のグランド配線とを電気的に接続するボンディングワイヤをさらに具備し、
前記ボンディングワイヤは、前記封止樹脂層の表面に露出し、かつ前記導電性シールド層に接する請求項1または請求項2に記載の半導体装置。 - 前記第1のグランド配線および前記第2のグランド配線の少なくとも一つは、前記半導体チップの少なくとも一部と重畳するベタ膜またはメッシュ膜を有する請求項1ないし請求項3のいずれか一項に記載の半導体装置。
- 請求項1ないし請求項4のいずれか一項に記載の半導体装置の前記第1のグランド端子と前記第2のグランド端子との間の抵抗値を測定する工程と、
前記抵抗値の測定結果に基づいて、前記第1のグランド配線および第2のグランド配線と前記導電性シールド層との接続状態を検査する工程と、を具備することを特徴とする半導体装置の検査方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013187132A JP5684349B1 (ja) | 2013-09-10 | 2013-09-10 | 半導体装置および半導体装置の検査方法 |
TW102146999A TWI503931B (zh) | 2013-09-10 | 2013-12-18 | Semiconductor device and semiconductor device inspection method |
CN201310729562.5A CN104425459B (zh) | 2013-09-10 | 2013-12-26 | 半导体装置及半导体装置的检查方法 |
US14/474,635 US20150070046A1 (en) | 2013-09-10 | 2014-09-02 | Semiconductor device and method of inspecting the same |
US16/386,774 US11715701B2 (en) | 2013-09-10 | 2019-04-17 | Semiconductor device and method of inspecting the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013187132A JP5684349B1 (ja) | 2013-09-10 | 2013-09-10 | 半導体装置および半導体装置の検査方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015004137A Division JP5933047B2 (ja) | 2015-01-13 | 2015-01-13 | 半導体装置の製造方法、半導体装置の検査方法、および半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP5684349B1 true JP5684349B1 (ja) | 2015-03-11 |
JP2015056427A JP2015056427A (ja) | 2015-03-23 |
Family
ID=52624997
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013187132A Active JP5684349B1 (ja) | 2013-09-10 | 2013-09-10 | 半導体装置および半導体装置の検査方法 |
Country Status (4)
Country | Link |
---|---|
US (2) | US20150070046A1 (ja) |
JP (1) | JP5684349B1 (ja) |
CN (1) | CN104425459B (ja) |
TW (1) | TWI503931B (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015073135A (ja) * | 2015-01-13 | 2015-04-16 | 株式会社東芝 | 半導体装置の製造方法 |
US11715701B2 (en) | 2013-09-10 | 2023-08-01 | Kioxia Corporation | Semiconductor device and method of inspecting the same |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20160036945A (ko) * | 2014-09-26 | 2016-04-05 | 삼성전기주식회사 | 인쇄회로기판 및 이를 포함하는 전자부품 패키지 |
US10379156B2 (en) * | 2015-05-29 | 2019-08-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump ball testing system and method |
JP6418605B2 (ja) * | 2015-07-31 | 2018-11-07 | 東芝メモリ株式会社 | 半導体装置および半導体装置の製造方法 |
JP6397806B2 (ja) | 2015-09-11 | 2018-09-26 | 東芝メモリ株式会社 | 半導体装置の製造方法および半導体装置 |
WO2017179325A1 (ja) | 2016-04-11 | 2017-10-19 | 株式会社村田製作所 | 高周波部品 |
US9793222B1 (en) | 2016-04-21 | 2017-10-17 | Apple Inc. | Substrate designed to provide EMI shielding |
JP6887326B2 (ja) * | 2017-06-28 | 2021-06-16 | 株式会社ディスコ | 半導体パッケージの形成方法 |
CN110998830B (zh) * | 2017-08-21 | 2023-09-22 | 株式会社村田制作所 | 电子部件模块以及电子部件模块的制造方法 |
CN112309873B (zh) * | 2019-07-26 | 2023-11-10 | 江苏长电科技股份有限公司 | 电磁屏蔽封装结构及其封装方法 |
US11694972B2 (en) * | 2020-06-09 | 2023-07-04 | Mediatek Inc. | Semiconductor package with heatsink |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2531464B2 (ja) * | 1993-12-10 | 1996-09-04 | 日本電気株式会社 | 半導体パッケ―ジ |
US6552425B1 (en) * | 1998-12-18 | 2003-04-22 | Intel Corporation | Integrated circuit package |
CN100454533C (zh) * | 2003-04-15 | 2009-01-21 | 波零公司 | 用于电子元件封装的emi屏蔽 |
KR100691632B1 (ko) | 2006-05-16 | 2007-03-12 | 삼성전기주식회사 | 반도체칩, 반도체칩의 제조방법 및 반도체칩 패키지 |
JP2008251608A (ja) | 2007-03-29 | 2008-10-16 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
JP2009236712A (ja) * | 2008-03-27 | 2009-10-15 | Toyota Motor Corp | 半導体集積回路及び半導体集積回路の検査装置、検査方法 |
WO2010014103A1 (en) | 2008-07-31 | 2010-02-04 | Skyworks Solutions, Inc. | Semiconductor package with integrated interference shielding and method of manufacture therof |
JP2010109274A (ja) | 2008-10-31 | 2010-05-13 | Sanyo Electric Co Ltd | 半導体モジュールおよび半導体モジュールの製造方法 |
US9362196B2 (en) | 2010-07-15 | 2016-06-07 | Kabushiki Kaisha Toshiba | Semiconductor package and mobile device using the same |
JP2012146882A (ja) | 2011-01-13 | 2012-08-02 | Renesas Electronics Corp | 半導体装置 |
JP2012151353A (ja) * | 2011-01-20 | 2012-08-09 | Sharp Corp | 半導体モジュール |
JP5512566B2 (ja) * | 2011-01-31 | 2014-06-04 | 株式会社東芝 | 半導体装置 |
US8766654B2 (en) * | 2012-03-27 | 2014-07-01 | Universal Scientific Industrial Co., Ltd. | Package structure with conformal shielding and inspection method using the same |
US8948712B2 (en) * | 2012-05-31 | 2015-02-03 | Skyworks Solutions, Inc. | Via density and placement in radio frequency shielding applications |
JP5684349B1 (ja) | 2013-09-10 | 2015-03-11 | 株式会社東芝 | 半導体装置および半導体装置の検査方法 |
KR102163707B1 (ko) * | 2013-11-14 | 2020-10-08 | 에스케이하이닉스 주식회사 | 전자기간섭 차폐층을 갖는 반도체 패키지 및 테스트 방법 |
-
2013
- 2013-09-10 JP JP2013187132A patent/JP5684349B1/ja active Active
- 2013-12-18 TW TW102146999A patent/TWI503931B/zh active
- 2013-12-26 CN CN201310729562.5A patent/CN104425459B/zh active Active
-
2014
- 2014-09-02 US US14/474,635 patent/US20150070046A1/en not_active Abandoned
-
2019
- 2019-04-17 US US16/386,774 patent/US11715701B2/en active Active
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11715701B2 (en) | 2013-09-10 | 2023-08-01 | Kioxia Corporation | Semiconductor device and method of inspecting the same |
JP2015073135A (ja) * | 2015-01-13 | 2015-04-16 | 株式会社東芝 | 半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US11715701B2 (en) | 2023-08-01 |
CN104425459B (zh) | 2017-10-20 |
CN104425459A (zh) | 2015-03-18 |
US20190244912A1 (en) | 2019-08-08 |
US20150070046A1 (en) | 2015-03-12 |
TW201511189A (zh) | 2015-03-16 |
TWI503931B (zh) | 2015-10-11 |
JP2015056427A (ja) | 2015-03-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5684349B1 (ja) | 半導体装置および半導体装置の検査方法 | |
JP6412844B2 (ja) | 電子部品 | |
JP6219155B2 (ja) | 半導体装置の製造方法 | |
TW201533860A (zh) | 配線基板及使用其之半導體裝置 | |
TW201415037A (zh) | 微節距探針卡介面裝置以及微節距探針卡 | |
TWI444625B (zh) | High frequency probe card | |
TWI430411B (zh) | 堆式防護結構 | |
CN109644550A (zh) | 柔性印制电路板 | |
JP5572066B2 (ja) | テスト用ボード | |
TW201703206A (zh) | 佈線基板 | |
JP2006229157A (ja) | シールドフレキシブルプリント配線板のシールドフィルム及びそれを用いたシールドフレキシブルプリント配線板 | |
WO2020057216A1 (zh) | 一种内存信号测试板 | |
JP5933047B2 (ja) | 半導体装置の製造方法、半導体装置の検査方法、および半導体装置 | |
CN111326502B (zh) | 半导体封装件以及获得半导体封装件的接触电阻的方法 | |
JP4045841B2 (ja) | プローブカード | |
TWM581284U (zh) | 串聯雙面晶片電阻 | |
JP2010139479A (ja) | プローブカード | |
JP2007311739A (ja) | Rf及び低電流相互接続用空間変換器 | |
JP2008226880A (ja) | 回路基板およびこれを用いた電気的接続装置 | |
US10153229B2 (en) | Method of manufacturing semiconductor products, corresponding semiconductor product and device | |
JP2012160576A (ja) | 半導体装置およびその製造方法 | |
KR20160071029A (ko) | 배선용 인터포저 및 이를 구비하는 전자 모듈 | |
JP2016009864A (ja) | 回路基板および回路基板を用いた電子部品の配置状態の検査方法 | |
JP2017130599A (ja) | 配線基板 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20141216 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20150114 |
|
R151 | Written notification of patent or utility model registration |
Ref document number: 5684349 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R151 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313111 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |