CN104425459B - 半导体装置及半导体装置的检查方法 - Google Patents

半导体装置及半导体装置的检查方法 Download PDF

Info

Publication number
CN104425459B
CN104425459B CN201310729562.5A CN201310729562A CN104425459B CN 104425459 B CN104425459 B CN 104425459B CN 201310729562 A CN201310729562 A CN 201310729562A CN 104425459 B CN104425459 B CN 104425459B
Authority
CN
China
Prior art keywords
wiring
semiconductor device
ground connection
terminal
face
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201310729562.5A
Other languages
English (en)
Other versions
CN104425459A (zh
Inventor
高野勇佑
后藤善秋
渡部武志
井本孝志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japanese Businessman Panjaya Co ltd
Kioxia Corp
Original Assignee
Toshiba Memory Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Memory Corp filed Critical Toshiba Memory Corp
Publication of CN104425459A publication Critical patent/CN104425459A/zh
Application granted granted Critical
Publication of CN104425459B publication Critical patent/CN104425459B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10Measuring as part of the manufacturing process
    • H01L22/14Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2853Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48095Kinked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15192Resurf arrangement of the internal vias
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788Glasses, e.g. amorphous oxides, nitrides or fluorides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

本发明提供能简便地进行导通检查的半导体装置及半导体装置的检查方法。实施方式的半导体装置(1)具备:布线基板(2),其具有第一面及第二面;半导体芯片(3),其设置于第一面上;外部连接端子(6),其设置于第二面上;密封树脂层(5),其设置于第一面上以将半导体芯片密封;和导电性屏蔽层(7),其将布线基板(2)的侧面的至少一部分和密封树脂层(5)覆盖。布线基板(2)具备:第一接地布线,其与导电性屏蔽层(7)电连接;和第二接地布线,其与导电性屏蔽层电连接且与第一接地布线电分离。

Description

半导体装置及半导体装置的检查方法
本申请以日本专利申请2013-187132号(申请日:2013年9月10日)为基础并享受其优先权。本申请通过参照该在先申请而包括其全部内容。技术领域
本发明涉及半导体装置及半导体装置的检查方法。
背景技术
在用于通信设备等的半导体装置中,为了抑制EMI(电磁干扰)等电磁波干扰,而使用将表面用导电性屏蔽层覆盖的结构。为了在上述结构中获得足够的磁场屏蔽效果,优选将导电性屏蔽层与接地布线电连接,并经接地布线使电磁噪声放出到外部。
此时,存在当导电性屏蔽层和接地布线的电连接不充分时不能得到磁场屏蔽效果的情况。因此,进行导电性屏蔽层和接地布线的电连接是否充分的检查(导通检查),并选择能获得足够的磁场屏蔽效果的半导体装置是有效的。上述导通检查通过使万用表(テスター)的端子与电连接于接地布线的外部连接端子和导电性屏蔽层接触并测定外部连接端子和导电性屏蔽层之间的电阻值来进行。在该检查方法中,由于必须使用专用的测定设备,因此很不便,此外,有可能损伤导电性屏蔽层的表面的一部分。因此,需要更简便且损伤小的检查方法。
发明内容
本发明要解决的问题是提供能简便地进行导通检查的半导体装置及半导体装置的检查方法。
实施方式的半导体装置具备:布线基板,其具有互相相对的.第一面及第二面;半导体芯片,其设置于布线基板的第一面上;密封树脂层,其设置于第一面上以将半导体芯片密封;和导电性屏蔽层,其将布线基板的侧面的至少一部分和密封树脂层覆盖。布线基板具备:第一接地布线,其与导电性屏蔽层电连接;和第二接地布线,其与导电性屏蔽层电连接且与第一接地布线电分离,外部连接端子具备:第一接地端子,其与第一接地布线电连接;和第二接地端子,其与第二接地布线电连接。
附图说明
图1是表示半导体装置的立体图。
图2是表示半导体装置的剖视图。
图3是布线基板的俯视示意图。
图4是布线基板的俯视示意图。
图5是表示半导体装置的另一例子的剖视图。
图6是表示半导体装置的另一例子的剖视图。
图7是表示半导体装置的另一例子的剖视图。
图8是表示半导体装置的另一例子的剖视图。
图9是表示电阻值的测定结果的图。
附图标记说明:
1 半导体装置 2 布线基板 3 半导体芯片 4A 焊料球4B 焊料球 5 密封树脂层 6 外部连接端子 6A 接地端子 6B 接地端子 7 导电性屏蔽层 8A 接合线(ボンディングワイヤ)8B 接合线 10A 露出部 10B 露出部 15A 导电层 15B 导电层20A 触点部 20B 触点部 21 绝缘层 21A 绝缘层21B 绝缘层 22 布线层 22A 布线22B 布线 22C 连接焊盘 23 布线层 23A 布线 23B 布线 24 过孔(ビア)24A 过孔24B 过孔 30 区域
具体实施方式
下面参照附图来说明实施方式的半导体装置。图1是表示半导体装置的立体图,图2是表示半导体装置的剖视图。
图1及图2所示的半导体装置1具备:具有第一面及第二面的布线基板2;具有电极焊盘且设置于布线基板2的第一面上的半导体芯片3;设置于布线基板2的第一面上以将半导体芯片3密封的密封树脂层5;设置于第二面上的外部连接端子6;将布线基板2的侧面的至少一部分和密封树脂层5覆盖的导电性屏蔽层7;和接合线8A及接合线8B。再有,布线基板2的第一面相当于图2中的布线基板2的上表面,第二面相当于图2中的布线基板2的下表面,布线基板2的第一面及第二面互相相对。
布线基板2具备:设置于第一面和第二面之间的绝缘层21;设置于第一面的布线层22;设置于第二面的布线层23;贯穿绝缘层21地设置的过孔(穿孔)24;设置于布线层22上的焊料抗蚀剂层28;和设置于布线层23上的焊料抗蚀剂层29。
作为绝缘层21,可使用例如硅基板和/或玻璃基板、陶瓷基板、环氧等树脂基板。此外,作为密封树脂层5,可使用例如绝缘性的有机树脂材料等。
在布线层22及布线层23,设有例如信号布线、电源布线、接地布线等。布线层22及布线层23的每个不限于单层结构,也可以是隔着绝缘层而层叠多个导电层的层叠结构。在布线层22及布线层23,使用例如铜箔和/或含有银或铜的导电性浆料并根据需要而在表面施行了镀镍和/或镀金等。
布线层22具有布线22A及布线22B。布线22A具有作为第一接地布线的功能,布线22B具有作为第二接地布线的功能。再有,向布线22A供给的接地电位的值可以与向布线22B供给的接地电位的值不同。此外,布线22A及布线22B具有连接焊盘。布线层23具有布线23A及布线23B。布线23A及布线23B具有连接焊盘。再有,布线23A也可具有作为第一接地布线的功能,且布线23B也可具有作为第二接地布线的功能。
贯穿绝缘层21地设有多个过孔24。过孔24具有例如在贯穿绝缘层21的开口的内面设置的导体层和在导体层的内侧填充的填孔材料。在导体层,使用例如铜箔和/或含有银或铜的导电性浆料并根据需要而在表面施行了镀镍和/或镀金等。填孔材料使用例如绝缘性材料或导电性材料来形成。再有,并不限于此,例如,也可通过在贯过孔内利用电镀等填充金属材料(铜等)来形成过孔24。
再有,作为外部连接端子6,设有例如信号端子、电源端子、接地端子等。例如,外部连接端子6具有接地端子6A及接地端子6B。接地端子6A与布线22A电连接,接地端子6B与布线22B电连接。换言之,接地端子6A与第一接地布线电连接,接地端子6B与第二接地布线电连接。外部连接端子6具有焊料球4。焊料球4设置于布线层23的连接焊盘上。再有,也可设置焊台(land)来代替焊料球4。
导电性屏蔽层7具有将从半导体芯片3等放射的多余电磁波屏蔽并防止向外部泄漏的功能。作为导电性屏蔽层7,优选使用例如电阻率低的金属层,且优选使用例如含有铜、银、镍等的金属层。通过使用电阻率低的金属层来作为导电性屏蔽层7,而能抑制经半导体芯片3和/或布线基板2而放射的多余电磁波的泄漏。
导电性屏蔽层7通过用例如转印法、丝网印刷法、喷涂法、喷射分配法(ジエットディスペンス法)、喷墨法、气溶胶法(エアロゾル法)等涂敷导电性浆料而形成。导电性浆料优选含有例如银和/或铜和树脂来作为主成分且电阻率低。此外,也可使用由无电解电镀法或电解电镀法将铜和/或镍等成膜的方法、由溅射法将铜等成膜的方法来形成导电性屏蔽层7。
导电性屏蔽层7的厚度优选基于其电阻率来设定。例如,优选的是,设定导电性屏蔽层7的厚度以使将导电性屏蔽层7的电阻率以厚度来分配的导电性屏蔽层7的电阻率的薄片(シート)电阻值为0.5Ω以下。通过使导电性屏蔽层7的薄片电阻值为0.5Ω以下,而能再现性良好地抑制多余电磁波从密封树脂层5泄漏。再有,能根据需要而以耐腐蚀性和/或耐迁移(マイグレーション)性优良的保护层覆盖导电性屏蔽层7。作为保护层,可使用聚酰亚胺树脂等。
接合线8A电连接于布线22A及半导体芯片3,接合线8B电连接于布线22B及半导体芯片3。再有,并不限于此,只要至少由接合线8A将布线基板2的连接焊盘或半导体芯片3与第一接地布线或第二接地布线电连接即可。
再有,本实施方式的半导体装置中,第一接地布线和第二接地布线的每个都电连接于导电性屏蔽层7,且第一接地布线及第二接地布线互相电分离(电学分离)。
例如,图3是布线基板2的俯视示意图。在图3中,为了方便,仅图示布线22A及图22B,省略了除此之外的构成要素。区域30是设置半导体芯片3及各种布线的区域。
在图3中,将布线22A及布线22B沿布线基板2的周缘配置以使两者互相电分离。布线22A在触点部20A处经过孔24A而与接地端子6A电连接,且布线22B在触点部20B处经过孔24B而与接地端子6B电连接。再有,触点部20A及触点部20B的每个都可设置多个。
再有,布线22A的侧面和布线22B的侧面在布线基板2的侧面露出。这样,布线22A的侧面和布线22B的侧面与导电性屏蔽层7接触。这样,通过将第一接地布线和第二接地布线与导电性屏蔽层7电连接而能经第一接地布线及第二接地布线使多余电磁波放出到外部。但是,并不限于此,也可采用布线23A的侧面和布线23B的侧面与导电性屏蔽层7接触的结构。
此外,布线22A具有在布线基板2的侧面露出的多个露出部10A,布线22B具有沿布线基板2的周缘在布线基板2的侧面露出的多个露出部10B。通过增大布线22A的面积及布线22B的、在布线基板2的侧面露出的面积,而能降低布线22A及布线22B与导电性屏蔽层7的接触电阻,且能提高磁场屏蔽效果。
在设有导电性屏蔽层的半导体装置中,例如,存在为了检测导电性屏蔽层所形成的屏蔽效果的有无而进行导电性屏蔽层和接地端子的导通检查的情况。通常的检查方法通过使导电性屏蔽层和接地端子与万用表接触并测定导电性屏蔽层和接地端子之间的电阻值来进行导电性屏蔽层和接地端子的导通检查。在该情况下,需要使用专用设备,且有可能因检查而损伤导电性屏蔽层。
在本实施方式的半导体装置中,将接地布线分为两个系统(第一接地布线、第二接地布线),将第一接地布线电连接于接地端子6A,将第二接地布线电连接于接地端子6B,且将第一接地布线及第二接地布线电连接于导电性屏蔽层7。因此,例如,能通过使接地端子6A和接地端子6B与万用表接触来测定接地端子6A和接地端子6B之间的电阻值,并基于测定结果来检查第一接地布线及第二接地布线和导电性屏蔽层7的连接状态。因此,即使不使用专用设备也能进行检查。此外,由于万用表不接触导电性屏蔽层7,因此能抑制检查所导致的导电性屏蔽层7的损伤。
再有,在本实施方式中,对于将接地布线分为两个系统的例子进行了说明,但是,并不限于此,也可分为三个系统以上(例如四个系统)。本实施方式的半导体装置适用于例如智能手机等便携式信息通信终端和/或触控型信息通信终端等。
此外,在本实施方式的半导体装置中,沿布线基板2的周缘配置第一接地布线或第二接地布线,从而第一接地布线及第二接地布线作为导电性屏蔽层发挥功能,且能抑制经半导体芯片3和/或布线基板2放射的多余电磁波的泄漏。
图9中表示在多个半导体装置的样本中使接地端子6A和接地端子6B与万用表接触时的接地端子6A和接地端子6B之间的电阻值的测定结果。如图9所示,测定的半导体装置的样本分为电阻值能测定的样本(此处,电阻值为0.1Ω~0.3Ω的样本(Sample1))和电阻值不能测定的开路状态的样本(Sample2)。
再有,表1中表示属于Sample1的样本和属于Sample2的样本的磁场屏蔽效果。再有,磁场强度为通过从离半导体装置的中央部以1mm上的磁场强度为基准来使测定设备扫描而得到的测定值。此外,磁场屏蔽效果为从有导电性屏蔽层的情况和没有导电性屏蔽层的情况的差分(差分)求出的值。
表1
Sample1 Sample2
磁场屏蔽效果(dB) 19.9 7.6
在表1中,相对于属于Sample1的样本的磁场屏蔽效果为19.9dB,属于Sample2的样本的磁场屏蔽效果为7.6dB,非常小,由此可知,属于Sample1的样本的磁场屏蔽效果的值和属于Sample2的样本的磁场屏蔽效果的值明显不同。由此可知,通过测定电阻值,而能挑选电连接不充分、即磁场屏蔽效果不充分的半导体装置。
再有,在本实施方式的半导体装置中,通过研究布线22A及布线22B的上表面布局,而能进一步提高磁场屏蔽效果。例如,也可使布线22A及布线22B延伸到布线基板的周缘以外的、例如没有设置其他布线的区域。此时,可使布线22A及布线22B的形状成为网格状。越使布线22A及布线22B延伸,则越能抑制在半导体装置1的厚度方向上经半导体芯片3和/或布线基板2而放射的多余电磁波的泄漏。此外,如图4所示,也可使用布线22B来作为导通检查用的布线。这样,在导通检查时,能抑制对于与接地布线连接的其他元件的影响。
再有,本实施方式的半导体装置的结构不限于上述结构。参照图5至图8来说明半导体装置的其他结构例。图5至图8是表示半导体装置的其他例子的剖视图。再有,在图5至图8所示的半导体装置中,对于与图2所示的半导体装置相同的部分标注相同标记,并适当地引用图2所示的半导体装置的说明。
图5所示的半导体装置1具备绝缘层21A及绝缘层21B以代替图2所示的半导体装置1的绝缘层21,还具备在绝缘层21A和绝缘层21B之间设置的导电层15。再有,对于半导体芯片3、密封树脂层5、外部连接端子6、导电性屏蔽层7、接合线8A、接合线8B的构成,引用图2所示的半导体装置1的说明。
作为绝缘层21A及绝缘层21B,可使用例如能适用于绝缘层21的基板。
导电层15具有导电层15A及导电层15B。导电层15A及导电层15B优选与半导体芯片3的至少一部分重叠。导电层15A具有作为第一接地布线的功能,导电层15B具有作为第二接地布线的功能。导电层15A及导电层15B优选为例如β膜或网状膜。换言之,第一接地布线及第二接地布线中的至少一个优选具有β膜或网状膜。
导电层15A及导电层15B可通过例如使用光刻技术在同一导电膜上形成抗蚀剂层并将该抗蚀剂层作为掩膜而将导电膜的一部分除去来形成。作为导电膜,优选使用例如可适用于导电性屏蔽层7的材料。
此外,过孔24A贯穿绝缘层21A、导电层15A及绝缘层21B地设置,过孔24B贯穿绝缘层21A、导电层15B及绝缘层21B地设置。再有,与信号布线等电连接的过孔24与导电层15A及导电层15B电分离。例如,通过预先在导电层15B设置开口而能将与信号布线等电连接的过孔24与导电层15A及导电层15B电分离。再有,对于布线22A、布线22B、布线23A、布线23B、过孔24A、过孔24B、焊料抗蚀剂层28、焊料抗蚀剂层29的构成,引用图2所示的半导体装置1的说明。
通过设置导电层15A及导电层15B,能提高抑制多余电磁波经布线基板2泄漏的效果。再有,导电层15A的侧面及导电层15B的侧面优选与导电性屏蔽层7接触。这样,能增加与导电性屏蔽层7的连接点数,因此能抑制接地端子6A及接地端子6B与导电性屏蔽层7的连接不良,且能降低接触电阻,因而能提高磁场屏蔽效果。
此外,图6所示的半导体装置1中,图5所示的半导体装置1的接合线8B的表面从密封树脂层5露出,并与导电性屏蔽层7接触。此时,在半导体芯片3设置虚设(ダミー)的电极焊盘以在该电极焊盘连接接合线8B。此外,过孔24B与导电层15B电分离,布线22B的侧面不与导电性屏蔽层7接触。例如,通过预先在导电层15B设置开口而能将过孔24B与导电层15B电分离。此时,布线23B或导电层15B的侧面可不与导电性屏蔽层7接触。通过采用上述结构,而使接地端子6B为导通检查用端子,在导通检查时,能抑制对于与接地布线连接的其他元件的影响。
此外,图7所示的半导体装置1中,图6所示的半导体装置1的接合线8B不与半导体芯片3电连接而与设置于布线层22的连接焊盘22C电连接。连接焊盘22C具有作为虚设焊盘的功能。通过采用上述结构,而使接地端子6B成为导通检查用端子,在导通检查时,能抑制对于与接地布线连接的其他元件的影响。
另外,图8所示的半导体装置1具有以下结构:图2所示的半导体装置1的过孔24A及过孔24B配置于布线基板2的周缘,且具有在厚度方向(过孔的贯穿方向)上被切断的形状。过孔24A的切断面在布线基板2的侧面露出,并与导电性屏蔽层7接触,过孔24B的切断面在布线基板2的侧面露出,并与导电性屏蔽层7接触。再有,在图8所示的半导体装置1中,使过孔24A及过孔24B的形状成为在厚度方向的途中被切断的形状,但是,并不限于此,也可使过孔24A及过孔24B的形状成为切断到厚度方向(过孔24的贯穿方向)的最后的形状。此外,过孔24A及过孔24B的切断面可不必通过中心,只要在切断面含有过孔的一部分即可。
通过采用使过孔24A及过孔24B的切断面与导电性屏蔽层7接触的结构,而能增加过孔24A及过孔24B与导电性屏蔽层7的接触面积、换言之、增加第一接地布线及第二接地布线和导电性屏蔽层7的接触面积,因此能降低接触电阻,且能提高磁场屏蔽效果。再有,也可设置图5所示的半导体装置1的绝缘层21A及绝缘层21B且设置导电层15A及导电层15B以代替图8所示的半导体装置1的绝缘层21。
再有,上述实施方式是一例,并不意在限定发明的范围。这些新实施方式能够以其他各种各样的形态来实施,能够在不脱离发明主旨的范围内进行各种省略、置换、变更。这些实施方式和/或其变形包含于发明的范围和/或主旨内,并且包含在技术方案所记载的发明及其等同范围内。

Claims (8)

1.一种半导体装置,其特征在于,
具备:
布线基板,其具有第一面及第二面;
半导体芯片,其设置于所述第一面上;
外部连接端子,其设置于所述第二面上,具备第一接地端子和第二接地端子;
密封树脂层,其设置于所述第一面上以将所述半导体芯片密封;和
导电性屏蔽层,其将所述布线基板的侧面的至少一部分和所述密封树脂层覆盖,
所述布线基板具备:
第一接地布线,其与所述导电性屏蔽层电连接;和
第二接地布线,其与所述导电性屏蔽层电连接且除去与所述导电性屏蔽层之间与所述第一接地布线电分离,
所述第一接地端子与所述第一接地布线电连接,
所述第二接地端子与所述第二接地布线电连接。
2.根据权利要求1所述的半导体装置,其特征在于,
所述布线基板还具备:
绝缘层,其设置于所述第一面和所述第二面之间;和
过孔,其贯穿所述绝缘层地设置,且与所述第一接地布线或所述第二接地布线电连接,
所述第一接地布线或所述第二接地布线及所述过孔中的至少一个在所述布线基板的侧面露出,且与所述导电性屏蔽层接触。
3.根据权利要求1或2所述的半导体装置,其特征在于,
还具备接合线,该接合线将所述布线基板的连接焊盘或所述半导体芯片与所述第一接地布线或所述第二接地布线电连接,
所述接合线在所述密封树脂层的表面露出且与所述导电性屏蔽层接触。
4.根据权利要求1或2所述的半导体装置,其特征在于,
所述第一接地布线及所述第二接地布线中的至少一个具有与所述半导体芯片的至少一部分重叠的β膜或网状膜。
5.根据权利要求3所述的半导体装置,其特征在于,
所述第一接地布线及所述第二接地布线中的至少一个具有与所述半导体芯片的至少一部分重叠的β膜或网状膜。
6.一种半导体装置的检查方法,其特征在于,
所述半导体装置具备:
布线基板,其具有第一布线及第二布线;
半导体芯片,其设置于所述布线基板的第一面上;
密封树脂层,其设置于所述第一面上以将所述半导体芯片密封;
导电层,其与所述第一布线及所述第二布线的各布线电连接,覆盖所述密封树脂层;
第一端子,其在所述布线基板的第二面上,与所述第一布线电连接;以及
第二端子,其在所述布线基板的第二面上,与所述第二布线电连接,
除去与所述导电层之间,所述第二布线与所述第一布线电分离,
所述检查方法包括:
测定所述第一端子与所述第二端子之间的电阻值,
基于所述电阻值的测定结果,检查所述第一端子以及所述第二端子与所述导电层的连接状态。
7.根据权利要求6所述的半导体装置的检查方法,其特征在于,
所述第一端子和所述第二端子的一方是用于外部连接的端子,
所述第一端子和所述第二端子的另一方是用于所述检查的端子。
8.根据权利要求6或7所述的半导体装置的检查方法,其特征在于,
在所述第一面中的与设置所述半导体芯片的区域对应的区域,配置有所述第一布线的一部分或所述第二布线的一部分。
CN201310729562.5A 2013-09-10 2013-12-26 半导体装置及半导体装置的检查方法 Active CN104425459B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013187132A JP5684349B1 (ja) 2013-09-10 2013-09-10 半導体装置および半導体装置の検査方法
JP187132/2013 2013-09-10

Publications (2)

Publication Number Publication Date
CN104425459A CN104425459A (zh) 2015-03-18
CN104425459B true CN104425459B (zh) 2017-10-20

Family

ID=52624997

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310729562.5A Active CN104425459B (zh) 2013-09-10 2013-12-26 半导体装置及半导体装置的检查方法

Country Status (4)

Country Link
US (2) US20150070046A1 (zh)
JP (1) JP5684349B1 (zh)
CN (1) CN104425459B (zh)
TW (1) TWI503931B (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5684349B1 (ja) 2013-09-10 2015-03-11 株式会社東芝 半導体装置および半導体装置の検査方法
KR20160036945A (ko) * 2014-09-26 2016-04-05 삼성전기주식회사 인쇄회로기판 및 이를 포함하는 전자부품 패키지
JP5933047B2 (ja) * 2015-01-13 2016-06-08 株式会社東芝 半導体装置の製造方法、半導体装置の検査方法、および半導体装置
US10379156B2 (en) 2015-05-29 2019-08-13 Taiwan Semiconductor Manufacturing Company, Ltd. Bump ball testing system and method
JP6418605B2 (ja) * 2015-07-31 2018-11-07 東芝メモリ株式会社 半導体装置および半導体装置の製造方法
JP6397806B2 (ja) 2015-09-11 2018-09-26 東芝メモリ株式会社 半導体装置の製造方法および半導体装置
WO2017179325A1 (ja) 2016-04-11 2017-10-19 株式会社村田製作所 高周波部品
US9793222B1 (en) 2016-04-21 2017-10-17 Apple Inc. Substrate designed to provide EMI shielding
JP6887326B2 (ja) * 2017-06-28 2021-06-16 株式会社ディスコ 半導体パッケージの形成方法
WO2019039336A1 (ja) * 2017-08-21 2019-02-28 株式会社村田製作所 電子部品モジュール及び電子部品モジュールの製造方法
CN112309873B (zh) * 2019-07-26 2023-11-10 江苏长电科技股份有限公司 电磁屏蔽封装结构及其封装方法
US11694972B2 (en) * 2020-06-09 2023-07-04 Mediatek Inc. Semiconductor package with heatsink

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5483101A (en) * 1993-12-10 1996-01-09 Nec Corporation Multilayer printed circuit board
CN1774804A (zh) * 2003-04-15 2006-05-17 波零公司 用于电子元件封装的emi屏蔽
CN102105981A (zh) * 2008-07-31 2011-06-22 斯盖沃克斯解决方案公司 半导体封装的集成干扰屏蔽罩及其制造方法
CN102610591A (zh) * 2011-01-20 2012-07-25 夏普株式会社 半导体模块
CN102623438A (zh) * 2011-01-31 2012-08-01 株式会社东芝 半导体装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6552425B1 (en) * 1998-12-18 2003-04-22 Intel Corporation Integrated circuit package
KR100691632B1 (ko) 2006-05-16 2007-03-12 삼성전기주식회사 반도체칩, 반도체칩의 제조방법 및 반도체칩 패키지
JP2008251608A (ja) 2007-03-29 2008-10-16 Casio Comput Co Ltd 半導体装置およびその製造方法
JP2009236712A (ja) * 2008-03-27 2009-10-15 Toyota Motor Corp 半導体集積回路及び半導体集積回路の検査装置、検査方法
JP2010109274A (ja) 2008-10-31 2010-05-13 Sanyo Electric Co Ltd 半導体モジュールおよび半導体モジュールの製造方法
US9362196B2 (en) 2010-07-15 2016-06-07 Kabushiki Kaisha Toshiba Semiconductor package and mobile device using the same
JP2012146882A (ja) 2011-01-13 2012-08-02 Renesas Electronics Corp 半導体装置
US8766654B2 (en) * 2012-03-27 2014-07-01 Universal Scientific Industrial Co., Ltd. Package structure with conformal shielding and inspection method using the same
US8948712B2 (en) * 2012-05-31 2015-02-03 Skyworks Solutions, Inc. Via density and placement in radio frequency shielding applications
JP5684349B1 (ja) 2013-09-10 2015-03-11 株式会社東芝 半導体装置および半導体装置の検査方法
KR102163707B1 (ko) * 2013-11-14 2020-10-08 에스케이하이닉스 주식회사 전자기간섭 차폐층을 갖는 반도체 패키지 및 테스트 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5483101A (en) * 1993-12-10 1996-01-09 Nec Corporation Multilayer printed circuit board
CN1774804A (zh) * 2003-04-15 2006-05-17 波零公司 用于电子元件封装的emi屏蔽
CN102105981A (zh) * 2008-07-31 2011-06-22 斯盖沃克斯解决方案公司 半导体封装的集成干扰屏蔽罩及其制造方法
CN102610591A (zh) * 2011-01-20 2012-07-25 夏普株式会社 半导体模块
CN102623438A (zh) * 2011-01-31 2012-08-01 株式会社东芝 半导体装置

Also Published As

Publication number Publication date
US20190244912A1 (en) 2019-08-08
TWI503931B (zh) 2015-10-11
TW201511189A (zh) 2015-03-16
US20150070046A1 (en) 2015-03-12
JP2015056427A (ja) 2015-03-23
JP5684349B1 (ja) 2015-03-11
CN104425459A (zh) 2015-03-18
US11715701B2 (en) 2023-08-01

Similar Documents

Publication Publication Date Title
CN104425459B (zh) 半导体装置及半导体装置的检查方法
CN102339817B (zh) 半导体封装以及使用其的移动设备
CN103996670B (zh) 半导体装置
TWI615065B (zh) 柔性線路板及其製作方法
CN104349575B (zh) 柔性电路板及其制作方法
US20150235966A1 (en) Wiring board and semiconductor device using the same
CN105792504B (zh) 一种具有屏蔽措施的pcb空穴埋置装置及制备工艺
CN104754855A (zh) 柔性电路板及其制作方法
CN104582240B (zh) 电路板及电路板制作方法
CN104716114A (zh) 半导体装置
CN104955260B (zh) 部件内置电路板
CN101814459A (zh) 半导体封装的安装结构及等离子体显示器件
CN105514053A (zh) 半导体封装件及其制法
WO2020057216A1 (zh) 一种内存信号测试板
TWI400012B (zh) 電路板和構造電路板的方法
JP2006261622A (ja) 集積回路パッケージ構造とそのパッケージ方法
CN103855128B (zh) 半导体装置
JP2012033786A (ja) 配線基板
CN207897217U (zh) 一种高信赖性碳墨线路板
KR102279152B1 (ko) 배선용 인터포저 및 이를 구비하는 전자 모듈
CN113015314B (zh) 电路板装置
JP5933047B2 (ja) 半導体装置の製造方法、半導体装置の検査方法、および半導体装置
TWI712358B (zh) 電路板裝置
CN101894761B (zh) 开窗型球栅阵列封装结构的基板及其制造方法
CN103426867B (zh) 适形屏蔽封装模组

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right
TA01 Transfer of patent application right

Effective date of registration: 20170803

Address after: Tokyo, Japan

Applicant after: TOSHIBA MEMORY Corp.

Address before: Tokyo, Japan

Applicant before: Toshiba Corp.

GR01 Patent grant
GR01 Patent grant
CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: Tokyo, Japan

Patentee after: TOSHIBA MEMORY Corp.

Address before: Tokyo, Japan

Patentee before: Japanese businessman Panjaya Co.,Ltd.

Address after: Tokyo, Japan

Patentee after: Kaixia Co.,Ltd.

Address before: Tokyo, Japan

Patentee before: TOSHIBA MEMORY Corp.

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20211014

Address after: Tokyo, Japan

Patentee after: Japanese businessman Panjaya Co.,Ltd.

Address before: Tokyo, Japan

Patentee before: TOSHIBA MEMORY Corp.