WO2020057216A1 - 一种内存信号测试板 - Google Patents

一种内存信号测试板 Download PDF

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Publication number
WO2020057216A1
WO2020057216A1 PCT/CN2019/093320 CN2019093320W WO2020057216A1 WO 2020057216 A1 WO2020057216 A1 WO 2020057216A1 CN 2019093320 W CN2019093320 W CN 2019093320W WO 2020057216 A1 WO2020057216 A1 WO 2020057216A1
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WIPO (PCT)
Prior art keywords
pcb substrate
test board
vias
memory
conductive strip
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PCT/CN2019/093320
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English (en)
French (fr)
Inventor
刘法志
朱黎
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郑州云海信息技术有限公司
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Publication of WO2020057216A1 publication Critical patent/WO2020057216A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/273—Tester hardware, i.e. output processing circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits

Definitions

  • the invention relates to the field of computer technology, and in particular to a memory signal test board.
  • DDR4 particles are a new generation of memory technology. Compared with DDR3 particles, DDR4 particles have more reliable transmission specifications, more reliable data reliability, and more energy-saving performance. They are increasingly used in servers and computers. However, the size of DDR4 particles is small, the chip density is high, and the wiring is dense, which makes the testing of DDR4 particles difficult. At this stage, only a small part of the signals can be derived from certain pins in the DDR4 particles for measurement, but DDR4 cannot be measured. All signals were completely tested, resulting in the test of DDR4 particles has not been carried out.
  • An object of the present invention is to provide a memory signal test board, which can perform a complete test of the memory signals through the memory signal test board.
  • the present invention provides a memory signal test board including a first PCB substrate;
  • the first PCB substrate includes a first surface and a second surface opposite to each other.
  • the first PCB substrate is provided with a plurality of first vias communicating with the first surface and the second surface.
  • a plurality of conductive strips isolated from each other are provided on a sidewall of the PCB substrate, and the conductive strips correspond to the first vias one-to-one;
  • a plurality of mutually isolated first traces are disposed in the first surface, and the first vias located in the first region of the first PCB substrate are electrically connected to the corresponding conductive strips through the first traces. connection;
  • a plurality of mutually isolated second traces are disposed in the second surface, and the first vias located in the second region of the first PCB substrate are electrically connected to the corresponding conductive strips through the second traces. connection.
  • the axis of the conductive strip is parallel to the thickness direction of the first PCB substrate; the length of the conductive strip is equal to the thickness of the first PCB substrate.
  • the conductive strip is a semi-cylindrical conductive strip
  • a sidewall of the first PCB substrate is provided with a groove corresponding to the conductive strip, and an arc surface of the conductive strip and an inner wall of the groove Phase fit.
  • the distance between adjacent conductive strips is equal.
  • the conductive strip is a copper strip.
  • test board further includes:
  • a reference layer located inside the first PCB substrate and parallel to the first surface.
  • test board further includes:
  • a first transparent protective layer located on the first surface of the first PCB substrate, covering the first trace and exposing the first via hole.
  • test board further includes:
  • a second transparent protective layer located on the second surface of the first PCB substrate, covering the second trace and exposing the first via hole.
  • the first PCB substrate is an S7038 substrate.
  • test board further includes a second PCB substrate
  • the second PCB substrate includes a third surface and a fourth surface opposite to each other.
  • the second PCB substrate is provided with a plurality of second vias communicating with the third surface and the fourth surface.
  • the third surface of the second PCB substrate and the second surface of the first PCB substrate are fixedly connected by soldering, so that the first via hole and the corresponding second via hole are electrically connected. connection.
  • a memory signal test board is provided with a plurality of through-type vias in a first PCB substrate, and two ends of the vias are respectively located on two opposite surfaces of the first PCB substrate.
  • conductive bars corresponding to the vias are provided on a one-to-one basis and are isolated from each other.
  • a plurality of first traces are provided on the first surface of the first PCB substrate, and the first traces will be located in the first area.
  • the vias are electrically connected to the corresponding conductive strips; a plurality of second traces are provided on the second surface of the first PCB substrate, and the second traces electrically connect the vias located in the second area with the corresponding conductive strips.
  • the pins of the memory are electrically connected one-to-one with the vias in the test board, and the pins of the memory are finally connected to the conductive strips on the side of the test board through the first and second traces. Electrical connection. Because the pins of the memory are relatively densely set, the density of the surface traces in the first PCB substrate can be effectively reduced by the first traces and the second traces distributed on different surfaces of the first PCB substrate; Each pin is finally electrically connected to the conductive strip on the side wall of the test board, and the signal transmitted to the conductive strip can be easily drawn out, so that each signal in the memory can be tested through the conductive strip, so as to complete the memory signal. Sex test.
  • FIG. 1 is a schematic structural diagram of a memory signal test board according to an embodiment of the present invention.
  • FIG. 2 is a top view of the memory signal test board in FIG. 1;
  • FIG. 3 is a bottom view of the memory signal test board in FIG. 1;
  • FIG. 4 is a schematic structural diagram of a specific memory signal test board according to an embodiment of the present invention.
  • FIG. 5 is a schematic structural diagram of another specific memory signal test board according to an embodiment of the present invention.
  • FIG. 6 is a top view of the second PCB substrate in FIG. 5;
  • FIG. 7 is a bottom view of the second PCB substrate in FIG. 5.
  • the core of the invention is to provide a memory signal test board.
  • the current memory such as DDR4
  • it is impossible to directly connect the leads from all the pins in DDR4 so it is impossible to connect the memory, such as DDR4.
  • Signal for integrity testing is impossible.
  • a plurality of through-type vias are provided in the first PCB substrate, and two ends of the vias are respectively located on two opposite surfaces of the first PCB substrate.
  • conductive bars corresponding to the vias are provided on a one-to-one basis and are isolated from each other.
  • a plurality of first traces are provided on the first surface of the first PCB substrate, and the first traces will be located in the first area.
  • the vias are electrically connected to the corresponding conductive strips; a plurality of second traces are provided on the second surface of the first PCB substrate, and the second traces electrically connect the vias located in the second area with the corresponding conductive strips.
  • the pins of the memory are electrically connected one-to-one with the vias in the test board, and the pins of the memory are finally connected to the conductive strips on the side of the test board through the first and second traces. Electrical connection. Because the pins of the memory are relatively densely set, the density of the surface traces in the first PCB substrate can be effectively reduced by the first traces and the second traces distributed on different surfaces of the first PCB substrate; Each pin is finally electrically connected to the conductive strip on the side wall of the test board, and the signal transmitted to the conductive strip can be easily drawn out, so that each signal in the memory can be tested through the conductive strip, so as to complete the memory signal. Sex test.
  • FIG. 1 is a schematic structural diagram of a memory signal test board according to an embodiment of the present invention
  • FIG. 2 is a top view of the memory signal test board in FIG. 1
  • the memory signal test board includes a first PCB substrate 1; the first PCB substrate 1 includes a first surface and a second surface opposite to each other, in the first PCB substrate 1 A plurality of first vias 2 communicating with the first surface and the second surface are provided. A sidewall of the first PCB substrate 1 is provided with a plurality of conductive bars 3 isolated from each other.
  • the conductive bars 3 and The first vias 2 correspond one-to-one; a plurality of mutually isolated first traces 4 are disposed in the first surface, and the first vias 2 located in the first area of the first PCB substrate 1 pass through The first trace 4 is electrically connected to the corresponding conductive strip 3; a plurality of isolated second traces 5 are disposed in the second surface, and are located in the second region of the first PCB substrate 1. The first via 2 is electrically connected to the corresponding conductive strip 3 through the second trace 5.
  • the above-mentioned first PCB substrate 1 is the main body of the entire test board.
  • the S7038 substrate is selected as the first PCB substrate 1 in the embodiment of the present invention, that is, the material of the substrate is preferably S7038. Selecting the S7038 substrate as the first PCB substrate 1 can control the impedance of the first PCB substrate 1 at about 50 ohms, thereby effectively reducing the loss of signals transmitted in the substrate.
  • a substrate of other materials may also be selected as the first PCB substrate 1.
  • the specific material of the first PCB substrate 1 is not specifically limited in the embodiment of the present invention.
  • the first PCB substrate 1 generally has two opposite surfaces, that is, the first surface and the second surface.
  • the memory is usually fixed on the first surface of the first PCB substrate 1; the circuit board on which the memory is installed is fixed on the second surface of the first PCB substrate 1, and the first PCB is passed between the memory and the circuit board Vias in the substrate 1 are electrically connected to each other.
  • the first PCB substrate 1 is provided with a plurality of first vias 2 communicating with the first surface and the second surface. That is, the first via hole 2 is a penetrating via hole, and both end surfaces of the first via hole 2 are respectively located on the first surface and the second surface of the first PCB substrate 1. Generally, the ends of the first via hole 2 on the first surface and the ends of the second via hole 2 are pads, respectively.
  • the specific structure of the first via hole 2 can be referred to the prior art, and is not described in detail in the embodiment of the present invention. It should be noted that the first vias 2 in the first PCB substrate 1 are isolated from each other, and the number and distribution of the first vias 2 need to correspond to the pins of the memory to be tested one-to-one.
  • the pins of the memory are electrically connected to the end surfaces of the corresponding vias located on the first surface of the first PCB substrate 1; and the pins of the circuit board responsible for powering the memory are located on the first PCB substrate 1
  • the end surface of the second surface is electrically connected.
  • the side walls of the first PCB substrate 1 are provided with a plurality of conductive bars 3 isolated from each other, that is, the conductive bars 3 are insulated from each other.
  • the number of the plurality of conductive bars 3 needs to be equal to the number of the first via holes 2, so that the conductive bars 3 can correspond one-to-one with the first via holes 2.
  • the axis of the conductive strip 3 is parallel to the thickness direction of the first PCB substrate 1;
  • the length of the conductive strip 3 is equal to the thickness of the first PCB substrate 1. That is, the conductive strips 3 are parallel to each other, and both end surfaces of the conductive strips 3 in the axial direction are respectively located on the first surface and the second surface of the first PCB substrate 1.
  • the memory signal test board provided in this application is a PCB board with a special structure
  • a semi-Via structure can be fabricated in the PCB board, that is, a semi-via structure can be fabricated on the edge of the first PCB substrate 1.
  • the conductive strip 3 is a semi-cylindrical conductive strip 3, that is, the structure of the conductive strip 3 is a semi-cylindrical type.
  • the side wall of the first PCB substrate 1 is provided with the semi-cylindrical conductive strip 3.
  • the inner wall of the groove is an arc surface, and the arc surface of the semi-cylindrical conductive strip 3 will adhere to the inner wall of the groove and be fixedly connected.
  • the conductive strip 3 is arranged in a semi-via structure to facilitate the manufacture of a memory signal test board.
  • the spacing between the conductive strips 3 is usually equal, that is, the conductive strips 3 are usually arranged uniformly on the first PCB substrate 1 of the side walls.
  • the conductive strip 3 is usually a copper strip. It should be noted that, in the sidewall of the first PCB substrate 1, not only the conductive strips 3 corresponding to the first vias 2 are provided, but also conductive strips 3 as ground wires may be provided. The conductive strips 3 Usually used as the ground wire of the memory signal test board.
  • the first traces 4 are located on the first surface of the first PCB substrate 1. It should be noted that the number of the first traces 4 needs to be less than the number of the first vias 2. They are isolated from each other, that is, the first traces 4 are insulated from each other.
  • the first trace 4 is used to electrically connect the first via 2 in the first region of the first PCB substrate 1 and the conductive strip 3 corresponding to the first via 2, that is, one end of the first trace 4 is
  • the first PCB substrate 1 is in contact with the first via hole 2 located in the first region, and the other end of the first trace 4 is in contact with the conductive strip 3 corresponding to the first via hole 2.
  • the second traces 5 are located on the second surface of the first PCB substrate 1. It should be noted that the number of the second traces 5 needs to be less than the number of the first vias 2, but the first traces 4 and The total number of the second traces 5 is generally equal to the number of the first vias 2.
  • the plurality of second traces 5 are isolated from each other, that is, the plurality of second traces 5 are insulated from each other.
  • the second trace 5 is used to electrically connect the first via 2 in the second region of the first PCB substrate 1 with the conductive strip 3 corresponding to the first via 2, that is, one end of the second trace 5 It is in contact with the first via hole 2 in the second area of the first PCB substrate 1, and the other end of the second trace 5 is in contact with the conductive strip 3 corresponding to the first via hole 2.
  • the one-to-one electrical connection between the first via 2 and the conductive strip 3 can be achieved through the first and second traces 4 and 5.
  • a memory signal test board is provided with a plurality of through-type vias in a first PCB substrate 1, and two ends of the vias are respectively located in two opposite ones of the first PCB substrate 1. surface.
  • a conductive strip 3 corresponding to one-to-one vias and isolated from each other is provided.
  • a plurality of first traces 4 and first traces 4 are provided.
  • the pins of the memory will be electrically connected one-to-one with the vias in the test board, and the pins of the memory will eventually be connected to the sides of the test board through the first and second traces 4 and 5.
  • the conductive strip 3 is electrically connected.
  • the pins of the memory are relatively densely arranged, the first trace 4 and the second trace 5 distributed on different surfaces of the first PCB substrate 1 can effectively reduce the density of surface traces on the first PCB substrate 1;
  • the pins in the memory are finally electrically connected to the conductive strips 3 on the side wall of the test board, and the signals transmitted to the conductive strips 3 can be easily extracted, so that the various signals in the memory can be tested through the conductive strips 3, In order to achieve the integrity test of the memory signal.
  • FIG. 4 is a schematic structural diagram of a specific memory signal test board according to an embodiment of the present invention.
  • the embodiments of the present invention further specifically limit the structure of the memory signal test board based on the foregoing embodiments of the present invention.
  • the remaining contents have been described in detail in the foregoing embodiments of the invention, and details are not described herein again.
  • the memory signal test board further includes a reference layer 6 located inside the first PCB substrate 1 and parallel to the first surface.
  • the above-mentioned first PCB substrate 1 is usually a multilayer composite structure.
  • a reference layer 6 is provided inside the first PCB substrate 1, and the reference layer 6 is generally parallel to the first surface of the first PCB substrate 1.
  • the so-called reference layer 6 is a metal layer in the first PCB substrate 1.
  • the metal layer can serve as an electrostatic shield to prevent electromagnetic radiation and avoid transmission to the first and second surfaces of the first PCB substrate 1 respectively. Interference between signals.
  • the reference layer 6 needs to have a through hole corresponding to the via hole to prevent the reference layer 6 and the via hole from being electrically connected.
  • the reference layer 6 usually needs to be electrically connected to the ground wire in the memory signal test board.
  • reference may be made to the prior art, which is not specifically limited in the embodiment of the present invention.
  • the test board further includes a first surface of the first PCB substrate 1 that covers the first trace 4 and exposes the first via 2.
  • a second transparent protective layer 8 located on the second surface of the first PCB substrate 1, covering the second trace 5 and exposing the first via hole 2.
  • the first trace 4 and the second trace 5 disposed on the surface of the first PCB substrate 1 are used to electrically connect the first via 2 to the corresponding conductive strip 3, and the first trace 4 is disposed at the first One surface and setting the second trace 5 on the second surface can also facilitate the user to observe which pin of the memory is electrically connected to which conductive strip 3 through which via, which is convenient for the user to observe and during the test Specific operations.
  • a first surface of the first PCB substrate 1 may be provided to cover the first trace 4 and expose the first trace.
  • the first transparent protective layer 7 of the via 2 ensures that while protecting the first trace 4, the first via 2 can still be electrically connected to the memory, and at the same time, the user can observe the connection position of the first trace 4. .
  • the specific material of the first transparent protective layer 7 is not specifically limited in the embodiment of the present invention, and it depends on specific situations.
  • a cover may be provided on the second surface of the first PCB substrate 1
  • the second trace 5 and the second transparent protective layer 8 of the first via 2 are exposed to ensure that the second via 5 is protected while the first via 2 can still be electrically connected to the circuit board for power supply.
  • the user can observe the connection position of the second trace 5.
  • the specific material of the above-mentioned second transparent protective layer 8 is not specifically limited in the embodiment of the present invention, and it depends on specific situations.
  • a memory signal test board provided in an embodiment of the present invention is provided with a reference layer 6 inside the first PCB substrate 1, which can function as an electrostatic shield, prevent electromagnetic radiation, and avoid transmitting to the first PCB substrate 1 separately.
  • a reference layer 6 inside the first PCB substrate 1, which can function as an electrostatic shield, prevent electromagnetic radiation, and avoid transmitting to the first PCB substrate 1 separately.
  • the first transparent protective layer 7 provided on the first surface of the first PCB substrate 1 and the second transparent protective layer 8 provided on the second surface of the first PCB substrate 1 may be While protecting the first trace 4 and the second trace 5, the user can observe the connection positions of the first trace 4 and the second trace 5, which is convenient for the user to measure the signals in the memory.
  • FIG. 5 is a schematic structural diagram of another specific memory signal test board according to an embodiment of the present invention.
  • FIG. 6 is a top view of the second PCB substrate in FIG. 5. A bottom view of the second PCB substrate in FIG. 5.
  • the embodiments of the present invention further specifically limit the structure of the memory signal test board based on the foregoing embodiments of the present invention.
  • the remaining contents have been described in detail in the foregoing embodiments of the invention, and details are not described herein again.
  • the memory signal test board further includes a second PCB substrate 9; the second PCB substrate 9 includes a third surface and a fourth surface opposite to each other, and the second PCB substrate 9 A plurality of second vias 10 communicating with the third surface and the fourth surface are provided therein, and the second vias 10 correspond to the first vias 2 one-to-one; the second PCB substrate 9 The third surface and the second surface of the first PCB substrate 1 are fixedly connected by solder 11 so that the first via hole 2 is electrically connected to the corresponding second via hole 10.
  • the second PCB substrate 9 is used to raise the first PCB substrate 1 and the memory pad in contact with the first surface of the first PCB substrate 1 during use. Similar to the first PCB substrate 1, the second PCB substrate 9 has a third surface and a fourth surface opposite to each other, and in the second PCB substrate 9, a plurality of connecting portions between the third surface and the fourth surface are provided.
  • second vias 10 that is, the second via hole 10 is a penetrating via hole, and both end surfaces of the second via hole 10 are respectively located on the third surface and the fourth surface of the second PCB substrate 9. It should be noted that, in the embodiment of the present invention, the second vias 10 need to correspond one-to-one with the first vias 2 so that the first vias 2 are electrically connected to the power supply circuit board through the second vias 10.
  • the third surface of the second PCB substrate 9 is fixedly connected to the second surface of the first PCB substrate 1 through the solder 11 so that the first via hole 2 is electrically connected to the corresponding second via hole 10.
  • the circuit board responsible for power supply will be in contact with the fourth surface of the second PCB substrate 9 and fixedly connected by the solder 11 so that each pin of the memory can pass through the first via 2 and the corresponding second via 10 Fixedly connected to the circuit board.
  • the specific material of the above-mentioned second PCB substrate 9 is not specifically limited in the embodiment of the present invention, and it depends on specific situations.
  • the commonly used memory at this stage is DDR4 particles, and the size of the DDR4 particles is usually 13.5mm * 7.5mm.
  • the size of the first PCB substrate 1 is generally 14.5mm * 9 mm, and the thinner the first PCB substrate 1 is, the better.
  • the size of the second PCB substrate 9 provided by the embodiment of the present invention is generally similar to that of the first PCB substrate 1, and is usually 14.5mm * 9mm; meanwhile, in order not to introduce a possible Via effect, the signal may be in a via hole. The back and forth reflection occurs, which affects the signal quality.
  • the thickness of the second PCB substrate 9 is usually about 1.4 mm.
  • a memory signal test board is provided with a second PCB substrate 9 for raising the first PCB substrate 1 on the second surface of the first PCB substrate 1 so as to avoid being disposed on the surface of the circuit board.
  • the obstructed components may cause obstacles to the first PCB substrate 1.

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Abstract

一种内存信号测试板，在第一PCB基板的侧壁设置有与第一过孔一一对应的导电条，第一走线将位于第一区域的过孔与对应的导电条电连接；第二走线将位于第二区域的过孔与对应的导电条电连接。在使用过程中，内存的引脚会与测试板中的过孔一一对应的电连接，并通过上述第一走线以及第二走线使得内存的引脚最终与测试板侧壁的导电条电连接。通过分布在第一PCB基板不同表面的第一走线以及第二走线可以有效降低第一PCB基板中表面走线的密度；同时将内存中的各个引脚最终电连接至测试板侧壁的导电条，而传输至导电条的信号可以方便的引出，从而实现对内存信号进行完整性测试。

Description

一种内存信号测试板
本申请要求于2018年9月19日提交中国专利局、申请号为201811093879.3、发明名称为“一种内存信号测试板”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及计算机技术领域，特别是涉及一种内存信号测试板。
背景技术
随着几年来社会不断的进步以及科技不断的发展，计算机技术得到了长足的进步。而计算机中的内存技术也是计算机领域中一个重要的组成部分。
在现阶段，DDR4颗粒是新一代的内存技术，因为DDR4颗粒相比于DDR3颗粒具备更可靠的传输规范，更可靠的数据可靠性，更节能等性能，在服务器、电脑等的使用日益增多。但是DDR4颗粒的尺寸较小，芯片密集度较高，走线密集，导致DDR4颗粒的测试比较困难，现阶段只能从DDR4颗粒中某些引脚引出很少一部分信号进行测量，而无法对DDR4全部的信号进行完整的测试，导致DDR4颗粒的测试一直没有展开。
所以如何对芯片密集度较高的内存，例如DDR4中的信号进行测试是本领域技术人员急需解决的问题。
发明内容
本发明的目的是提供一种内存信号测试板，可以通过内存信号测试板对内存的信号进行完整的测试。
为解决上述技术问题，本发明提供一种内存信号测试板，包括第一PCB基板；
所述第一PCB基板包括相对的第一表面与第二表面，所述第一PCB基板中设置有连通所述第一表面与所述第二表面的多个第一过孔，所述第一PCB基板的侧壁设置有相互隔离的多个导电条，所述导电条与所述第一 过孔一一对应；
所述第一表面中设置有多条相互隔离的第一走线，位于所述第一PCB基板第一区域的所述第一过孔通过所述第一走线与对应的所述导电条电连接；
所述第二表面中设置有多条相互隔离的第二走线，位于所述第一PCB基板第二区域的所述第一过孔通过所述第二走线与对应的所述导电条电连接。
可选的，所述导电条的轴线平行于所述第一PCB基板的厚度方向；所述导电条的长度与所述第一PCB基板的厚度相等。
可选的，所述导电条为半圆柱型导电条，所述第一PCB基板的侧壁设置有与所述导电条相对应的凹槽，所述导电条的弧面与所述凹槽内壁相贴合。
可选的，相邻所述导电条之间的间距相等。
可选的，所述导电条为铜条。
可选的，所述测试板还包括：
位于所述第一PCB基板内部，且平行于所述第一表面的参考层。
可选的，所述测试板还包括：
位于所述第一PCB基板的所述第一表面，覆盖所述第一走线且裸露所述第一过孔的第一透明保护层。
可选的，所述测试板还包括：
位于所述第一PCB基板的所述第二表面，覆盖所述第二走线且裸露所述第一过孔的第二透明保护层。
可选的，所述第一PCB基板为S7038基板。
可选的，所述测试板还包括第二PCB基板；
所述第二PCB基板包括相对的第三表面与第四表面，所述第二PCB基板中设置有连通所述第三表面与所述第四表面的多个第二过孔，所述第二过孔与所述第一过孔一一对应；
所述第二PCB基板的所述第三表面与所述第一PCB基板的所述第二表面之间通过焊料固定连接，以使所述第一过孔与对应的所述第二过孔电 连接。
本发明所提供的一种内存信号测试板，在第一PCB基板中设置有多个贯穿型过孔，该过孔的两个端部分别位于第一PCB基板中两个相对的表面。在第一PCB基板的侧壁设置有与过孔一一对应且相互隔离的导电条，在第一PCB基板的第一表面设置有多条第一走线，第一走线将位于第一区域的过孔与对应的导电条电连接；在第一PCB基板的第二表面设置有多条第二走线，第二走线将位于第二区域的过孔与对应的导电条电连接。在使用过程中，内存的引脚会与测试板中的过孔一一对应的电连接，并通过上述第一走线以及第二走线使得内存的引脚最终与测试板侧壁的导电条电连接。由于内存的引脚设置的相对比较密集，而通过分布在第一PCB基板不同表面的第一走线以及第二走线可以有效降低第一PCB基板中表面走线的密度；同时将内存中的各个引脚最终电连接至测试板侧壁的导电条，而传输至导电条的信号可以方便的引出，即可以便于通过该导电条对内存中的各个信号进行测试，从而实现对内存信号进行完整性测试。
附图说明
为了更清楚的说明本发明实施例或现有技术的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单的介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例所提供的一种内存信号测试板的结构示意图；
图2为图1中内存信号测试板的俯视图；
图3为图1中内存信号测试板的仰视图；
图4为本发明实施例所提供的一种具体的内存信号测试板的结构示意图；
图5为本发明实施例所提供的另一种具体的内存信号测试板的结构示意图；
图6为图5中第二PCB基板的俯视图；
图7为图5中第二PCB基板的仰视图。
图中：1.第一PCB基板、2.第一过孔、3.导电条、4.第一走线、5.第二走线、6.参考层、7.第一透明保护层、8.第二透明保护层、9.第二PCB基板、10.第二过孔、11.焊料。
具体实施方式
本发明的核心是提供一种内存信号测试板。在现有技术中，现阶段的内存，例如DDR4的尺寸较小，芯片密集度较高，走线密集，导致无法直接从DDR4中的全部引脚直接连接出引线，从而无法对内存，例如DDR4的信号进行完整性测试。
而本发明所提供的一种内存信号测试板，在第一PCB基板中设置有多个贯穿型过孔，该过孔的两个端部分别位于第一PCB基板中两个相对的表面。在第一PCB基板的侧壁设置有与过孔一一对应且相互隔离的导电条，在第一PCB基板的第一表面设置有多条第一走线，第一走线将位于第一区域的过孔与对应的导电条电连接；在第一PCB基板的第二表面设置有多条第二走线，第二走线将位于第二区域的过孔与对应的导电条电连接。在使用过程中，内存的引脚会与测试板中的过孔一一对应的电连接，并通过上述第一走线以及第二走线使得内存的引脚最终与测试板侧壁的导电条电连接。由于内存的引脚设置的相对比较密集，而通过分布在第一PCB基板不同表面的第一走线以及第二走线可以有效降低第一PCB基板中表面走线的密度；同时将内存中的各个引脚最终电连接至测试板侧壁的导电条，而传输至导电条的信号可以方便的引出，即可以便于通过该导电条对内存中的各个信号进行测试，从而实现对内存信号进行完整性测试。
为了使本技术领域的人员更好地理解本发明方案，下面结合附图和具体实施方式对本发明作进一步的详细说明。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
请参考图1，图2与图3，图1为本发明实施例所提供的一种内存信号测试板的结构示意图；图2为图1中内存信号测试板的俯视图；图3为图1中内存信号测试板的仰视图。
参见图1，在本发明实施例中，所述内存信号测试板包括第一PCB基板1；所述第一PCB基板1包括相对的第一表面与第二表面，所述第一PCB基板1中设置有连通所述第一表面与所述第二表面的多个第一过孔2，所述第一PCB基板1的侧壁设置有相互隔离的多个导电条3，所述导电条3与所述第一过孔2一一对应；所述第一表面中设置有多条相互隔离的第一走线4，位于所述第一PCB基板1第一区域的所述第一过孔2通过所述第一走线4与对应的所述导电条3电连接；所述第二表面中设置有多条相互隔离的第二走线5，位于所述第一PCB基板1第二区域的所述第一过孔2通过所述第二走线5与对应的所述导电条3电连接。
上述第一PCB基板1为整个测试板的主体，作为优选的，在本发明实施例中会选用S7038基板作为第一PCB基板1，即基板的材质优选为S7038。选用S7038基板作为第一PCB基板1可以将第一PCB基板1的阻抗控制在50ohm左右，从而可以有效降低基板中做传输的信号的损耗。当然，在本发明实施例中也可以选用其他材质的基板作为第一PCB基板1，有关第一PCB基板1的具体材质在本发明实施例中并不做具体限定。
上述第一PCB基板1通常具有两个相对的表面，即上述第一表面以及第二表面。在使用过程中，内存通常会固定在第一PCB基板1的第一表面；而安装内存的线路板会固定在第一PCB基板1的第二表面，上述内存与线路板之间通过第一PCB基板1中的过孔相互电连接。
上述第一PCB基板1中设置有连通所述第一表面与所述第二表面的多个第一过孔2。即上述第一过孔2为贯穿性过孔，第一过孔2的两端面分别位于第一PCB基板1的第一表面以及第二表面。通常情况下，第一过孔2位于第一表面的端部以及位于第二表面的端部分别为焊盘。有关第一过孔2的具体结构可以参照现有技术，在本发明实施例中并不做详细介绍。需要说明的是，位于第一PCB基板1中的第一过孔2之间相互隔离绝缘，且第一过孔2的数量以及分布需要与待测试的内存的引脚一一对应。在使 用过程中，内存的引脚会与对应过孔位于第一PCB基板1第一表面的端面电连接；而负责给内存供电的线路板的引脚会与对应过孔位于第一PCB基板1第二表面的端面电连接。
上述第一PCB基板1的侧壁设置有相互隔离的多个导电条3，即导电条3之间相互绝缘。而多个导电条3的数量需要与第一过孔2的数量相等，使得导电条3可以与第一过孔2一一对应。
在本发明实施例中，为了使得第一过孔2便于与对应的导电条3相互电连接，作为优选的，所述导电条3的轴线平行于所述第一PCB基板1的厚度方向；所述导电条3的长度与所述第一PCB基板1的厚度相等。即导电条3之间相互平行，且导电条3沿轴线方向的两端面分别位于第一PCB基板1的第一表面以及第二表面。
作为优选的，由于本申请中所提供的内存信号测试板为一块具有特殊结构的PCB板，而在PCB板中可以制作半Via结构，即在第一PCB基板1的边缘可以制作半过孔结构，以形成上述导电条3。在半过孔结构中，上述导电条3为半圆柱型导电条3，即导电条3的结构为半圆柱型，相应的在第一PCB基板1的侧壁设置有与半圆柱型导电条3对应的凹槽，该凹槽的内壁为一弧面，半圆柱型导电条3的弧面会与所述凹槽内壁相贴合且固定连接。将上述导电条3设置成半过孔结构便于内存信号测试板的制作。
通常情况下，为了便于后续在导电条3表面设置引线以对于测试板电连接的内存的信号进行测试，上述导电条3之间的间距通常相等，即导电条3通常均匀设置在第一PCB基板1的侧壁。通常情况下，为了降低制作成本，上述导电条3通常为铜条。需要说明的是，在第一PCB基板1的侧壁中，不仅仅设置有与第一过孔2一一对应的导电条3，还可以设置有作为地线的导电条3，该导电条3通常作为内存信号测试板的地线所使用。
参见图2，上述第一走线4位于第一PCB基板1的第一表面，需要说明的是，第一走线4的数量需要小于第一过孔2的数量，多条第一走线4之间相互隔离，即多条第一走线4之间相互绝缘。所述第一走线4用于将第一PCB基板1中位于第一区域的第一过孔2与该第一过孔2对应的导电条3电连接，即第一走线4的一端会与第一PCB基板1中位于第一区域的 第一过孔2相接触，同时第一走线4的另一端会与该第一过孔2对应的导电条3相接触。
参见图3，上述第二走线5位于第一PCB基板1的第二表面，需要说明的是，第二走线5的数量需要小于第一过孔2的数量，但第一走线4与第二走线5一共的数量通常与第一过孔2的数量相等。多条第二走线5之间相互隔离，即多条第二走线5之间相互绝缘。所述第二走线5用于将第一PCB基板1中位于第二区域的第一过孔2与该第一过孔2对应的导电条3电连接，即第二走线5的一端会与第一PCB基板1中位于第二区域的第一过孔2相接触，同时第二走线5的另一端会与该第一过孔2对应的导电条3相接触。通过上述第一走线4以及第二走线5可以实现第一过孔2与导电条3一一对应的电连接。
本发明实施例所提供的一种内存信号测试板，在第一PCB基板1中设置有多个贯穿型过孔，该过孔的两个端部分别位于第一PCB基板1中两个相对的表面。在第一PCB基板1的侧壁设置有与过孔一一对应且相互隔离的导电条3，在第一PCB基板1的第一表面设置有多条第一走线4，第一走线4将位于第一区域的过孔与对应的导电条3电连接；在第一PCB基板1的第二表面设置有多条第二走线5，第二走线5将位于第二区域的过孔与对应的导电条3电连接。在使用过程中，内存的引脚会与测试板中的过孔一一对应的电连接，并通过上述第一走线4以及第二走线5使得内存的引脚最终与测试板侧壁的导电条3电连接。由于内存的引脚设置的相对比较密集，而通过分布在第一PCB基板1不同表面的第一走线4以及第二走线5可以有效降低第一PCB基板1中表面走线的密度；同时将内存中的各个引脚最终电连接至测试板侧壁的导电条3，而传输至导电条3的信号可以方便的引出，即可以便于通过该导电条3对内存中的各个信号进行测试，从而实现对内存信号进行完整性测试。
有关上述内存信号测试板的具体结构将在下述发明实施例中做详细介绍。
请参考图4，图4为本发明实施例所提供的一种具体的内存信号测试 板的结构示意图。
区别于上述发明实施例，本发明实施例是在上述发明实施例的基础上，进一步的对内存信号测试板的结构进行具体限定。其余内容已在上述发明实施例中进行了详细介绍，在此不再进行赘述。
参见图4，在本发明实施例中，所述内存信号测试板还包括位于所述第一PCB基板1内部，且平行于所述第一表面的参考层6。
上述第一PCB基板1通常为多层复合结构，而在本发明实施例中，第一PCB基板1内部设置有一层参考层6，该参考层6通常平行于第一PCB基板1的第一表面。所谓参考层6，即第一PCB基板1中一层金属层，该金属层可以起到静电屏蔽的作用，防止电磁辐射，同时避免分别传输至第一PCB基板1第一表面与第二表面的信号之间的干扰。需要说明的是，上述参考层6中需要具有与上述过孔对应的通孔，以防止参考层6与过孔之间接触而电连接。同时，参考层6通常需要与内存信号测试板中的地线电连接。有关参考层6的具体结构以及具体材质可以参考现有技术，在本发明实施例中并不做具体限定。
作为优选的，在本发明实施例中，所述测试板还包括位于所述第一PCB基板1的所述第一表面，覆盖所述第一走线4且裸露所述第一过孔2的第一透明保护层7。以及位于所述第一PCB基板1的所述第二表面，覆盖所述第二走线5且裸露所述第一过孔2的第二透明保护层8。
上述设置在第一PCB基板1表面的第一走线4以及第二走线5除了用于将第一过孔2与对应的导电条3电连接之外，将第一走线4设置在第一表面，以及将第二走线5设置在第二表面还可以便于用户观察到内存的引脚具体是通过哪一个过孔与哪一个导电条3电连接，便于用户的观测以及在测试过程中具体的操作。而为了进一步保护上述第一走线4，使得第一走线4不易被损坏，在本发明实施例中可以在第一PCB基板1的第一表面设置覆盖第一走线4，并裸露第一过孔2的第一透明保护层7，以保证在保护第一走线4的同时，使得第一过孔2仍然可以与内存电连接，同时使得用户可以观测到第一走线4的连接位置。有关上述第一透明保护层7的具体材质在本发明实施例中并不做具体限定，视具体情况而定。
与上述第一透明保护层7相类似，为了进一步保护上述第二走线5，使得第二走线5不易被损坏，在本发明实施例中可以在第一PCB基板1的第二表面设置覆盖第二走线5，并裸露第一过孔2的第二透明保护层8，以保证在保护第二走线5的同时，使得第一过孔2仍然可以与用于供电的线路板电连接，同时使得用户可以观测到第二走线5的连接位置。有关上述第二透明保护层8的具体材质在本发明实施例中并不做具体限定，视具体情况而定。
本发明实施例所提供的一种内存信号测试板，在第一PCB基板1内部设置有参考层6，可以起到静电屏蔽的作用，防止电磁辐射，同时避免分别传输至第一PCB基板1第一表面与第二表面的信号之间发干扰；设置在第一PCB基板1第一表面的第一透明保护层7以及设置在第一PCB基板1第二表面的第二透明保护层8可以在保护第一走线4以及第二走线5的同时，使得用户可以观测到第一走线4以及第二走线5的连接位置，便于用户对内存的信号进行测量。
在具体测量过程中，在负责向内存供电的线路板表面通常设置有其他的元件，而上述元件可能会阻碍上述第一PCB基板1的设置以及阻碍在第一PCB基板1的侧壁设置引线。此时需要在第一PCB基板1的下方设置第二PCB基板，通过第二PCB基板将第一PCB基板1垫高，以避免设置在线路板表面的元件对第一PCB基板1的阻碍。有关内存信号测试板的具体内容将在下述发明实施例中做详细介绍。
请参考图5，图6以及图7，图5为本发明实施例所提供的另一种具体的内存信号测试板的结构示意图；图6为图5中第二PCB基板的俯视图；图7为图5中第二PCB基板的仰视图。
区别于上述发明实施例，本发明实施例是在上述发明实施例的基础上，进一步的对内存信号测试板的结构进行具体限定。其余内容已在上述发明实施例中进行了详细介绍，在此不再进行赘述。
参见图5，在本发明实施例中，所述内存信号测试板还包括第二PCB基板9；所述第二PCB基板9包括相对的第三表面与第四表面，所述第二 PCB基板9中设置有连通所述第三表面与所述第四表面的多个第二过孔10，所述第二过孔10与所述第一过孔2一一对应；所述第二PCB基板9的所述第三表面与所述第一PCB基板1的所述第二表面之间通过焊料11固定连接，以使所述第一过孔2与对应的所述第二过孔10电连接。
参见图6以及图7，上述第二PCB基板9用于在使用时将上述第一PCB基板1以及与第一PCB基板1第一表面接触的内存垫高。与第一PCB基板1相类似，第二PCB基板9具有相对的第三表面以及第四表面，而在第二PCB基板9中，设置有连通所述第三表面与所述第四表面的多个第二过孔10。即上述第二过孔10为贯穿性过孔，第二过孔10的两端面分别位于第二PCB基板9的第三表面以及第四表面。需要说明是，在本发明实施例中，第二过孔10需要与第一过孔2一一对应，以便第一过孔2通过第二过孔10与供电的线路板电连接。
在具体的使用过程中，第二PCB基板9的第三表面会通过焊料11与第一PCB基板1的第二表面固定连接，以使第一过孔2与对应的第二过孔10电连接。而负责供电的线路板会与第二PCB基板9的第四表面相接触，并通过焊料11固定连接，以使内存的各个引脚可以通过上述第一过孔2以及对应的第二过孔10与线路板固定连接。有关上述第二PCB基板9的具体材质在本发明实施例中并不做具体限定，视具体情况而定。
在本发明实施例中，现阶段常用的内存为DDR4颗粒，而DDR4颗粒的尺寸通常为13.5mm*7.5mm，相应的在本发明实施例中，第一PCB基板1的尺寸通常为14.5mm*9mm，而第一PCB基板1的厚度则越薄越好。而本发明实施例所提供的第二PCB基板9的尺寸通常与第一PCB基板1相类似，也通常为14.5mm*9mm；同时为了不引入可能出现的Via效应，使信号可能在过孔中发生来来回回的反射，而影响信号的质量，上述第二PCB基板9的厚度通常在1.4mm左右。
本发明实施例所提供的一种内存信号测试板，在第一PCB基板1的第二表面设置有用于将第一PCB基板1垫高的第二PCB基板9，从而避免了设置在线路板表面的元件可能对第一PCB基板1所造成的阻碍。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其它实施例的不同之处，各个实施例之间相同或相似部分互相参见即可。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上对本发明所提供的一种内存信号测试板进行了详细介绍。本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想。应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以对本发明进行若干改进和修饰，这些改进和修饰也落入本发明权利要求的保护范围内。

Claims (10)

  1. 一种内存信号测试板，其特征在于，包括第一PCB基板；
    所述第一PCB基板包括相对的第一表面与第二表面，所述第一PCB基板中设置有连通所述第一表面与所述第二表面的多个第一过孔，所述第一PCB基板的侧壁设置有相互隔离的多个导电条，所述导电条与所述第一过孔一一对应；
    所述第一表面中设置有多条相互隔离的第一走线，位于所述第一PCB基板第一区域的所述第一过孔通过所述第一走线与对应的所述导电条电连接；
    所述第二表面中设置有多条相互隔离的第二走线，位于所述第一PCB基板第二区域的所述第一过孔通过所述第二走线与对应的所述导电条电连接。
  2. 根据权利要求1所述的测试板，其特征在于，所述导电条的轴线平行于所述第一PCB基板的厚度方向；所述导电条的长度与所述第一PCB基板的厚度相等。
  3. 根据权利要求2所述的测试板，其特征在于，所述导电条为半圆柱型导电条，所述第一PCB基板的侧壁设置有与所述导电条相对应的凹槽，所述导电条的弧面与所述凹槽内壁相贴合。
  4. 根据权利要求3所述的测试板，其特征在于，相邻所述导电条之间的间距相等。
  5. 根据权利要求4所述的测试板，其特征在于，所述导电条为铜条。
  6. 根据权利要求1所述的测试板，其特征在于，所述测试板还包括：
    位于所述第一PCB基板内部，且平行于所述第一表面的参考层。
  7. 根据权利要求1所述的测试板，其特征在于，所述测试板还包括：
    位于所述第一PCB基板的所述第一表面，覆盖所述第一走线且裸露所述第一过孔的第一透明保护层。
  8. 根据权利要求1所述的测试板，其特征在于，所述测试板还包括：
    位于所述第一PCB基板的所述第二表面，覆盖所述第二走线且裸露所述第一过孔的第二透明保护层。
  9. 根据权利要求1所述的测试板，其特征在于，所述第一PCB基板为S7038基板。
  10. 根据权利要求1至9任一项权利要求所述的测试板，其特征在于，所述测试板还包括第二PCB基板；
    所述第二PCB基板包括相对的第三表面与第四表面，所述第二PCB基板中设置有连通所述第三表面与所述第四表面的多个第二过孔，所述第二过孔与所述第一过孔一一对应；
    所述第二PCB基板的所述第三表面与所述第一PCB基板的所述第二表面之间通过焊料固定连接，以使所述第一过孔与对应的所述第二过孔电连接。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11258294A (ja) * 1998-03-12 1999-09-24 Jsr Corp 回路基板の検査装置および検査方法
CN1422108A (zh) * 2001-11-27 2003-06-04 日本电气株式会社 侧面上形成测试点的印刷电路板
CN207586893U (zh) * 2018-01-02 2018-07-06 蓝思科技（长沙）有限公司 一种双面导电结构和触控面板
CN109240873A (zh) * 2018-09-19 2019-01-18 郑州云海信息技术有限公司 一种内存信号测试板

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101325840A (zh) * 2007-06-15 2008-12-17 富士康(昆山)电脑接插件有限公司 防氧化印刷电路板及其金手指和该印刷电路板的制造方法
CN201607505U (zh) * 2010-02-25 2010-10-13 深圳市普联技术有限公司 用于测试网络信号变压器参数的测试套件

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11258294A (ja) * 1998-03-12 1999-09-24 Jsr Corp 回路基板の検査装置および検査方法
CN1422108A (zh) * 2001-11-27 2003-06-04 日本电气株式会社 侧面上形成测试点的印刷电路板
CN207586893U (zh) * 2018-01-02 2018-07-06 蓝思科技（长沙）有限公司 一种双面导电结构和触控面板
CN109240873A (zh) * 2018-09-19 2019-01-18 郑州云海信息技术有限公司 一种内存信号测试板

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