JP5930980B2 - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP5930980B2 JP5930980B2 JP2013021036A JP2013021036A JP5930980B2 JP 5930980 B2 JP5930980 B2 JP 5930980B2 JP 2013021036 A JP2013021036 A JP 2013021036A JP 2013021036 A JP2013021036 A JP 2013021036A JP 5930980 B2 JP5930980 B2 JP 5930980B2
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
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- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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Description
<基板一体型電極の製造方法>
図1〜5は、本発明の本実施形態に関する半導体装置における基板一体型電極10の製造工程を示す図である。
図6は、本発明の本実施形態に関する半導体装置100の上面図である。また図7は、本発明の本実施形態に関する半導体装置100の断面図である。
図8〜図17は、本発明の本実施形態に関する半導体装置100の製造工程を示す図である。
図18〜図29は、本発明の本実施形態に関する半導体装置100の製造工程の他の態様を示す図である。以下の説明では、上記の半導体装置の製造方法1と異なる工程について説明し、半導体装置の製造方法1と同様である工程については、その説明を省略する。
図32は、本発明の前提技術に関する半導体装置102の上面図である。また図33は、本発明の前提技術に関する半導体装置101の断面図である。
図30は、本発明の本実施形態に関する変形例である半導体装置101の上面図である。また図31は、本発明の本実施形態に関する変形例である半導体装置101の断面図である。
本発明に関する実施形態によれば、半導体装置が、板状の電極部材であるプレート電極5と、プレート電極5上に設けられた一体化絶縁シートとしてのエポキシシート3と、エポキシシート3上に設けられた、制御基板としての両面プリント基板1とを備え、プレート電極5と両面プリント基板1とが、エポキシシート3によって一体に形成されている基板一体型電極10を備える。
Claims (13)
- 板状の電極部材と、
前記電極部材上に設けられた一体化絶縁シートと、
前記一体化絶縁シート上に設けられた、制御基板とを備え、
前記電極部材と前記制御基板とが、前記一体化絶縁シートによって一体に形成されている基板一体型電極を備えることを特徴とする、
半導体装置。 - 前記制御基板が、その両面に回路パターンを有し、
前記回路パターンを覆って前記制御基板上面に設けられた上面レジスト層をさらに備えることを特徴とする、
請求項1に記載の半導体装置。 - 前記上面レジスト層が設けられた位置に対応する前記電極部材下面に設けられた下面レジスト層をさらに備えることを特徴とする、
請求項2に記載の半導体装置。 - 前記一体化絶縁シートが、その表面または内部において、板または網目状の金属シールド層を有することを特徴とする、
請求項1〜3のいずれかに記載の半導体装置。 - 前記基板一体型電極と電気的に接続された、半導体素子をさらに備えることを特徴とする、
請求項1〜4のいずれかに記載の半導体装置。 - 前記基板一体型電極が前記半導体素子と接合され、当該接合される部分の周辺において開口部が形成されていることを特徴とする、
請求項5に記載の半導体装置。 - 前記基板一体型電極が前記半導体素子と接合され、当該接合される接合部において前記半導体素子側に凸形状が形成されていることを特徴とする、
請求項5または6に記載の半導体装置。 - 前記基板一体型電極が、前記半導体素子の陰極側と電気的に接続されていることを特徴とする、
請求項5〜7のいずれかに記載の半導体装置。 - (a)板状の電極部材上に一体化絶縁シートを設ける工程と、
(b)前記一体化絶縁シート上に制御基板を設け、前記電極部材と前記制御基板とを、前記一体化絶縁シートを介して一体に形成する工程と、
(c)前記工程(b)において一体に形成された基板一体型電極を、半導体素子と電気的に接続させる工程とを備えることを特徴とする、
半導体装置の製造方法。 - (d)前記工程(c)の前に、前記基板一体型電極の前記半導体素子と接合される周辺において、開口部を形成する工程をさらに備えることを特徴とする、
請求項9に記載の半導体装置の製造方法。 - (e)前記工程(c)の前に、前記基板一体型電極の前記半導体素子と接合される接合部において、前記半導体素子側に凸形状を形成する工程をさらに備えることを特徴とする、
請求項9または10に記載の半導体装置の製造方法。 - (f)前記工程(c)の前に、前記制御基板両面に回路パターンを設ける工程と、
(g)前記制御基板上面に、前記回路パターンを覆う上面レジスト層を設ける工程とをさらに備えることを特徴とする、
請求項9〜11のいずれかに記載の半導体装置の製造方法。 - (h)前記工程(g)で設けられた前記上面レジスト層の位置に対応する前記電極部材下面に、下面レジスト層を設ける工程をさらに備えることを特徴とする、
請求項12に記載の半導体装置の製造方法。
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JP2013021036A JP5930980B2 (ja) | 2013-02-06 | 2013-02-06 | 半導体装置およびその製造方法 |
DE102013219959.7A DE102013219959B4 (de) | 2013-02-06 | 2013-10-01 | Halbleitervorrichtung und Verfahren zum Herstellen derselben |
US14/061,417 US9093277B2 (en) | 2013-02-06 | 2013-10-23 | Semiconductor device and method of manufacturing the same |
CN201410045315.8A CN103972277B (zh) | 2013-02-06 | 2014-02-07 | 半导体装置及其制造方法 |
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JP6447842B2 (ja) * | 2015-02-02 | 2019-01-09 | 株式会社村田製作所 | 半導体モジュール |
JP2016162888A (ja) * | 2015-03-02 | 2016-09-05 | 株式会社デンソー | 電子装置 |
USD864968S1 (en) | 2015-04-30 | 2019-10-29 | Echostar Technologies L.L.C. | Smart card interface |
US11749633B2 (en) | 2019-04-18 | 2023-09-05 | Hitachi Energy Switzerland Ag | Power semiconductor module with laser-welded leadframe |
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