JP5975180B2 - 半導体モジュール - Google Patents
半導体モジュール Download PDFInfo
- Publication number
- JP5975180B2 JP5975180B2 JP2015540430A JP2015540430A JP5975180B2 JP 5975180 B2 JP5975180 B2 JP 5975180B2 JP 2015540430 A JP2015540430 A JP 2015540430A JP 2015540430 A JP2015540430 A JP 2015540430A JP 5975180 B2 JP5975180 B2 JP 5975180B2
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- Japan
- Prior art keywords
- wiring layer
- circuit board
- disposed
- semiconductor module
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000004065 semiconductor Substances 0.000 title claims description 105
- 239000002184 metal Substances 0.000 claims description 46
- 229910052751 metal Inorganic materials 0.000 claims description 46
- 239000000758 substrate Substances 0.000 claims description 46
- 229910000679 solder Inorganic materials 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 9
- 230000017525 heat dissipation Effects 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 description 17
- 239000011347 resin Substances 0.000 description 15
- 229920005989 resin Polymers 0.000 description 15
- 239000010949 copper Substances 0.000 description 14
- 238000007747 plating Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 13
- 239000000919 ceramic Substances 0.000 description 11
- 238000001816 cooling Methods 0.000 description 10
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- 238000005266 casting Methods 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- 238000007789 sealing Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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Description
(1)回路板52をセラミック板51の一つの面に接合するため、絶縁基板54の面積が大きくなる。
(2)電気回路の配線の一部を回路板52で行なっているため、電気回路の構成を変更する場合には回路板52のパターンを変更する必要があり、その都度、絶縁基板54と金属マスクなどの組立治具を変更する必要がある。
(3)電気回路の配線の一部を金属ワイヤ60で行なっているため、バッチ処理ができずに工程時間が長くなり、処理装置が多数必要になる。
(4)電気回路の配線を金属ワイヤ60と外部端子58で行なっているため、異なる電気回路にする場合、外部端子58の形状を変更する必要があり、外部端子58の加工に伴って金型がその都度必要になる。
(5)構成部材数(金属ワイヤ60、樹脂ケース59、蓋62およびゲル61など)が多く、製造コストが高くなる。
(6)電気回路が金属ワイヤ60と回路板52および外部端子58で構成され、金属ワイヤと対向する回路板の距離が大きいため、配線インダクタンスが大きくなる。
第1セラミック板3aおよび第2セラミック板3bは、アルミナや窒化アルミ、窒化珪素などの高熱伝導セラミックなどで構成される。また、第1回路板1a、第2回路板1b、第3回路板1c、第1金属板2a、第2金属板2bは、銅やアルミなどの高熱伝導金属で構成される。
第1半導体チップ6aは、第1配線層13aおよび第1回路板1aとの間に挟まれ、両面がはんだなどの導電性の接合材7で電気的かつ機械的に接続されている。これにより、第1配線層13aおよび第1回路板1aと、第1半導体チップ6aの両面の電極がそれぞれ電気的に接続される。
この第1半導体チップ6a及び第2半導体チップ6bのそれぞれの表裏面には良好なはんだなどの接合材7の濡れ性を高めるために導電性めっき(例えば、Ti,Ni,Auなどの金属めっき)が施されている。接合材7としては、AgペーストやCuペーストなどの導電性接着剤を用いても構わない。
第1ビア12aは、プリント基板8の絶縁板8aに形成された多数の微小な貫通孔20に金属を埋め込み、細線の柱状の導体21が集合した構造をしている。ここでは、貫通孔20の平面形状は円形の場合を示したが、これに限るものではなく、多角形やスリット状の場合もある。図4では、上下の第1配線層13a及び第3配線層13cを点線で示した。
一方、熱抵抗Rth1は、図5(a)及び図5(b)のいずれの場合も、埋め込み率が10%以下ではRth1の上昇が顕著となり好ましくない。このため、埋め込み率を10%以上にするのが望ましい。
上記結果については、第2半導体チップ6bから第2ビア12bを経由した、第1絶縁基板4への熱伝導についても同様である。そのため、第2ビア12bの埋め込み率についても、10%以上が望ましい。
尚、プリント基板8の絶縁板8aとしてセラミック板を用いると、例えば、ガラスエポキシ板などを用いる場合より熱抵抗を低減できるのでよい。その場合には、ビアはめっき以外の方法(例えばスパッタ法など)で形成すればよい。
図7に示すように、プリント基板8の両面の配線層を変更することで、異なる電気回路を容易に構成することができる。なお、図7ではB部で電流の向きが逆になり配線インダクタンスを小さくできる。
また、上記のダイオードモジュールは、容易にIGBTモジュールなどに変更することが可能である。
また、第1回路板1aや第2回路板1b、第3回路板1cと、これらに対向するプリント基板8の各配線層の電流方向を互いに逆方向にすることにより、配線インダクタンスを低減することができる。さらに、図6や図7で示した通り、プリント基板8の両面の配線層の電流方向を互いに逆方向にすることにより、配線インダクタンスを低減することができる。これは、これらの間で生じる相互誘導の効果である。
また、第1ビア12aと第1放熱部材16aを配置することで、第1半導体チップ6aから発生した熱を効果的に両面冷却することが可能となる。同様に、第2ビア12bと第2放熱部材16bを配置することで、第2半導体チップ6bから発生した熱を効果的に両面冷却することが可能となる。
まず、第1絶縁基板4及び第2絶縁基板5のそれぞれに、金属マスク30を載置する(図9(a))。
次に、金属マスク30上に、固化して接合材7になるはんだペースト7aを塗布する(図9(b))。
次に、金属マスク30を取り外すと、第1回路板1a及び第2回路板1b上にはんだペースト7aが載置される(図9(c))。
次に、上記のはんだペースト7a上に第1半導体チップ6a及び第2半導体チップ6bを載置し、図示しないリフロー炉で処理してはんだペースト7aを固化する(図9(d))。
次に、金属マスク31上にはんだペースト7aを塗布する(図10(f))。
次に、金属マスク31を取り外すと、第2回路板1b及び第3回路板1c上にはんだペースト7aが載置される(図10(g))。
次に、金属マスク33上にはんだペースト7aを塗布する(図10(i))。
次に、金属マスク33を取り外すと、プリント基板8の主面上にはんだペースト7aが載置される。
尚、上記のはんだ印刷工程は、ディスペンサーなどによりはんだペーストを塗布してもよい。
次に、プリント基板8の主面上に、第1絶縁基板4を第1回路板1aを下向きにして載置する。さらに、その上に第1絶縁基板4を固定する固定治具14を載置する(図11(l))。なお、固定治具14および固定治具15は、カーボン・セラミック材など線膨張係数が小さく、はんだが付着しない材料で構成されている。また、固定治具14および固定治具15には、第1絶縁基板4や第2絶縁基板5、プリント基板8などの位置決めができるように加工が施されている。また、固定治具14には、外部端子9を挿入するために貫通孔39が設けられている。また、対地絶縁距離を確保するために、外部端子9の下端は第2金属板2bよりも高い位置に固定する。
次に、構造体34を注型治具35bに固定し、さらに注型治具35aを被せ、その内部に熱硬化性樹脂40を注入する(図13(o))。なお、注型治具35aには、外部端子9を貫通させる貫通孔35cが設けられている。
(1)第1絶縁基板4及び第2絶縁基板5に第1半導体チップ6a及び第2半導体チップ6bを固着する工程。
(2)プリント基板8と、その両面に配置される第1絶縁基板4及び第2絶縁基板5と、外部端子9をはんだペースト7aを用いて同時に固着する工程。
(3)封止樹脂10で被覆する工程。
そのため、バッチ処理による組立工程時間の削減が可能となり、製造コストを低減できる。
図15は、第1ビア12aを形成する工程を説明した工程図である。
まず、プリント基板8の絶縁板8aに微小な貫通孔20を多数形成する(図15(a))。貫通孔20の直径は、第1配線層13aの厚さの2倍以内とする。
次に、めっき処理でCuめっき膜21aを絶縁板8aの両面に形成する。このとき、貫通孔20の直径をCuめっき膜21aの厚さ、すなわち第1配線層13aの厚さの2倍以内にすることで、貫通孔20の側壁に形成されたCuめっき膜21a同士が貫通孔20の内部で接触する(図15(b))。この接触によって貫通孔20内はCuめっき膜21aで充填されて導体21が形成される。この導体21の集合体が第1ビア12aである。
これらの工程により、第1配線層13aおよび第3配線層13cに電気的かつ機械的に接続された第1ビア12aが形成される。
ここでは、第1ビア12aはめっき法で形成した場合を示したが、スパッタ法や蒸着法などを用いても形成することもできる。
1b 第2回路板
1c 第3回路板
2a 第1金属板
2b 第2金属板
3a 第1セラミック板
3b 第2セラミック板
4 第1絶縁基板
5 第2絶縁基板
6a 第1半導体チップ
6b 第2半導体チップ
7 接合材
7a はんだペースト
8 プリント基板
8a 絶縁板
9 外部端子
10 封止樹脂
11 貫通ビア
12a 第1ビア
12b 第2ビア
13 配線層
13a 第1配線層
13b 第2配線層
13c 第3配線層
13d 第4配線層
14,15 固定治具
16a 第1放熱部材
16b 第2放熱部材
17 導電体
18 高熱伝導絶縁体
20 貫通孔
21 導体
21a Cuめっき膜
30,31,33 金属マスク
32 開口部
34 構造体
35a,35b 注型治具
37 金属層
38 凹部
39 貫通孔
40 熱硬化性樹脂
100 半導体モジュール
Claims (10)
- 絶縁板と、前記絶縁板の主面に配置された第1配線層および第4配線層と、前記主面の反対側の面に配置された第2配線層および第3配線層と、前記絶縁板内に配置され前記第1配線層及び前記第3配線層に電気的かつ機械的に接続された第1ビアと、前記絶縁板内に配置され前記第2配線層及び前記第4配線層に電気的かつ機械的に接続された第2ビアとを有するプリント基板と、
前記第1配線層に対向して配置され、前記第1配線層および前記第4配線層との対向面に第1回路板が配置される第1絶縁基板と、
前記第2配線層に対向して配置され、前記第2配線層と対向した第2回路板が配置され、前記第3配線層と対向した第3回路板が配置される第2絶縁基板と、
前記第1配線層と前記第1回路板との間に挟まれ、両面がそれぞれ導電性の接合材で固定される第1半導体チップと、
前記第2配線層と前記第2回路板との間に挟まれ、両面がそれぞれ導電性の接合材で固定される第2半導体チップと、
前記第3配線層と前記第3回路板との間に挟まれて固定された第1放熱部材と、
前記第4配線層と前記第1回路板との間に挟まれて固定された第2放熱部材と、
を備えた半導体モジュール。 - 前記絶縁板上における前記第1ビアの面積が、前記第1半導体チップの面積に対して10%以上である請求項1に記載の半導体モジュール。
- 前記絶縁板上における前記第2ビアの面積が、前記第2半導体チップの面積に対して10%以上である請求項1に記載の半導体モジュール。
- 前記第1放熱部材および前記第2放熱部材は、導電性接合材もしくは金属板で構成されている請求項1に記載の半導体モジュール。
- 前記第2回路板および前記第3回路板が一体で構成され、前記第1放熱部材が高熱伝導絶縁体で構成されている請求項1に記載の半導体モジュール。
- 前記第2絶縁基板の第2回路板が配置される面の反対面に、金属板が配置されている請求項1に記載の半導体モジュール。
- 前記第1絶縁基板の第1回路板が配置される面の反対面に、金属板が配置されている請求項1に記載の半導体モジュール。
- 前記第1ビア及び第2ビアが、前記プリント基板の絶縁板に配置された複数の貫通孔内を埋めた柱状の導体からなる請求項1に記載の半導体モジュール。
- 前記接合材および前記放熱部材が、いずれもはんだである請求項1に記載の半導体モジュール。
- 前記第1配線層もしくは第2配線層と電気的に接続されている外部端子をさらに備えた請求項1に記載の半導体モジュール。
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- 2014-08-29 DE DE112014001487.7T patent/DE112014001487B4/de not_active Expired - Fee Related
- 2014-08-29 JP JP2015540430A patent/JP5975180B2/ja not_active Expired - Fee Related
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2015
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US10978381B2 (en) | 2018-02-16 | 2021-04-13 | Denso Corporation | Semiconductor device |
Also Published As
Publication number | Publication date |
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DE112014001487T5 (de) | 2015-12-10 |
JPWO2015049944A1 (ja) | 2017-03-09 |
WO2015049944A1 (ja) | 2015-04-09 |
DE112014001487B4 (de) | 2021-03-04 |
US20160027711A1 (en) | 2016-01-28 |
US9530707B2 (en) | 2016-12-27 |
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