JP7322369B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP7322369B2 JP7322369B2 JP2018177889A JP2018177889A JP7322369B2 JP 7322369 B2 JP7322369 B2 JP 7322369B2 JP 2018177889 A JP2018177889 A JP 2018177889A JP 2018177889 A JP2018177889 A JP 2018177889A JP 7322369 B2 JP7322369 B2 JP 7322369B2
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- solder
- semiconductor device
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Description
第1の実施の形態の半導体装置の製造方法について、図1及び図2を用いて説明する。図1は、第1の実施の形態の半導体装置の製造方法を説明するための図である。なお、図1(A)~図1(C)は、半導体装置の製造方法に含まれる準備工程と塗布工程と接合工程とをそれぞれ表している。図2は、第1の実施の形態の半導体装置の製造方法における塗布工程を説明するための図である。図1及び図2は、半導体装置の製造工程中の要部を側断面視で示した図である。
第2の実施の形態では第1の実施の形態の半導体装置についてより具体的に図3及び図4を用いて説明する。図3は、第2の実施の形態の半導体装置の要部断面図である。なお、図3に示す半導体装置10は、半導体装置10に含まれるセラミック回路基板11の断面の端部を拡大して表示している。また、図4は、第2の実施の形態の半導体装置のコンタクト部品を示す図である。なお、図4(A)は、コンタクト部品17の上面図を、図4(B)は、図4(A)の一点鎖線X-Xにおける断面図をそれぞれ表している。
第3の実施の形態では第2の実施の形態において配線部材として金属ブロックを用いた半導体装置について図6を用いて説明する。図6は、第3の実施の形態の半導体装置の要部断面図である。なお、図6に示す半導体装置10aは、半導体装置10aに含まれるセラミック回路基板11近傍の断面の端部を拡大して表示している。また、半導体装置10aが含む構成は、半導体装置10と同じ構成には同じ符号を付して、その詳細な説明については省略、または簡略化する。
第4の実施の形態では第2の実施の形態において配線部材に代わって電子部品を用いた半導体装置について図7を用いて説明する。図7は、第4の実施の形態の半導体装置の要部断面図である。なお、図7に示す半導体装置10bは、半導体装置10bに含まれるセラミック回路基板11近傍の断面の端部を拡大して表示している。また、半導体装置10bが含む構成は、半導体装置10,10aと同じ構成には同じ符号を付して、その詳細な説明については省略、または簡略化する。
第5の実施の形態ではセラミック回路基板11上に半導体チップとコンタクト部品と電子部品を配置させた半導体装置について図9を用いて説明する。図9は、第5の実施の形態の半導体装置の要部断面図である。なお、図9に示す半導体装置10cは、半導体装置10cに含まれるセラミック回路基板11近傍の断面の端部を拡大して表示している。また、半導体装置10cが含む構成は、半導体装置10,10a,10bと同じ構成には同じ符号を付して、その詳細な説明については省略、または簡略化する。
1a 第1配置領域
1b 第2配置領域
2a 第1接合部材
2b 第2接合部材
3a 第1部品
3b 第2部品
4,51 第1マスク
4a 第1開口
5,52 第2マスク
5a 第2開口
10,10a,10b,10c 半導体装置
11 セラミック回路基板
12 絶縁板
13 金属板
14a,14b,14c,14d,14e 回路パターン
14a1 チップ配置領域
14a2 配線配置領域
14a4 凹部
14b1 部品配置領域
14c1 段差
15a,15b,15c,15d はんだ
16 半導体チップ
17 コンタクト部品
17a 胴体部
17b 中空孔
17b1,17b2 開口端部
18 金属ブロック
19 電子部品
21 放熱板
22 リードフレーム
22a,22b 接続部
23 ケース
24 外部接続端子
24a 内部接続部
24b 外部接続部
51a,55a 配線開口
52a,54a,57a チップ開口
53 第3マスク
53a,56a 部品開口
54 第4マスク
54b,57b 脚部
55 第5マスク
56 第6マスク
57 第7マスク
Claims (6)
- おもて面に第1配置領域と前記おもて面に形成された凹部の底面に前記第1配置領域よりも低位の第2配置領域とがそれぞれ設定された導電板を用意する準備工程と、
前記第1配置領域に第1接合部材を塗布し、前記第2配置領域に前記第1配置領域を越えない高さで前記第1接合部材よりも液相線温度が高い第2接合部材を塗布する塗布工程と、
前記第1配置領域に前記第1接合部材を介して半導体チップである第1部品を接合し、前記第2配置領域に前記第2接合部材を介して配線部品である第2部品を接合する接合工程と、
を有し、
前記塗布工程は、
前記第1配置領域よりも低位の前記第2配置領域に対応した第1開口が形成された第1マスクを前記導電板の前記おもて面に配置して、前記第1開口を介して前記第2接合部材を塗布する工程と、
前記第2接合部材の塗布後、前記第1マスクを取り除き、前記第2接合部材を加熱することなく、前記第1配置領域に対応した第2開口が形成され、前記導電板の前記おもて面に対向する面が平坦を成す第2マスクを前記導電板の前記おもて面に配置して、前記第2接合部材を覆って、前記第2開口を介して前記第1接合部材を塗布する工程と、
を有する、
半導体装置の製造方法。 - 前記第1接合部材及び前記第2接合部材ははんだであって、
前記第2接合部材は、前記第1接合部材に対してフラックス材の量及びフラックス材の成分の少なくとも一つが異なる、
請求項1に記載の半導体装置の製造方法。 - 前記第2接合部材は、前記第1接合部材よりもフラックス材の量が少ない、
請求項2に記載の半導体装置の製造方法。 - 前記配線部品は、内部に中空孔が形成された筒状のコンタクト部品、接続ピンまたはリードフレームである、
請求項1乃至3のいずれかに記載の半導体装置の製造方法。 - おもて面に第1配置領域と前記おもて面に形成された凹部の底面に前記第1配置領域よりも低位の第2配置領域とがそれぞれ設定された導電板を用意する準備工程と、
前記第1配置領域に第1接合部材を塗布し、前記第2配置領域に前記第1接合部材と異なる第2接合部材を塗布する塗布工程と、
前記第1配置領域に前記第1接合部材を介して、スイッチング素子またはダイオードを含む半導体チップである第1部品を接合し、前記凹部内の前記第2配置領域に前記第2接合部材を介して、筒状のコンタクト部品、接続ピンまたはリードフレームである第2部品を接合する接合工程と、
を有し、
前記第1接合部材及び前記第2接合部材ははんだであって、
前記第2接合部材は、前記第1接合部材に対して、フラックス材の量が少ない、
半導体装置の製造方法。 - 前記第1接合部材の濡れ性は前記第2接合部材の濡れ性よりも大きい、
請求項5に記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018177889A JP7322369B2 (ja) | 2018-09-21 | 2018-09-21 | 半導体装置の製造方法 |
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