JP7156155B2 - 半導体モジュール - Google Patents
半導体モジュール Download PDFInfo
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- JP7156155B2 JP7156155B2 JP2019080267A JP2019080267A JP7156155B2 JP 7156155 B2 JP7156155 B2 JP 7156155B2 JP 2019080267 A JP2019080267 A JP 2019080267A JP 2019080267 A JP2019080267 A JP 2019080267A JP 7156155 B2 JP7156155 B2 JP 7156155B2
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Description
図1は、実施の形態1に係る半導体モジュールを示す断面図である。絶縁基板1は、絶縁板1aと、絶縁板1aの下面に設けられた導体1bと、絶縁板1aの上面に設けられた導体1cとを有する。絶縁基板1の上方に絶縁基板2が配置されている。絶縁基板2は、絶縁板2aと、絶縁板2aの下面に設けられた導体2bと、絶縁板2aの上面に設けられた導体2cとを有する。なお、本願明細書では、図1の断面図における上側の面を「上面」、下側の面を「下面」と記載する。
図3は、実施の形態2に係る半導体モジュールを示す断面図である。本実施の形態では、実施の形態1の絶縁基板2を銅又はアルミニウム等の金属ブロック13に変更している。金属ブロック13は半導体素子5の上面電極に接続されている。封止樹脂12の一部12aが金属ブロック13の上面を覆っている。
図5は、実施の形態3に係る半導体モジュールを示す断面図である。本実施の形態では、半導体素子15が絶縁基板7に設けられている。半導体素子15の上面電極は絶縁基板7の導体7bにはんだ等のろう材16により接続され、ろう材17により絶縁基板1の導体1cに接続されている。このようにモジュール内部の絶縁基板7にも半導体素子15を設けることにより半導体モジュールの高電流密度化が可能となる。その他の構成及び効果は実施の形態1と同様である。なお、実施の形態2のように絶縁基板1,2を金属ブロック13,14に変更してもよい。
図6は、実施の形態4に係る半導体モジュールを示す断面図である。絶縁基板1と絶縁基板7との間の隙間を確保する銅等の金属のスペーサー18が設けられている。絶縁基板2と絶縁基板7との間の隙間を確保する銅等の金属のスペーサー19が設けられている。スペーサー18は絶縁基板1,7の導体1c,7bとろう材により接続されている。スペーサー19は絶縁基板2,7の導体2b,7bとろう材により接続されている。
図7は、実施の形態5に係る半導体素子と絶縁基板の接合部を拡大した断面図である。実施の形態1~4の半導体モジュールにおいて、絶縁基板7の導体7bにろう材9との接合領域を制御するためのレジスト等の絶縁膜20を設ける。そして、絶縁膜20の開口面積を半導体素子3の上面電極の面積より小さくする。このように接合領域を制御することでろう材9が溶けた際に台形のような形になり、ろう材9と半導体素子3の接続面積がろう材9と絶縁基板7の導体7bの接続面積より大きくなる。半導体素子5と絶縁基板7の接合部も同様である。このようにろう材9の形状を制御することで、半導体素子3,5に付与される応力を低減することができる。
Claims (8)
- 第1の絶縁板と、
前記第1の絶縁板の上方に配置された第2の絶縁板と、
前記第1の絶縁板の上面に設けられた第1の半導体素子と、
前記第2の絶縁板の下面に設けられた第2の半導体素子と、
前記第1の絶縁板と前記第2の絶縁板の間に配置された第3の絶縁板と、前記第3の絶縁板の表面に設けられ前記第1及び第2の半導体素子に接続された導体とを有する絶縁基板と、
前記第1及び第2の半導体素子と前記絶縁基板を封止する封止樹脂とを備え、
前記第3の絶縁板の絶縁耐圧は前記第1及び第2の絶縁板の絶縁耐圧より低いことを特徴とする半導体モジュール。 - 前記第1の絶縁板を有し、下面が前記封止樹脂から露出した第1の絶縁基板と、
前記第2の絶縁板を有し、上面が前記封止樹脂から露出した第2の絶縁基板とを更に備えることを特徴とする請求項1に記載の半導体モジュール。 - 前記第2の半導体素子の上面に接続された第1の金属ブロックを更に備え、
前記第2の絶縁板は、前記第1の金属ブロックの上面を覆う前記封止樹脂の一部であることを特徴とする請求項1に記載の半導体モジュール。 - 前記第1の半導体素子の下面に接続された第2の金属ブロックを更に備え、
前記第1の絶縁板は、前記第2の金属ブロックの下面を覆う前記封止樹脂の一部であることを特徴とする請求項1又は3に記載の半導体モジュール。 - 前記絶縁基板に設けられた第3の半導体素子を更に備えることを特徴とする請求項1~4の何れか1項に記載の半導体モジュール。
- 前記第1又は第2の絶縁板と絶縁基板との間の隙間を確保するスペーサーを更に備えることを特徴とする請求項1~5の何れか1項に記載の半導体モジュール。
- 前記第1又は第2の半導体素子を前記絶縁基板の前記導体に接続するろう材を更に備え、
前記ろう材と前記第1又は第2の半導体素子の接続面積は、前記ろう材と前記絶縁基板の前記導体の接続面積より大きいことを特徴とする請求項1~6の何れか1項に記載の半導体モジュール。 - 前記第1及び第2の半導体素子はワイドバンドギャップ半導体によって形成されていることを特徴とする請求項1~7の何れか1項に記載の半導体モジュール。
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