JP2019067949A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2019067949A JP2019067949A JP2017192699A JP2017192699A JP2019067949A JP 2019067949 A JP2019067949 A JP 2019067949A JP 2017192699 A JP2017192699 A JP 2017192699A JP 2017192699 A JP2017192699 A JP 2017192699A JP 2019067949 A JP2019067949 A JP 2019067949A
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- insulating substrate
- metal layer
- semiconductor element
- semiconductor device
- layer
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Abstract
Description
12:封止体
14、214、314:P端子
15:N端子
16:O端子
18、19:信号端子
20、40、:半導体素子
22、42:上側絶縁基板
24、44:導体スペーサ
26、46、226、326:下側絶縁基板
28、48:上側絶縁基板の絶縁層
30、50:上側絶縁基板の内側金属層
32、52:上側絶縁基板の外側金属層
34、54:下側絶縁基板の絶縁層
36、56、236、336:下側絶縁基板の内側金属層
36c、56c:内側金属層の周側面
38、58:下側絶縁基板の外側金属層
60、260、360:継手
70:冷却器
72:放熱グリス
74:絶縁板
122:共通上側絶縁基板
126:共通下側絶縁基板
128:共通上側絶縁基板の共通絶縁層
130、150:共通上側絶縁基板の第1内側金属層
132:共通上側絶縁基板の共通外側金属層
134:共通下側絶縁基板の共通絶縁層
136、156:共通下側絶縁基板の内側金属層
138:共通下側絶縁基板の共通外側金属層
202、302:U端子
204、304:V端子
206、306:W端子
400:パワーユニット
410:第2の半導体装置
422、426、442、446:放熱板
CA1、CA2:接触面積
CD:沿面距離
D1:パワーユニットに採用された本実施例の半導体装置の厚み
D2:パワーユニットに採用された第2の半導体装置の厚み
TH1:下側絶縁基板の内側金属層の厚み
TH2:下側絶縁基板の外側金属層の厚み
WL:溶接による接合箇所
Claims (8)
- 絶縁層の両面に金属層がそれぞれ設けられた第1絶縁基板と、
前記第1絶縁基板の一方側の金属層上に配置された第1半導体素子と、
絶縁層の両面に金属層がそれぞれ設けられた第2絶縁基板と、
前記第2絶縁基板の一方側の金属層上に配置された第2半導体素子と、
前記第1半導体素子及び前記第2半導体素子を封止する封止体と、
を備え、
前記第1絶縁基板の他方側の金属層及び前記第2絶縁基板の他方側の金属層は、前記封止体の平坦な第1表面に露出している、半導体装置。 - 絶縁層の両面に金属層がそれぞれ設けられた第3絶縁基板と、
絶縁層の両面に金属層がそれぞれ設けられた第4絶縁基板と、をさらに備え、
前記第3絶縁基板は、前記第1半導体素子を挟んで前記第1絶縁基板と対向しているとともに、一方側の金属層が前記第1半導体素子へ電気的に接続されており、
前記第4絶縁基板は、前記第2半導体素子を挟んで前記第2絶縁基板と対向しているとともに、一方側の金属層が前記第2半導体素子へ電気的に接続されており、
前記第3絶縁基板の他方側の金属層及び前記第4絶縁基板の他方側の金属層は、前記封止体の前記第1表面とは反対側に位置する平坦な第2表面に露出している、請求項1に記載の半導体装置。 - 前記第1半導体素子と前記第3絶縁基板との間に配置された第1導体スペーサと、
前記第2半導体素子と前記第4絶縁基板との間に配置された第2導体スペーサと、をさらに備え、
前記第1導体スペーサ及び前記第2導体スペーサの各線膨張係数は、前記第1絶縁基板及び前記第2絶縁基板の前記金属層の線膨張係数よりも小さく、かつ、前記封止体の線膨張係数よりも小さい、請求項2に記載の半導体装置。 - 前記第1絶縁基板及び前記第2絶縁基板の前記金属層の材料は銅であり、
前記第1導体スペーサ及び前記第2導体スペーサの材料は、銅−モリブデン合金又は銅−タングステン合金である、請求項3に記載の半導体装置。 - 前記第1絶縁基板と前記第2絶縁基板の少なくとも一方では、前記一方側の金属層の厚みの方が、前記他方側の金属層の厚みよりも大きい、請求項1から4のいずれか一項に記載の半導体装置。
- 前記第1絶縁基板と前記第2絶縁基板の少なくとも一方では、前記他方側の金属層の厚みの方が、前記一方側の金属層の厚みよりも大きい、請求項1から4のいずれか一項に記載の半導体装置。
- 前記第1絶縁基板と前記第2絶縁基板の少なくとも一方では、前記一方側の金属層の厚みの方が、前記他方側の金属層の厚みと等しい、請求項1から4のいずれか一項に記載の半導体装置。
- 前記第1絶縁基板と前記第2絶縁基板の少なくとも一方は、DBC基板である、請求項1から7のいずれか一項に記載の半導体装置。
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US16/146,340 US10777488B2 (en) | 2017-10-02 | 2018-09-28 | Semiconductor device including conductive spacer with small linear coefficient |
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