JP5817696B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP5817696B2 JP5817696B2 JP2012220379A JP2012220379A JP5817696B2 JP 5817696 B2 JP5817696 B2 JP 5817696B2 JP 2012220379 A JP2012220379 A JP 2012220379A JP 2012220379 A JP2012220379 A JP 2012220379A JP 5817696 B2 JP5817696 B2 JP 5817696B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- semiconductor device
- output bus
- bus bar
- switching element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
Claims (3)
- エミッタ電極とゲート電極とコレクタ電極とがともに設けられた第1電極面を有するスイッチング素子と、
前記スイッチング素子に積層されるように配置され、アノード電極とカソード電極とがともに設けられた第2電極面を有する整流素子と、
前記コレクタ電極及び前記カソード電極に接続された第1出力バスバと、
前記エミッタ電極及び前記アノード電極に接続された第2出力バスバと、を備え、
前記スイッチング素子及び前記整流素子は、前記第1電極面と前記第2電極面とが対向するように向き合って配置され、
前記第1及び第2出力バスバは、前記スイッチング素子及び前記整流素子に挟まれるように配置されている、
ことを特徴とする半導体装置。 - 前記スイッチング素子が接続された第1放熱板と、
前記整流素子が接続された第2放熱板と、を更に備え、
前記第1放熱板は、前記スイッチング素子において前記第1電極面の反対側の面と接しており、
前記第2放熱板は、前記整流素子において前記第2電極面の反対側の面と接している、
ことを特徴とする請求項1に記載の半導体装置。 - 前記ゲート電極に接続された信号ターミナルを更に備え、
前記信号ターミナルは、前記第1及び第2出力バスバよりも厚さが薄い、
ことを特徴とする請求項1又は2に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012220379A JP5817696B2 (ja) | 2012-10-02 | 2012-10-02 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012220379A JP5817696B2 (ja) | 2012-10-02 | 2012-10-02 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014075376A JP2014075376A (ja) | 2014-04-24 |
JP5817696B2 true JP5817696B2 (ja) | 2015-11-18 |
Family
ID=50749354
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012220379A Expired - Fee Related JP5817696B2 (ja) | 2012-10-02 | 2012-10-02 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5817696B2 (ja) |
-
2012
- 2012-10-02 JP JP2012220379A patent/JP5817696B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2014075376A (ja) | 2014-04-24 |
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